CN112164676A - Circuit board and packaging body - Google Patents

Circuit board and packaging body Download PDF

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Publication number
CN112164676A
CN112164676A CN202010736984.5A CN202010736984A CN112164676A CN 112164676 A CN112164676 A CN 112164676A CN 202010736984 A CN202010736984 A CN 202010736984A CN 112164676 A CN112164676 A CN 112164676A
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CN
China
Prior art keywords
circuit board
solder mask
mask layer
jointed
circuit
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Pending
Application number
CN202010736984.5A
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Chinese (zh)
Inventor
王忠宝
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Individual
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Individual
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Publication of CN112164676A publication Critical patent/CN112164676A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The invention discloses a circuit board and a packaging body, wherein the circuit board mainly comprises an end point and a solder mask layer, wherein the surface of the circuit board which is jointed with plastic is composed of the solder mask layer except the surface of the end point, the solder mask layer has a flat surface, and the jointing quality and the cost are superior to those of an insulating layer, so that the quality of the packaging body is better and the cost is lower.

Description

Circuit board and packaging body
Technical Field
The present invention relates to the field of circuit boards and semiconductor packaging technologies, and in particular, to a package for a semiconductor and a circuit board.
Background
Fig. 9A and 9B are cross-sectional views of a conventional circuit board and a conventional package.
The package 10 includes a circuit board 60, a chip 20, a conductive member 28, and a plastic 45.
The circuit board 60 has; the terminal 30, the circuit 70, the connecting member 78, the passivation 77, the solder mask 90, the insulating layer 40 and the insulating layer 4A.
The terminal (terminal)30 is copper and provides electrical communication to the outside, and has an upper surface 31, a lower surface 32, and sides 33.
The insulating layer 40 has an upper surface 41 and a lower surface 42 and is made of GHPL830NS from Mitsubishi gas corporation or other BT (Bismaleimide Triazinesin) resin.
The insulating layer 40 covers the lower surface 32 and the side 33 of the terminal 30, and the upper surface 31 of the terminal 30 is exposed outside the insulating layer 40.
The trace 70 engages the lower surface 42 of the insulating layer 40 and is in electrical communication with the terminal 30 via a connector 78 housed within the insulating layer 40.
The solder mask 90 is made of AUS308 from sun ink or other solder mask (solder mask) and has an upper surface 91, a lower surface 92, and sides 93. the solder mask 90 is bonded to the upper surface 41 of the insulating layer 40, and the upper surface 31 of the terminal 30 needs to be provided with a passivation 77 to prevent the terminal 30 from being oxidized.
The passivation layer 77 is an organic solder resist (organic solder resist), and the insulating layer 4A, the insulating layer 4A and the lower surface 42 of the insulating layer 40 are bonded to each other and cover the wiring 70.
In addition, when the design value of the thickness T6 of the circuit board 60 is 110 ± 30 micrometers (μm), the rigidity is not enough to cause the extrusion damage when in use, so that it is necessary to add a carrier 80 to increase the rigidity of the circuit board 60 to avoid the extrusion damage, the carrier 80 is removed before the manufacturing process of the package 10 is completed, the carrier 80 has an upper surface 81 and a lower surface 82, the upper surface 81 is connected with the lower surface 62 of the circuit board 60, the structure of the carrier 80 is designed to be composed of five layers of metal components 8C and 8E and three layers of insulating components 8D, the design value of the thickness T of the carrier 80 is 260 ± 40 μm, and the component 8C connected with the circuit board 60, the structure of the component 8C connected with the component 8E has the detachable effect, during the process of removing the carrier 80, the component 8E is removed first, and the component 8C is still connected with the circuit board 60, the component 8C is then removed to expose the lower surface 62 of the circuit board 60 to the atmosphere.
The chip 20 has an upper surface 21, a lower surface 22 and connection pads 24, and is disposed on an upper surface 61 of the circuit board 60.
The conductive member 28 is implemented as a copper bump (copper pillar bump) composed of a component 2P implemented as a copper pillar (copper pillar) and a component 2S implemented as tin bonded, wherein one end of the component 2P is bonded to the connection pad 24 of the chip 20 and the component 2S is in electrical communication with the terminal 30 of the circuit board 60, so that the chip 20 is in electrical communication with the circuit board 60.
The plastic 45 is an insulator that engages the upper surface 61 of the circuit board 60 and encapsulates the chip 20 and the conductive member 28.
The above package 10 has the following disadvantages to be improved:
1) when the package 10 needs to use the circuit board 60, the surface of the passivation layer 77 needs to be coated with flux (flux), and then the passivation layer 77 is removed by a heating and cleaning process, and when the conductive element 28 is to be bonded to the upper surface 31 of the terminal 30, the flux needs to be reused to improve the bonding quality between the conductive element 28 and the terminal 30, and water or a cleaning agent needs to be used to remove the contaminants M such as flux or dust remaining on the upper surface 61 of the circuit board 60, however, since the upper surface 91 of the solder mask layer 90 usually protrudes 20 μ M above the upper surface 41 of the insulating layer 40, the contaminants M are accumulated on the side 93 of the solder mask layer 90 and are not easily removed, and the plastic 45 and the circuit board 60 are damaged by peeling due to the contaminants M.
2) The quality is not good, because the quality of the bonding between the plastic 45 and the solder mask 90 is better than the quality of the bonding between the insulating layer 40 due to the material characteristics, therefore, the plastic 45 preferably does not have a joint with the insulating layer 40, but the circuit board 60 is limited by the height and cost of the conductive member 28, and the insulating layer 40 is exposed to the atmosphere at least in the region corresponding to the upper surface 21 of the chip 20, whereby there is a risk of peeling off and damaging the plastic 45 and the upper surface 41 of the insulating layer 40.
3) Although the carrier plate 80 can improve the rigidity of the circuit board 60, the circuit board 60 with the thickness of 110 microns is matched with the carrier plate 80 with the thickness of 260 microns, so that the rigidity of the total thickness of 370 microns is excessively stressed, because the thickness T6 of the circuit board 60 is usually larger than 136 microns, the requirement of the circuit board 60 on the rigidity can be met, therefore, the carrier plate 80 is excessively used and is not environment-friendly, the production efficiency is reduced due to the excessively large thickness T, and the cost of the circuit board 60 is increased to cause waste.
Disclosure of Invention
The technical scheme provided by the invention is as follows:
a circuit board is mainly composed of an end point and a solder mask layer, wherein the end point is provided with an upper surface, a lower surface and a side edge, the solder mask layer is provided with an upper surface and a lower surface, the solder mask layer is at least jointed with the side edge of the end point, and the surface of the circuit board jointed with the packaging body by plastics is made to be the solder mask layer except the surface of the end point, so that the quality of the circuit board jointed with the plastics is better, or the circuit board can be jointed with a support plate to improve the rigidity of the circuit board, or the warping (warp) degree is adjusted, or the arrangement of a protective layer is reduced, so that the circuit board has higher.
A circuit board and a carrier board are provided, the circuit board includes an end point, an insulating layer, a circuit, a conductive layer, a solder mask layer, a passivation layer and a carrier board. The terminal is used for external electrical connection and has an upper surface, a lower surface and a side edge. The insulating layer has an upper surface and a lower surface, and the insulating layer covers the lower surface and the side edges of the end points, and the upper surface of the end points is exposed and does not protrude out of the upper surface of the insulating layer. The circuit is jointed with the lower surface of the insulating layer and is electrically communicated with the end point by a conductive piece accommodated in the insulating layer; the solder mask layer is provided with an upper surface and a lower surface, the solder mask layer covers the circuit and is connected with the lower surface of the insulating layer, and part of the lower surface of the circuit is exposed in the atmosphere. The protective layer is embodied as a conductor and is arranged on the surface of the line which is exposed to the atmosphere. Meanwhile, the upper surfaces of the insulating layer and the terminal are implemented as the upper surface of the circuit board. The carrier plate is provided with an upper surface and a lower surface, at least consists of a first metal element, and the carrier plate is jointed with the upper surface of the circuit board.
A package at least comprises a circuit board, a chip, a conductive piece and plastic. The circuit board at least comprises a solder mask layer and an end point, and comprises an upper surface and a lower surface. Wherein, the upper surface of the circuit board consists of an upper surface of the end point and an upper surface of the solder mask layer; the end point comprises an upper surface, a lower surface and a side edge; the solder mask layer comprises an upper surface and a lower surface, wherein the upper surface of the solder mask layer is flat, the solder mask layer is at least jointed with the side edge of the endpoint, and the upper surface of the endpoint is exposed on the upper surface of the solder mask layer; the plastic is jointed with the upper surface of the circuit board, the plastic wraps the chip and the conductive piece, and the chip connecting pad and the end point of the circuit board are respectively jointed with one end of the conductive piece to enable the chip to be electrically communicated with the circuit board.
A method for manufacturing a package body comprises the following steps:
the method comprises the following steps: providing a circuit board and a carrier plate, wherein the circuit board comprises a solder mask layer and an end point, and the circuit board is provided with an upper surface and a lower surface; the upper surface of the circuit board consists of the upper surfaces of the end points and the upper surface of the solder mask layer; the end point comprises an upper surface, a lower surface and a side edge; the solder mask layer comprises an upper surface and a lower surface, wherein the upper surface of the solder mask layer is flat; the solder mask layer is at least jointed with one part of the side edge of the endpoint, and the upper surface of the endpoint is exposed out of the upper surface of the solder mask layer; the carrier plate comprises an upper surface and a lower surface, the carrier plate is jointed with the upper surface of the circuit board, and the jointed surface of the carrier plate and the circuit board consists of metal elements;
step two: providing a removing procedure to remove the carrier plate and expose the upper surface of the circuit board in the atmosphere;
step three: providing a chip and a conductive piece, wherein the chip is arranged on the upper surface of the circuit board, and the chip connecting pad and the end point of the circuit board are respectively jointed with one end point of the conductive piece so as to lead the chip to be electrically communicated with the conductive piece; and;
step four: providing a filling process and plastic to make the plastic joint with the upper surface of the circuit board and make the plastic cover the chip and the conductive piece.
Drawings
The invention is further described with reference to the following figures and examples:
fig. 1A to 1B and fig. 2A to 2B are: a circuit board and a package body are in a cross-sectional view;
fig. 3 to 6 are: a circuit board cross-sectional view;
fig. 7A to 7E are: a cross-sectional view of the carrier plate;
fig. 8A to 8B are: a method for manufacturing the package;
fig. 9A to 9B are: the circuit board and the package body are cut in the prior art.
Wherein the various symbols in the drawings are:
10. 1A, 1b. 18. A.electrical conductor;
20. a chip and connection pads; 21. 31, 41, 61, 71, 81, 91, upper surface;
2P, 2S, 8C, 8D, 8e. 22. 32, 42, 62, 72, 82, 92 lower surface;
30. 3A, 3B, 3c.. end points; 33. 93..
40. An insulating layer; 44. 94........... hole opening;
reserving an opening hole; 60. 6A, 6B, 6c.. circuit board;
70. a 75. 77..
78........... a connector; 80. A.
88......... recess; 90. 9a.
A. T, T6.
Detailed Description
As shown in fig. 1A and 1B, which are cross-sectional views of a circuit board and a package, the package 1A includes a circuit board 6A, a chip 20, a conductive member 28, and a plastic 45, the circuit board 6A has: the terminal 3A, the solder mask layer 9A, the circuit 70, the connecting member 78, the insulating layer 40 and the insulating layer 4A, wherein the terminal 3A is a conductor of copper, nickel or tin, and is used for external electrical connection, and has an upper surface 31, a lower surface 32 and a side 33, the solder mask layer 9A is an insulator, and is usually made of AUS308 of solar ink company or other solder mask ink, and has an upper surface 91 and a lower surface 92, wherein the upper surface 91 is flat, so that the height difference of the upper surface 91 can be less than 10 microns, or not more than 5 microns, or even not more than 1 micron within a 100 micron square area, the solder mask layer 9A is joined to the side 33 of the terminal 3A, and the upper surface 31 and the lower surface 32 of the terminal 3A are exposed on the upper surface 91 and the lower surface 92 of the solder mask layer 9A, respectively, and the terminal 3A is made by electroplating process, so that the terminal 3A gradually thickens from the upper surface 31, the lower surface 32 of the terminal 3A may be recessed or flush with or protrude from the lower surface 92 of the solder mask 9A, the insulating layer 40 is an insulator, typically made of GHPL830NS from mitsubishi gas corporation or other BT resin, or ABF (Ajinomoto build-up film) resin, and has an upper surface 41 and a lower surface 42, the insulating layer 40 is bonded to the terminal 3A and the lower surfaces 32, 92 of the solder mask 9A, the wiring 70 is bonded to the lower surface 42 of the insulating layer 40 and is electrically connected to the terminal 3A by a connector 78 housed in the insulating layer 40, the insulating layer 4A is an insulator, which may be implemented as solder mask ink or BT resin or ABF resin, and the insulating layer 4A is bonded to the lower surface 42 of the insulating layer 40 and covers the wiring 70; the carrier board 8A is made of a metal element 8C, and has an upper surface 81 and a lower surface 82, before the conductive element 28 and the element 2S are joined to the upper surface 31 of the terminal 3A, the carrier board 8A needs to be removed to expose the upper surface 31 of the terminal 3A to the atmosphere, or any one of the carrier boards 8A shown in fig. 7A to 7E can be disposed on the lower surface 62 of the circuit board 6A as required; the chip 20 has an upper surface 21, a lower surface 22 and a connecting pad 24, and is disposed on the upper surface 61 of the circuit board 6A; the conductive member 28 is implemented as a copper bump, which is composed of a component 2P implemented as a copper pillar and a component 2S implemented as tin, wherein the component 2P is bonded to the bonding pad 24 of the chip 20, and the component 2S is bonded to the terminal 3A of the circuit board 6A, so that the chip 20 is electrically connected to the circuit board 6A; the plastic 45 is an insulator, which is bonded to the upper surface 61 of the circuit board 6A and covers the chip 20 and the conductive member 28; compared with the package 10 of fig. 9B, the above package 1A has several advantages as follows: 1) the quality is better, and the characteristic of the joint of the carrier plate 8A and the end point 3A of the circuit board 6A can prevent the upper surface 31 of the end point 3A from being oxidized, so that a protective layer implemented as an organic solder resist is not required to be arranged, and the protective layer is not required to be removed by soldering flux, so that the soldering flux is not left on the upper surface 61 of the circuit board 6A, and the damage of stripping between the plastic 45 and the circuit board 6A can be avoided; 2) the quality is better, the upper surface 61 of the circuit board 6A is except the upper surface 31 of the end point 3A, the other areas are composed of the flat solder mask layer 9A, by the flat upper surface 61 of the circuit board 6A, except that the pollutants (M) such as soldering flux and the like are not accumulated, and further, because the area of the upper surface 61 of the circuit board 6A corresponding to the chip 20 is also provided with the solder mask layer 9A, therefore, the upper surface 61 of the circuit board 6A is not easy to accumulate the pollutants, and the insulating layer 40 is not jointed with the plastic 45, the plastic 45 and the circuit board 6A have better jointing quality, and because of the characteristics of the material, the jointing quality of the plastic 45 and the solder mask layer 9A can meet the requirements of the packaging body 1A, and the insulating layer 40 which is made of BT resin or AB; 3) a carrier plate with low cost, wherein when the thickness of the circuit board 6A is less than 110 μm, the lower surface 62 of the circuit board 6A can be joined to a carrier plate for enhancing rigidity, and the carrier plate can be implemented as the carrier plate 8A shown in fig. 7A to 7E, so that the carrier plate has the effects of less material consumption, thinner thickness and lower cost. .
As shown in fig. 2A and 2B, which are cross-sectional views of embodiments of a circuit board and a package, the package 1B includes a circuit board 6B, a chip 20, a conductive member 18 and a plastic 45, the circuit board 6B is developed based on the circuit board 6A shown in FIG. 1A, except that the upper surface 31 of the terminal 3A of the circuit board 6B is recessed on the upper surface 91 of the solder mask layer 9A, and the terminal 3A has a passivation layer 77 for bonding, the remaining features and symbols are the same as for the circuit board 6A of fig. 1A, as described with reference to fig. 1A, wherein the passivation layer 77 may be made of silver, or nickel and gold, or nickel, palladium and gold, to improve the quality of the connection with the conductive member 18, when the lower surface 62 of the circuit board 6B is composed of the insulating layer 4A, the insulating layer 4A may be implemented as a solder mask, or the insulating layer 4A has an opening 44 so that the lower surface 72 of the line 70 can be electrically connected to the outside, or has a reserved opening 44H so that the line 70 cannot be electrically connected to the outside; the plastic 45 is an insulator, which is bonded to the upper surface 61 of the circuit board 6B and covers the chip 20 and the conductive member 18, and when the insulating layer 4A has the reserved opening 44H, after the plastic 45 is bonded to the circuit board 6B, the reserved opening 44H needs to be converted into the opening 44 so that the circuit 70 can be electrically connected to the outside; the chip 20 has an upper surface 21, a lower surface 22 and a connecting pad 24, and is disposed on the upper surface 61 of the circuit board 6A; the conductive member 18 is implemented as a conductive wire, and the chip 20 connection pads 24 and the terminal 3A of the circuit board 6B are respectively connected with the conductive member 18, so that the chip 20 is electrically connected with the circuit board 6B; the circuit board 6B of fig. 2A may be formed by adding a passivation layer 77, or changing the insulating layer 4A to have the opening 44 or reserving the opening 44H, or adding another insulating layer 40 and a conductive member 78 on the lower surface 41 of the insulating layer 4A to make the circuit board 6B have a multi-layer circuit, or adding another circuit 75, where the circuit 75 has the function of transmitting electricity or adjusting the warpage, and making the circuit 75 be connected to the lower surface 92 of the solder mask layer 9A, or adding a conductive member (78) to make the circuit 70 electrically connected to the circuit 75, so that the package 1B has more practicability.
As shown in fig. 3 and 4, which are cross-sectional views of an embodiment of a circuit board and a carrier board, the circuit board 6A and the carrier board 8A in fig. 1A are developed, the circuit board 6B includes a terminal 3B and a solder mask layer 9A, the terminal 3B has an upper surface 31, a lower surface 32, a side 33 and a passivation layer 77, and the passivation layer 77 is implemented as the upper surface 31 of the terminal 3B for the connection of a conductive member, wherein the upper surface 31 of the terminal 3B in fig. 4 protrudes from the upper surface 91 of the solder mask layer 9A, the solder mask layer 9A is an insulator having an upper surface 91 and a lower surface 92, at least a portion of the side 33 of the terminal 3B is connected to the solder mask layer 9A, so that the lower surface 32 of the terminal 3B can be recessed or flush with the lower surface 92 of the solder mask layer 9A, when the lower surface 32 protrudes from the lower surface 92 of the solder mask layer 9A, a portion of the side 33 is exposed to, for improving the bonding strength and quality of the terminal 3B and tin or other materials; the carrier 8A is bonded to the upper surface 61 of the circuit board 6B and has an effect of preventing the upper surface 31 of the terminal 3B from being oxidized, and the carrier 8A may have a recess 88 for accommodating the terminal 3B or for adjusting the warpage of the circuit board 6B as required, and the carrier 8A may be replaced with any one of the carriers 8A shown in fig. 7A to 7E as required.
As shown in fig. 5, which is a cross-sectional view of an embodiment of a circuit board and a carrier board, developed based on the circuit board 6B and the carrier board 8A of fig. 3, the circuit board 6A includes an end point 3A, a solder mask layer 9A and a circuit 70, wherein the end point 3A has an upper surface 31, a lower surface 32 and a side 33 and is used for external electrical connection, and the circuit 70 has an upper surface 71, a lower surface 72 and a side 73 and is used for electrical transmission; line 70 is disposed adjacent to endpoint 3A and in electrical communication with endpoint 3A, or line 70 is disposed adjacent only endpoint 3A and is in electrical communication with endpoint 3A; the solder mask layer 9A has an upper surface 91 and a lower surface 92 and covers the terminal 3A and the circuit 70, wherein the upper surfaces 31 and 71 of the terminal 3A and the circuit 70 are exposed on the upper surface 91 of the solder mask layer 9A, and the lower surface 92 of the solder mask layer 9A protrudes from the lower surfaces 32 and 72 of the terminal 3A and the circuit 70, and meanwhile, the solder mask layer 9A may have an opening 94 or a reserved opening 94H, when the opening 94 is present, the terminal 3A or the lower surfaces 32 and 72 of the circuit 70 may be electrically connected to the outside, and when the reserved opening 94H is present, the terminal 3A or the lower surfaces 32 and 72 of the circuit 70 may not be electrically connected to the outside before the reserved opening 94H is converted into the opening 94, no matter whether the solder mask layer 9A has the opening 94 or the reserved opening 94H, at least a portion of the solder mask layer 9A is joined to the lower surfaces 32 and 72 of the terminal; the carrier 8A is bonded to the upper surface 61 of the circuit board 6A, and has the same characteristics as the carrier 8A of fig. 3; in addition, a circuit can be added on the lower surface 92 of the solder mask 9A to increase the density, or a solder mask can be disposed on the upper surface 91 to cover the upper surface 71 of the circuit 70.
As shown in fig. 6, which is a cross-sectional view of an embodiment of a circuit board and a carrier board, the circuit board 6C is made of a terminal 3C, an insulating layer 40, a circuit 70, a conductive member 78, a solder mask layer 9A and a protective layer 77, the designed value of the thickness T6 of the circuit board 6C in this embodiment is 110 ± 30 μm, the terminal 3C has an upper surface 31, a lower surface 32 and a side 33 for external electrical connection, the insulating layer 40 is made of GHPL830NS of mitsubishi gas corporation or other BT resin and has an upper surface 41 and a lower surface 42, the insulating layer 40 covers the lower surface 32 and the side 33 of the terminal 3C and exposes the upper surface 31 of the terminal 3C to the upper surface 41 of the insulating layer 40, the circuit 70 is connected to the lower surface 42 of the insulating layer 40 and is electrically connected to the terminal 3C through the conductive member 78 accommodated in the insulating layer 40, the solder mask layer 9A is made of AUS308 of tai corporation or other solder mask ink, the solder mask layer 9A covers the circuit 70 and is bonded to the lower surface 42 of the insulating layer 40, and a portion of the lower surface 72 of the circuit 70 is exposed to the atmosphere, and the passivation layer 77 is bonded to the lower surface 72 of the circuit 70 exposed to the atmosphere; the lower surface 82 of the carrier plate 8A is jointed with the upper surface 61 of the circuit board 6C, and has the effects of increasing rigidity and adjusting warping, so that the circuit board 6C is not damaged by extrusion due to insufficient rigidity or excessive warping in the using process, the structure of the carrier plate 8A is designed according to the warping degree of the circuit board 6C, the warping degree of the circuit board 6C is generated by the thermal expansion coefficient of each component and the characteristic of circuit layout (layout), the insulating element 8D of the carrier plate 8A is respectively jointed with the metal element 8C and the metal element 8E, the element 8E is further jointed with another element 8C, the structure for jointing the element 8C and the element 8E has the effect of being detachable, in the process of removing the carrier plate 8A, the element 8E is firstly removed, then the element 8C is removed by an etching method, so that the upper surface 61 of the circuit board 6C is exposed in the atmosphere, the design value of the thickness T of the carrier 8A is 100 + -50 microns, that is, the thickness T of the carrier 8A can be between 50-150 microns, and the thickness T of the circuit board 6C with the thickness of 110 microns can carry the carrier 8A with the thickness of 100 microns, the total thickness is 210 microns, because the difference between the thickness T6 of the circuit board 6C and the thickness T of the carrier 8A is not large, the warping degree can meet the requirement in production, and the thickness T of the carrier 8A is 150 microns less than the thickness T of the conventional carrier 80 in FIG. 9A, the carrier 8A has the advantages of less material consumption and thinner thickness, which makes the production efficiency better, further reduces the cost of the carrier 8A, makes the designed carrier 8A more usable, and at the same time, the thickness of the component 8C or the component 8D of the carrier 8A can be adjusted according to the thickness and the characteristics of the circuit board, making the carrier 8A have the carrier structure as shown in FIGS. 7A-7E, when the carrier 8A is composed of only the device 8C, compared to the conventional carrier 80 shown in fig. 9A, the carrier 8A may have a recess (88_ see fig. 3) as required, or the thickness T of the carrier 8A may be reduced to 5 microns or less than 5 microns, and the carrier 8A is composed of only the device 8C, so that the material and production cost of the carrier 8A are lower, the usage amount is less, and the carrier is more environment-friendly; from the above description, the insulator bonded to the side of the terminal can be a solder mask or an insulating layer, and the carrier can also be bonded to the upper surface or the lower surface of the circuit board, so that the circuit board and the carrier can be used more flexibly.
As shown in fig. 7A to 7E, which are cross-sectional views of embodiments of the carrier plate, when the circuit board is in use, and when the rigidity is insufficient or the thickness of the circuit board is less than 110 μm, the carrier plate can be bonded to the lower surface or/and the upper surface of the circuit board to avoid the above-mentioned damage, but since the carrier plate 8A is an auxiliary material, the carrier plate can be removed before or after the circuit board is bonded to the plastic 45; the carrier 8A is composed of conductive elements 8C, 8E and/or an insulating element 8D, and has an upper surface 81 and a lower surface 82, which may be composed of only one element 8C, and an element 8D may be further superimposed on the surface of the element 8C, or an element 8C may be further superimposed on the surface of the element 8D, or an element 8C, an element 8E and an element 8D may be superimposed, wherein the element 8D is exposed to the atmosphere, or an element 8C is further superimposed on the surface of the element 8D exposed to the atmosphere; when the component 8C is implemented as the upper surface 81 or the lower surface 82 of the carrier 8A, it can be used for the conductive path in the electroplating process when the terminal 3A is fabricated, and when the carrier 8A has a recess (88_ fig. 4), the terminal 3A can protrude from the upper surface 91 of the solder mask layer 9A; fig. 7A-7E are merely illustrative embodiments, and the number of elements 8C, 8D may be increased or decreased as desired.
Referring to fig. 8A-8B, which are cross-sectional views illustrating an embodiment of a method for manufacturing a package, first, as shown in fig. 8A, a circuit board 6A and a carrier 8A are provided, and features and symbols of the circuit board 6A and the carrier 8A are the same as those of the circuit board 6A and the carrier 8A shown in fig. 5, please refer to fig. 5 for description, a solder mask layer 9A of the circuit board 6A may have an opening or a reserved opening, which is implemented as an opening 94 in this example, so that the lower surface 72 of the circuit 70 can be electrically connected, and then, a removing process is provided to remove the carrier 8A; next, as shown in fig. 8B, first providing a chip 20 and a conductive member 28, the chip 20 having a connection pad 24 and being disposed on an upper surface 61 of the circuit board 6A, the conductive member 28 being implemented as a copper bump and composed of a component 2P and a component 2S, the connection pad 24 of the chip 20 and an end 3A of the circuit board 6A being respectively joined to one end of the conductive member 28, so that the chip 20 is electrically connected to the circuit board 6A, the chip 20 and the conductive member 28 being replaceable into the chip 20 and the conductive member 18 of fig. 2B, then providing a plastic 45, joining the plastic 45 to the upper surface 61 of the circuit board 6A by a filling process, and covering the chip 20 and the conductive member 28 to join, and thus forming a package 1A; next, when the solder mask layer 9A has a predetermined opening, an opening process is provided to remove a portion of the solder mask layer 9A, so that the predetermined opening is converted into the opening 94 and the lower surface 72 of the circuit 70 can be electrically connected.
The embodiments are merely illustrative of the principles and effects of the present invention, and do not limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed herein be covered by the appended claims.

Claims (13)

1. A circuit board comprises an end point and a solder mask layer, wherein the surfaces of the circuit board exposed in the atmosphere are respectively implemented as an upper surface and a lower surface, and the upper surface of the circuit board is jointed with plastic of a packaging body; the method is characterized in that:
the end point is made of conductive materials and comprises an upper surface, a lower surface and side edges; and
the welding-proof layer is made of insulating materials and comprises an upper surface and a lower surface; wherein, the upper surface of the solder mask layer is flat, the solder mask layer is at least jointed with the side edge of the endpoint, and the upper surface of the endpoint is exposed on the upper surface of the solder mask layer; the upper surfaces of the solder mask layer and the terminal are implemented as the upper surface of the circuit board.
2. A circuit board according to claim 1, wherein: comprises a carrier plate; the carrier plate comprises an upper surface and a lower surface, the carrier plate is jointed with the upper surface or/and the lower surface of the circuit board, and the surface of the carrier plate jointed with the upper surface of the circuit board is implemented as a metal element.
3. A circuit board according to claim 1, wherein: the upper surface of the end point protrudes out of the upper surface of the solder mask layer.
4. A circuit board according to claim 1, wherein: comprises a circuit which is jointed with the lower surface of the solder mask layer.
5. A circuit board according to claim 1, wherein: the structure comprises an insulating layer, a circuit and a conductive piece, wherein the upper surface of the insulating layer is jointed with the lower surface of the solder mask layer, the circuit is jointed with the lower surface of the insulating layer, and the circuit is electrically communicated with an endpoint by the conductive piece arranged in the insulating layer.
6. A circuit board according to claim 1, wherein: comprises a circuit, which comprises an upper surface, a lower surface and a side edge; the line is arranged adjacent to the end point; wherein, the lower surface of the solder mask layer protrudes out of the end points and the lower surface of the circuit.
7. A circuit board according to claim 2, wherein: the carrier plate includes a recess.
8. A circuit board and a carrier plate are characterized in that:
the circuit board comprises an end point, an insulating layer, a circuit, a conductive piece, a solder mask layer and a protective layer; the end point is used for external electric connection, and comprises an upper surface, a lower surface and a side edge; the insulating layer comprises an upper surface and a lower surface, the lower surface and the side edges of the end points are coated by the insulating layer, and the upper surface of the end points is exposed and does not protrude out of the upper surface of the insulating layer; the circuit is jointed with the lower surface of the insulating layer and is electrically communicated with the end point through a conductive piece accommodated in the insulating layer; the solder mask layer comprises an upper surface and a lower surface, the solder mask layer covers the circuit and is jointed with the lower surface of the insulating layer, and the lower surface of the circuit is partially exposed in the atmosphere; the protective layer is implemented as a conductor and is arranged on the surface of the circuit exposed in the atmosphere; meanwhile, the upper surfaces of the insulating layer and the end points are implemented as the upper surface of the circuit board; and
the carrier plate comprises an upper surface and a lower surface, is at least composed of a first metal element and is jointed with the upper surface of the circuit board.
9. The circuit board and carrier of claim 8, wherein: the carrier plate comprises an insulating element and a first metal element; wherein, a surface of the insulating element is jointed with the first metal element.
10. The circuit board and carrier of claim 8, wherein: the carrier plate comprises an insulating element and a second metal element; one surface of the second metal element is jointed with the first metal element, and the other surface of the second metal element is jointed with the insulating element.
11. The circuit board and carrier of claim 8, wherein: the carrier plate includes a recess.
12. The utility model provides a packaging body, packaging body includes circuit board, chip, electrically conductive piece and plastics at least, its characterized in that:
the circuit board comprises a solder mask layer and an end point, and the circuit board is provided with an upper surface and a lower surface; the upper surface of the circuit board consists of the upper surfaces of the end points and the upper surface of the solder mask layer; the end point comprises an upper surface, a lower surface and a side edge; the solder mask layer comprises an upper surface and a lower surface, wherein the upper surface of the solder mask layer is flat, the solder mask layer is at least jointed with one part of the side edge of the endpoint, and the upper surface of the endpoint is exposed on the upper surface of the solder mask layer; and
the plastic, the chip and the conductive piece; the plastic is jointed with the upper surface of the circuit board, and the chip and the conductive piece are coated by the plastic; the chip connecting pad and the end point are respectively jointed with one end of the conductive piece, so that the chip is electrically communicated with the circuit board.
13. A method for manufacturing a package is characterized in that: the method comprises the following steps:
the method comprises the following steps: providing a circuit board and a carrier plate, wherein the circuit board comprises a solder mask layer and an end point, and the circuit board is provided with an upper surface and a lower surface; the upper surface of the circuit board consists of the upper surfaces of the end points and the upper surface of the solder mask layer; the end point comprises an upper surface, a lower surface and a side edge; the solder mask layer comprises an upper surface and a lower surface, wherein the upper surface of the solder mask layer is flat; the solder mask layer is at least jointed with one part of the side edge of the endpoint, and the upper surface of the endpoint is exposed out of the upper surface of the solder mask layer; the carrier plate comprises an upper surface and a lower surface, the carrier plate is jointed with the upper surface of the circuit board, and the jointed surface of the carrier plate and the circuit board consists of metal elements;
step two: providing a removing procedure to remove the carrier plate and expose the upper surface of the circuit board in the atmosphere;
step three: providing a chip and a conductive piece, wherein the chip is arranged on the upper surface of the circuit board, and the chip connecting pad and the end point of the circuit board are respectively jointed with one end point of the conductive piece so as to lead the chip to be electrically communicated with the conductive piece; and;
step four: providing a filling process and plastic to make the plastic joint with the upper surface of the circuit board and make the plastic cover the chip and the conductive piece.
CN202010736984.5A 2020-04-29 2020-07-28 Circuit board and packaging body Pending CN112164676A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW109114320 2020-04-29
TW109114320A TW202142058A (en) 2020-04-29 2020-04-29 A printed circuit board and package

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Publication Number Publication Date
CN112164676A true CN112164676A (en) 2021-01-01

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