CN112163355B - SiC MOSFET packaging structure optimization design method, medium and equipment - Google Patents
SiC MOSFET packaging structure optimization design method, medium and equipment Download PDFInfo
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Abstract
The invention relates to an embedded fan-out type SiC MOSFET packaging structure optimization design method, medium and equipment, wherein the method constructs a three-dimensional model of a SiC MOSFET device, determines a feasible region of chip distribution, utilizes a response surface method to carry out simulation parameter design based on the feasible region, carries out finite element simulation based on the simulation parameter, constructs a mathematical model between the distribution condition of the chip and the maximum heat dissipation temperature and the maximum stress according to a simulation result, thereby obtaining a chip distribution mode with optimal heat dissipation and stress, and realizing the packaging structure optimization design. Compared with the prior art, the method has the advantages of high analysis efficiency, high optimization accuracy and the like.
Description
Technical Field
The invention belongs to the field of semiconductor device reliability optimization, relates to power electronic devices, finite element analysis and response surface experiment optimization design, and in particular relates to an SiC MOSFET packaging structure optimization design method, medium and equipment.
Background
Compared with Si chips, the SiC chips can realize higher withstand voltage and lower loss by using smaller volume, and bring more convenience to the research and development design of traction conversion systems and power transmission systems. Furthermore, siC chips have lower output capacitance and gate charge. The characteristics of high switching speed, low switching loss and high switching frequency can improve the power density and efficiency of the power supply module. At higher temperatures, the switching loss of Si IGBTs increases significantly, while the switching loss of SiC MOSFETs does not change much with temperature. However, the wide range of applications of SiC MOSFETs in high temperature applications is currently greatly limited. One of the most important limiting factors is uncertainty in its reliability under high temperature conditions, since the lifetime of a power semiconductor is closely related to its thermal profile. In addition, with the rise of temperature level, the long-time thermal cycle can easily accelerate the abrasion processes such as wire stripping, solder cracking and the like. Therefore, new package technologies such as leadless have to be developed to promote the development of the power module. While there is a need for methods to optimize the structure of leadless packaged SiC MOSFETs.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide an embedded fan-out type SiC MOSFET packaging structure optimization design method, medium and equipment.
The aim of the invention can be achieved by the following technical scheme:
the method constructs a three-dimensional model of a SiC MOSFET device, determines a feasible region of chip distribution, carries out simulation design by using a response surface method based on the feasible region, carries out finite element simulation based on simulation times and simulation sequences obtained by the simulation design, constructs a mathematical model between the distribution condition of the chip and the maximum heat dissipation temperature and the maximum stress according to the simulation result, thereby obtaining a chip distribution mode with optimal heat dissipation and stress, and realizing the optimal design of the package structure.
Further, a feasible region of the chip distribution is determined based on each encapsulation layer constraint in the three-dimensional model.
Further, the packaging layer constraints include device via locations, chip size RDL layer constraints, and solder mask constraints.
Further, the packaging structure packages two chips which are symmetrical in center about the center of the feasible region, and when simulation design is carried out by using a response surface method based on the feasible region, the center point coordinate of one of the chips is determined.
Further, the simulation parameters include simulation times and simulation sequences.
Further, the finite element simulation includes a heat dissipation simulation and a temperature cycle simulation based on JEDEC standards.
Further, when the temperature cycle simulation based on the JEDEC standard is performed, the simulation environment temperature parameter and the boundary condition are determined according to the JEDEC standard.
Further, the method further comprises:
and (3) performing response surface analysis on the finite element simulation result, and analyzing simulation accuracy.
The invention also provides a computer readable storage medium, on which a computer program is stored, which when being executed by a processor, implements the steps of the embedded fan-out type SiC MOSFET packaging structure optimizing design method.
The present invention also provides an electronic device including:
a processor;
a memory storing processor-executable instructions;
the processor is coupled to the memory, and is configured to read the program instructions stored in the memory, and in response, execute steps in the embedded fan-out SiC MOSFET package structure optimization design method.
The invention also provides a SiC MOSFET packaging structure obtained based on the embedded fan-out type SiC MOSFET packaging structure optimization design method.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention adopts a response surface design method to design, and performs finite element analysis by researching different distribution conditions of the chip, thereby effectively improving analysis efficiency.
2. The finite element simulation comprises a heat dissipation simulation and a JEDEC standard-based temperature cycle simulation, the temperature distribution condition of the device in steady-state operation is obtained under a heat dissipation simulation test, the influence of chip distribution on the reliability of thermal stress of a redistribution layer (RDL) is obtained under a temperature impact simulation test, and simulation data are comprehensive, so that the accuracy of the optimal design of the packaging structure is effectively improved.
3. The invention adopts the response curved surface to obtain the mathematical model, obtains the result which finally enables the temperature and the stress to reach the optimum based on the obtained optimized mathematical model, and has high optimization design efficiency.
4. By the structure optimization method, the structure of the device can be effectively improved, the heat dissipation temperature and the thermal stress of the device can be reduced, and the reliability of the device can be improved.
Drawings
FIG. 1 is a flow chart of the method of the present invention;
FIG. 2 is a device model diagram of the method of the present invention;
FIG. 3 is an exploded view of a device model in the method of the present invention;
FIG. 4 is a schematic diagram of a feasible region in the method of the present invention;
FIG. 5 is a schematic diagram of a redistribution layer (RDL) in the method of the present invention;
FIG. 6 is a contour plot of response surface temperature optimization in the method of the present invention;
FIG. 7 is a contour plot of response surface stress optimization in the method of the present invention;
FIG. 8 is a graph of response surface optimization results in the method of the present invention.
Detailed Description
The invention will now be described in detail with reference to the drawings and specific examples. The present embodiment is implemented on the premise of the technical scheme of the present invention, and a detailed implementation manner and a specific operation process are given, but the protection scope of the present invention is not limited to the following examples.
Example 1
The embodiment provides an embedded fan-out type SiC MOSFET packaging structure optimization design method which is mainly applied to power devices and module reliability optimization occasions. The method utilizes a response surface method to carry out optimization design and analysis on simulation, calculates the maximum heat dissipation temperature of a re-wiring layer (RDL) in the SiC MOSFET in steady-state heat dissipation and the maximum stress after temperature cycle simulation based on finite element simulation analysis, and constructs a mathematical model between the distribution condition of the chip and the heat dissipation temperature and the maximum stress, thereby finding out the chip distribution mode with optimal heat dissipation and stress so as to achieve the aim of optimization.
As shown in fig. 1, the method comprises the steps of:
step one: and establishing a three-dimensional model of the SiC MOSFET device, and determining the basic structure and parameters of the SiC MOSFET device. The three-dimensional model of the SiC MOSFET device established in this embodiment is shown in fig. 2.
As shown in fig. 3, the SiC MOSFET device includes a solder resist layer 1, a re-wiring layer (RDL) 2, a cured pre-material layer 3, a SiC chip 5, a BT laminate 4, a cured pre-material layer 6, a re-wiring layer (RDL) 7, and a solder resist layer 8, which are disposed in this order. In the present embodiment, the SiC chip 5 is provided with two.
Step two: and determining the feasible region of the chip distribution on the substrate according to the established model, and calculating the size of the feasible region.
As shown in fig. 4, the feasible region of the chip distribution is determined on the BT laminate (substrate) based on the established three-dimensional model, and the size thereof is calculated. The constraint condition of the feasible region determination is the constraint of each packaging layer of the device, so that a certain reserved space is reserved among the structures of each layer, and the phenomena of contact and extrusion can not occur. Specific constraints include:
1. device via location: as shown in fig. 4, the device has three groups of through holes for heat dissipation, and two chips cannot contact with the through holes;
2. chip size: as shown in fig. 4, the experimental factor required to be determined by the experimental design of the response surface method is the coordinate of the center point of the right chip in the cured pre-material layer, and the change of the coordinate of the center point needs to be reduced due to the size of the chip;
3. RDL layer restrictions: as shown in fig. 5, the RDL layer is formed by several metal sheets with different sizes, and the chip distribution is considered, and meanwhile, the RDL layer cannot be contacted and extruded to cause unnecessary errors;
4. and (3) limit of a solder mask: the outermost side of the device is a solder mask layer, and the chip cannot be in direct contact with the solder mask layer, so that a reserved space is reserved.
Step three: for chip distribution in a feasible domain, experimental design is performed by using a response surface method, and simulation times and simulation sequences are determined as shown in table 1.
TABLE 1
Step four: and determining environmental parameters and boundary conditions of the temperature cycle simulation according to JEDEC standards, and performing finite element simulation according to the simulation sequence in the step three.
Step five: and after all the simulations are completed, performing response surface analysis on the simulation results in the step four, and analyzing the simulation accuracy.
The optimization process in this embodiment is: and analyzing the contour diagrams of the calculated temperature and stress respectively about the factors x and y, and analyzing the curve characteristics of the contour diagrams, as shown in fig. 6 and 7.
Step six: and constructing a mathematical model of chip distribution, heat dissipation temperature and thermal stress response to obtain a result of finally optimizing the temperature and the stress.
The mathematical model obtained by simulation in this embodiment is as follows:
wherein T represents the highest temperature of the device, and sigma represents the maximum stress of the RDL layer; x and y are the abscissa and ordinate of the center point of the right chip, respectively.
Example 2
The present embodiment provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the embedded fan-out SiC MOSFET package structure optimization design method described in embodiment 1.
Example 3
The present invention also provides an electronic device, including a processor and a memory storing instructions executable by the processor, wherein the processor is coupled to the memory, and is configured to read the program instructions stored in the memory, and in response, perform the steps in the method for optimizing the design of the embedded fan-out SiC MOSFET package structure according to embodiment 1.
The foregoing describes in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be made in accordance with the concepts of the invention by one of ordinary skill in the art without undue burden. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by the person skilled in the art according to the inventive concept shall be within the scope of protection defined by the claims.
Claims (6)
1. The method is characterized in that the method constructs a three-dimensional model of an SiC MOSFET device, the SiC MOSFET device comprises a solder mask layer, a rewiring layer, a curing pre-material layer, an SiC chip, a BT laminated board, a curing pre-material layer, a rewiring layer and a solder mask layer which are sequentially arranged, a feasible region of chip distribution is determined on a substrate according to the established model, the size of the feasible region is calculated, simulation design is carried out by using a response curved surface method based on the feasible region, finite element simulation is carried out based on simulation times and simulation sequences obtained by the simulation design, the maximum heat dissipation temperature of the rewiring layer in steady-state heat dissipation and the maximum stress after temperature cycle simulation are calculated, response curved surface analysis is carried out on the result of finite element simulation, the accuracy of the simulation is analyzed, a mathematical model between the distribution condition of the chip and the maximum heat dissipation temperature and the maximum stress is constructed according to the simulation result, and therefore the optimal chip distribution mode of heat dissipation and stress is obtained, and the optimal design of the packaging structure is realized;
determining a feasible region of the chip distribution based on each packaging layer constraint in the three-dimensional model, wherein the packaging layer constraint comprises a device through hole position, a chip size, an RDL layer limit and a solder mask limit, and specifically:
device via location: three groups of through holes for heat dissipation are formed in the device, and two chips cannot be contacted with the through holes;
chip size: the change of the coordinates of the central point is reduced because the chip has the size;
RDL layer restrictions: the RDL layer is formed by a plurality of metal sheets with different sizes, and the distribution of chips is considered, and meanwhile, the RDL layer cannot be contacted and extruded to cause unnecessary errors;
and (3) limit of a solder mask: the outermost side of the device is a solder mask layer, and the chip cannot be in direct contact with the solder mask layer, so that a reserved space is needed;
the packaging structure packages two chips which are centrally symmetrical about the center of a feasible region, and when simulation design is carried out by using a response surface method based on the feasible region, the coordinates of the center point of one chip are determined, and the experimental factors required to be determined by the response surface method experimental design are the coordinates of the center point of one chip in a curing pre-material layer.
2. The embedded fan-out SiC MOSFET package structure optimization design method of claim 1, wherein the finite element simulation includes a heat dissipation simulation and a JEDEC standard-based temperature cycling simulation.
3. The method for optimizing the design of the embedded fan-out type SiC MOSFET packaging structure according to claim 2, wherein when the temperature cycle based on the JEDEC standard is simulated, the simulation environment temperature parameter and the boundary condition are determined according to the JEDEC standard.
4. A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor performs the steps of the embedded fan-out SiC MOSFET package structure optimization design method of any of claims 1-3.
5. An electronic device, comprising:
a processor;
a memory storing processor-executable instructions;
wherein the processor is coupled to the memory for reading the program instructions stored by the memory and, in response, performing the steps in the embedded fan-out SiC MOSFET package structure optimization design method of any one of claims 1-3.
6. A SiC MOSFET package obtained based on the embedded fan-out SiC MOSFET package optimization design method of any one of claims 1-3.
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| CN113158601A (en) * | 2021-03-24 | 2021-07-23 | 复旦大学 | High-reliability board-level fan-out SiC MOSFET packaging structure optimization method |
| CN113392552B (en) * | 2021-06-15 | 2022-04-15 | 武汉大学 | Current-sharing optimization design method for multiple parallel switch devices based on finite element simulation |
| CN113343535B (en) * | 2021-06-23 | 2022-04-01 | 复旦大学 | High-reliability embedded SiC power device packaging design method |
| CN115376971A (en) * | 2022-09-15 | 2022-11-22 | 绍兴中芯集成电路制造股份有限公司 | Method, device and equipment for determining chip position in power module and storage medium |
| CN116127903B (en) * | 2023-02-14 | 2023-11-14 | 电子科技大学 | High-power PA chip layout and wind tunnel type self-heat-dissipation packaging design method |
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