CN117391033A - Thermal model determination and thermal simulation method, device, equipment and storage medium - Google Patents
Thermal model determination and thermal simulation method, device, equipment and storage medium Download PDFInfo
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- G06F30/00—Computer-aided design [CAD]
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- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
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Abstract
The present disclosure relates to thermal model determination and thermal simulation methods, apparatuses, devices, and storage media. The thermal model determining method comprises the following steps: determining a physical structure equivalent model associated with a thermal via disposed under a heat source chip of a circuit board, the physical structure equivalent model including a thermal via region and a non-thermal via region and having dimensional parameters associated with the circuit board and the heat source chip; acquiring a first thermal resistance for the thermal via region and a second thermal resistance for the non-thermal via region; determining a target thermal conductivity for the physical structure equivalent model based on the first thermal resistance and the second thermal resistance; and based on the target thermal conductivity and the dimensional parameter, obtaining a target equivalent thermal model associated with the thermal via. In this way, the accuracy of the thermal simulation of the junction temperature of the chip on the circuit board can be improved.
Description
Technical Field
The present disclosure relates generally to the field of autopilot and heat dissipation simulation technology, and in particular to thermal model determination and thermal simulation methods, apparatus, devices, and storage media.
Background
With the development of new energy vehicles, domain controllers related to automatic driving are widely adopted. The thermal power consumption of the critical components of the domain controller, the system on a chip (SOC) and other power chips, increases. With the increase of calculation power, the temperature control of the chip becomes a key for ensuring the safe operation of the system, and reasonable thermal design is required.
As a core component for heat dissipation, the heat conducting performance of the circuit board is particularly important. The thermal conductivity in the board thickness direction is smaller than the thermal conductivity in the plane. In order to improve the thermal conductivity in the thickness direction, thermal vias (Via) are often designed on printed circuit boards.
Currently, estimation of domain controller thermal design relies primarily on commercial electronic thermal simulation software. The thermal conductivity of the circuit board is generally simplified to be uniform and consistent in the plane direction and the thickness direction, so that a certain error exists in simulation results. In fact, the thermal conductivity of the circuit board is significantly non-uniform in all directions, especially in the thickness direction at different locations. Among these, the most important influencing factors is that a circuit board under the chip is usually provided with a large number of thermal vias to enhance the heat dissipation effect. If a detailed thermal via model is directly built according to the actual size of the thermal via in the circuit board level or system level thermal simulation, the grid of the thermal simulation model is exponentially increased due to at least one order of magnitude difference between the thermal via size and the circuit board and chip size, and finally, huge operation load is generated, which is not practical in practical application. Therefore, the arrangement of a reasonable thermal model on the circuit board below the chip has important significance for the accuracy of thermal simulation.
The equivalent thermal model determination and thermal modeling method of the existing thermal via structure is simplified and replaced for a single thermal via. However, in practical cases, the number of thermal vias under the main chip on a Printed Circuit Board (PCB) varies from a few to tens of hundreds, and the number of thermal vias on the entire printed circuit board can even reach thousands. If the equivalent model of each thermal via unit is still built separately according to the simplified method, the simplified thermal vias are still quite complex and numerous. Furthermore, the size of a single thermal via is typically below 1 mm. Thus, the simplified thermal vias are not significantly reduced in volume and number. Simulation according to such a simplified model still results in a huge amount of mesh and corresponding calculation.
Accordingly, there is a need for an improved thermal model determination and solution for thermal simulation using the thermal model.
Disclosure of Invention
According to example embodiments of the present disclosure, a thermal model determination and thermal simulation method, apparatus, device, and storage medium are provided to at least partially solve the problems of the prior art.
In a first aspect of the present disclosure, a thermal model determination method is provided. The method comprises the following steps: determining a physical structure equivalent model associated with a thermal via, the thermal via disposed under a heat source chip of the circuit board, the physical structure equivalent model including a thermal via region and a non-thermal via region and having dimensional parameters associated with the circuit board and the heat source chip; acquiring a first thermal resistance for a thermal via region and a second thermal resistance for a non-thermal via region; determining a target thermal conductivity for the physical structure equivalent model based on the first thermal resistance and the second thermal resistance; and based on the target thermal conductivity and the dimensional parameter, obtaining a target equivalent thermal model associated with the thermal via.
In some embodiments, determining a physical structure equivalent model associated with the thermal vias disposed under the heat source chip of the circuit board and dimensional parameters of the physical structure equivalent model associated with the circuit board and the heat source chip may include at least one of: in response to determining that the heat source chip is packaged by the heat dissipation pad, determining a cuboid area with the same area as the lower surface of the heat dissipation pad and the same thickness as the circuit board as a physical structure equivalent model according to the projection of the lower surface of the heat dissipation pad; and determining a cuboid area with the same area as the lower surface of the heat source chip and the same thickness as the circuit board as a physical structure equivalent model according to the lower surface projection of the heat source chip in response to determining that the heat source chip is not packaged by the heat dissipation pad.
In some embodiments, obtaining a first thermal resistance for the hot via region and a second thermal resistance for the non-hot via region may include: determining a first set of thermal resistances for each thermal via in the thermal via region; connecting the thermal resistances in the first set of thermal resistances in parallel to obtain a first thermal resistance for the thermal via region; determining a second set of thermal resistances of the circuit board multilayer material corresponding to the non-thermal via region; each thermal resistor in the second set of thermal resistors is connected in series to obtain a second thermal resistor for the non-thermal via region.
In some embodiments, the thermal via includes an inner circular hole and an outer circular ring, and wherein obtaining a first thermal resistance for the thermal via region and a second thermal resistance for the non-thermal via region may include: obtaining inner circle Kong Rezu and outer circle thermal resistance; and connecting the inner circle Kong Rezu and the outer circle thermal resistor in parallel to obtain the thermal resistor of the thermal via.
In some embodiments, determining the target thermal conductivity for the physical structure equivalent model based on the first thermal resistance and the second thermal resistance may include: coupling the first thermal resistance and the second thermal resistance in parallel to obtain target thermal resistance aiming at a physical structure equivalent model; and obtaining the target thermal conductivity based on the target thermal resistance.
In some embodiments, based on the target thermal conductivity and the dimensional parameter, obtaining a target equivalent thermal model associated with the thermal via may include: acquiring the size parameters of the equivalent model of the physical structure; applying boundary conditions on the physical structure equivalent model; and based on the boundary conditions, the dimensional parameters, and the target thermal conductivity, obtaining a target equivalent thermal model associated with the thermal via.
In some embodiments, imposing boundary conditions on the physical structure equivalent model may include: forming a receiving hole under the heat source chip, wherein the receiving hole has the same size parameter as the physical structure equivalent model; and embedding the physical structure equivalent model into the receiving hole with the contact thermal resistance set to zero.
In a second aspect of the present disclosure, a thermal model determination apparatus is provided. The device comprises: a thermal via equivalent model determination module configured to determine a physical structure equivalent model associated with a thermal via disposed under a heat source chip of the circuit board, the physical structure equivalent model including a thermal via region and a non-thermal via region and having dimensional parameters associated with the circuit board and the heat source chip; a thermal resistance acquisition module configured to acquire a first thermal resistance for a thermal via region and a second thermal resistance for a non-thermal via region; a target thermal conductivity determination module configured to determine a target thermal conductivity for the physical structure equivalent model based on the first thermal resistance and the second thermal resistance; and a target equivalent thermal model determination module configured to obtain a target equivalent thermal model associated with the thermal via based on the target thermal conductivity and the dimensional parameter.
In some embodiments, the thermal via equivalent model determination module may be further configured to perform at least one of: in response to determining that the heat source chip is packaged by the heat dissipation pad, determining a cuboid area with the same area as the lower surface of the heat dissipation pad and the same thickness as the circuit board as a physical structure equivalent model according to the projection of the lower surface of the heat dissipation pad; and determining a cuboid area with the same area as the lower surface of the heat source chip and the same thickness as the circuit board as a physical structure equivalent model according to the lower surface projection of the heat source chip in response to determining that the heat source chip is not packaged by the heat dissipation pad.
In some embodiments, the thermal resistance acquisition module may be further configured to: determining a first set of thermal resistances for each thermal via in the thermal via region; connecting the thermal resistances in the first set of thermal resistances in parallel to obtain a first thermal resistance for the thermal via region; determining a second set of thermal resistances of the circuit board multilayer material corresponding to the non-thermal via region; each thermal resistor in the second set of thermal resistors is connected in series to obtain a second thermal resistor for the non-thermal via region.
In some embodiments, the thermal via includes an inner circular hole and an outer ring, and the thermal resistance acquisition module may be further configured to: obtaining inner circle Kong Rezu and outer circle thermal resistance; and connecting the inner circle Kong Rezu and the outer circle thermal resistor in parallel to obtain the thermal resistor of the thermal via.
In some embodiments, the target thermal conductivity determination module may be further configured to: coupling the first thermal resistance and the second thermal resistance in parallel to obtain target thermal resistance aiming at a physical structure equivalent model; and obtaining the target thermal conductivity based on the target thermal resistance.
In some embodiments, the target equivalent thermal model determination module may be further configured to: acquiring the target equivalent thermal model associated with the thermal vias may include: acquiring the size parameters of the equivalent model of the physical structure; applying boundary conditions on the physical structure equivalent model; and based on the boundary conditions, the dimensional parameters, and the target thermal conductivity, obtaining a target equivalent thermal model associated with the thermal via.
In some embodiments, the target equivalent thermal model determination module may be further configured to: forming a receiving hole under the heat source chip, wherein the receiving hole has the same size parameter as the physical structure equivalent model; and embedding the physical structure equivalent model into the receiving hole with the contact thermal resistance set to zero.
In a third aspect of the present disclosure, an electronic device is provided. The apparatus includes one or more processors; and a memory coupled to the processor, the memory having instructions stored therein that, when executed by the processor, cause the device to perform actions comprising: determining a physical structure equivalent model associated with a thermal via, the thermal via disposed under a heat source chip of the circuit board, the physical structure equivalent model including a thermal via region and a non-thermal via region and having dimensional parameters associated with the circuit board and the heat source chip; acquiring a first thermal resistance for a thermal via region and a second thermal resistance for a non-thermal via region; determining a target thermal conductivity for the physical structure equivalent model based on the first thermal resistance and the second thermal resistance; and based on the target thermal conductivity and the dimensional parameter, obtaining a target equivalent thermal model associated with the thermal via.
In a fourth aspect of the present disclosure, there is provided a computer readable medium having stored thereon a computer program which when executed by a processor implements a method according to the first aspect of the present disclosure.
In a fifth aspect of the present disclosure, a thermal simulation method is provided. The method comprises the following steps: performing thermal simulation modeling with a target equivalent thermal model to obtain a thermal simulation model for the circuit board, wherein the target equivalent thermal model is obtained according to the method of the first aspect of the present disclosure; and performing heat dissipation simulation by using the thermal simulation model to obtain the junction temperature of the heat source chip on the circuit board.
In a sixth aspect of the present disclosure, a thermal simulation apparatus is provided. The device comprises: a thermal simulation model acquisition module configured to perform thermal simulation modeling with a target equivalent thermal model to acquire a thermal simulation model for a circuit board, wherein the target equivalent thermal model is obtained according to the method of the first aspect of the present disclosure; and the heat radiation simulation module is configured to perform heat radiation simulation by using the thermal simulation model so as to obtain the junction temperature of the heat source chip on the circuit board.
In a seventh aspect of the present disclosure, an electronic device is provided. The electronic device includes one or more processors; and a memory coupled to the processor, the memory having instructions stored therein that, when executed by the processor, cause the apparatus to perform a method according to the fifth aspect of the disclosure.
In an eighth aspect of the present disclosure, there is provided a computer readable medium having stored thereon a computer program which when executed by a processor implements a method according to the fifth aspect of the present disclosure.
Various embodiments according to the present disclosure can at least provide the following technical effects:
the thermal distribution of the circuit board can be better known by accurately estimating the thermal conductivity of the thermal vias below the chip and performing thermal simulation modeling. This enables a designer to optimize the layout for a specific location and number of thermal vias to improve thermal energy transfer efficiency and thermal dissipation performance. Therefore, the thermal management capability of the system is improved, which is helpful to reduce the chip temperature, improve the reliability and stability of the system and improve the thermal management efficiency of the system.
By accurately estimating the thermal conductivity of the thermal vias, a designer may better understand the heat transfer path and heat dissipation effects of the circuit board. This enables optimization of hardware design and layout, such as adjusting the chip position, density, and placement to maximize heat dissipation and overall performance. Through more effective heat management, the dependence on other heat dissipation devices and system components can be reduced, so that the design is simplified, the hardware cost is reduced, and the once-through rate of the heat dissipation performance of the product is improved.
Through accurate thermal simulation calculation and evaluation, complicated modification and debugging in a later development stage can be avoided, so that the development period of the product is obviously shortened, the development cost is reduced, and the marketing speed and the competitiveness of the product are improved.
And the thermal conductivity of the thermal via hole below the chip is accurately estimated by utilizing theoretical calculation and measurement experience, and thermal simulation modeling is carried out, so that the computational power requirement of the thermal simulation can be reduced. This means that more efficient computing methods and hardware resources can be used, thus saving hardware costs.
The comprehensive application of the technical effects can provide a more efficient, reliable and economical solution for the design and development of domain controllers in the fields of new energy automobiles and the like.
It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements. The accompanying drawings are included to provide a better understanding of the present disclosure, and are not to be construed as limiting the disclosure, wherein:
FIG. 1 illustrates a schematic diagram of an example environment in which various embodiments of the present disclosure may be implemented;
FIG. 2 illustrates a schematic flow diagram of a thermal model determination method according to some embodiments of the present disclosure;
FIG. 3 illustrates a schematic diagram of a circuit board heat source chip and thermal via structure according to some embodiments of the present disclosure;
FIG. 4 illustrates a schematic isometric view of a thermal via arrangement area on a chip back side circuit board, according to some embodiments of the present disclosure;
FIG. 5 illustrates a thermal via Kong Shiyi magnification structure on a chip back side circuit board in accordance with some embodiments of the present disclosure;
FIG. 6 illustrates a schematic diagram of a simplified model of a circuit board heat source chip and thermal vias according to some embodiments of the present disclosure;
FIG. 7 illustrates an exploded view of a simplified model of a circuit board heat source chip and thermal vias according to some embodiments of the present disclosure;
FIG. 8 illustrates a schematic diagram of a packaged BGA model with heat source chip backside un-soldered pads, in accordance with some embodiments of the present disclosure;
fig. 9 illustrates a schematic diagram of a package QFN model with heat source chip backside passing through heat spreader pads in accordance with some embodiments of the present disclosure;
FIG. 10 illustrates a heat source chip and circuit board thermal via cross-sectional view according to some embodiments of the present disclosure;
FIG. 11 illustrates a schematic flow diagram of a thermal simulation method in accordance with some embodiments of the present disclosure;
FIG. 12 illustrates a schematic block diagram of a thermal model determination device according to some embodiments of the present disclosure;
FIG. 13 illustrates a schematic block diagram of a thermal simulation apparatus in accordance with some embodiments of the present disclosure; and
FIG. 14 illustrates a block diagram of an example computing device capable of implementing various embodiments of the disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.
As mentioned above, in the current technology, since there is at least one order of magnitude difference between the thermal via size and the circuit board and chip size, if the detailed thermal via model is directly built according to the actual size, the grid of the thermal simulation model grows exponentially, and a huge operation load is finally generated. In addition, the existing equivalent thermal model determining and thermal modeling method of the thermal via structure is simplified and replaced for a single thermal via, but if the equivalent model of each thermal via unit is respectively built according to the simplified method, the simplified thermal via is still quite complex and numerous, and huge grid quantity and corresponding calculated quantity still can be caused during simulation.
Based on the above, according to the embodiments of the present disclosure, a physical structure equivalent model near a thermal via area is first established, then thermal resistances of a via area and a non-via area of the physical structure equivalent model are measured and calculated, so as to obtain a target thermal conductivity of the physical structure equivalent model, and a target equivalent thermal model is obtained through the target thermal conductivity of the physical structure equivalent model, thereby remarkably improving the accuracy of chip junction temperature thermal simulation on a circuit board, and performing accurate simulation calculation and evaluation on the junction temperature of a heat source chip of the circuit board in a product development stage, so as to ensure the once-through rate of heat dissipation performance of the product.
Exemplary embodiments of the present disclosure will be described below in conjunction with fig. 1-14.
FIG. 1 illustrates a schematic diagram of an example environment 100 in which various embodiments of the present disclosure may be implemented. The environment 100 may integrally include a thermal simulation application 101 and a computing device 109, the thermal simulation application 101 being coupled to the computing device 109 to perform thermal simulation of the circuit board 103. Depending on the context, the circuit board 103 may be equally understood as a thermal simulation model corresponding to the circuit board 103 in the respective scenarios. The circuit board 103 may be, for example, an intelligent driving area controller circuit board or other circuit board in any other use scenario.
In some embodiments, computing device 109 may be any device having computing and communication capabilities. As non-limiting examples, the computing device 109 may be any type of fixed, mobile, or portable computing device, including but not limited to a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a multimedia computer, a personal computer, a server computer, a handheld device, a multiprocessor system, a consumer electronics, a minicomputer, a mainframe computer, a distributed computing environment that includes any of the above systems or devices, a virtual machine in a cloud platform, or other computing device, and the like. The computing device 109 may include components or modules for implementing the aspects provided herein, which may be, for example, part of an application running on the computing device 109.
In some embodiments, thermal simulation application 101 may be ANSYS, COMSOL, solidWorks, autodesk CFD, simScale, or any other suitable application. The thermal simulation application 101 may build a complete machine model of the circuit board 103 to perform thermal simulation at the circuit board 103 level. Accordingly, the thermal simulation application 101 may also locally model devices on the circuit board 103. The thermal simulation application 101 may be executed, in particular, by the computing device 109, alone or in part, to effect the corresponding operations.
With continued reference to fig. 1, the circuit board 103 may include a heat source chip 105 (also referred to as a "heat generating chip"). As mentioned previously, the heat source chip 105 belongs to the primary heat generating device on the circuit board 103 and may be generally provided with a plurality of thermal vias of a specific size thereunder, and various embodiments of the present disclosure will model the thermal via area to yield a complete thermal simulation model of the circuit board 103. In one embodiment, the thermal via area under the heat source chip 105 on the circuit board 103 may be simplified, for example, by the thermal simulation application 101, to obtain a target equivalent thermal model 107 associated with the thermal via. The target equivalent thermal model 107 may be, for example, a model corresponding to a rectangular parallelepiped region below the heat source chip 105 on the circuit board 103. In other embodiments, the target equivalent thermal model 107 may be obtained by other applications, software, or any other suitable means. The process of obtaining the target equivalent thermal model 107 associated with the thermal vias will be described in detail below in conjunction with fig. 2-10.
Fig. 2 illustrates a schematic flow diagram of a thermal model determination method 200 according to some embodiments of the present disclosure. The thermal model determination method 200 may be implemented by the computing device 109 of fig. 1. For ease of discussion, the thermal model determination method 200 will be described in connection with other related figures, including fig. 1.
At block 201, a physical structure equivalent model associated with thermal vias disposed under a heat source chip of a circuit board is determined, the physical structure equivalent model including thermal via regions and non-thermal via regions and having dimensional parameters associated with the circuit board and the heat source chip.
In one embodiment, as shown in FIG. 3, thermal vias 104 may be provided on the circuit board 103 below the heat source chip 105. The thermal vias may be small holes penetrating the printed circuit board 103, typically 0.4mm to 1.0mm in diameter, and the walls of the holes may be copper plated in such a way that the thermal conductivity of the circuit board 103 in the thickness direction may be significantly improved. As can be seen in fig. 3, the thermal vias 104 may be densely arranged below the heat source chip 105. The size parameter and the number of the thermal vias can be estimated initially according to specifications of the selected chip and the design instruction file of the internal circuit board of the company. The embodiment of the disclosure equivalent all the thermal vias under the heating chip to a model similar to the chip in size, and the equivalent model of the simplified thermal via 104 usually comprises dozens, so that the number and the calculated amount are obviously reduced under the condition of ensuring the calculation accuracy. To simplify the thermal model of the thermal vias, the area where the thermal vias 104 are located may be structurally equivalent to the physical structural equivalent model 102 shown in fig. 4. In this embodiment, the physical structure equivalent model 102 can be understood as the target equivalent thermal model 107 whose parameters such as thermal conductivity and simulation parameters are not confirmed.
Fig. 4 illustrates a schematic isometric view of a thermal via arrangement area on a chip back side circuit board, according to some embodiments of the present disclosure. As shown in fig. 4, the physical structure equivalent model 102 associated with the thermal via 104, which is obtained by equivalent of the physical structure under the circuit board 103, may include a thermal via region 104-1 and a non-thermal via region 104-2. The thermal via region 104-1 may be an opening region of all thermal vias 104, and the other regions may correspond to non-thermal via regions 104-2.
Fig. 5 illustrates a thermal via Kong Shiyi magnification structure on a chip back side circuit board in accordance with some embodiments of the present disclosure. In one embodiment, as shown in fig. 5, for a single thermal via 104, it may include an inner circular hole 1041 and an outer circular ring 1042. In some embodiments, the thermal resistance of the individual thermal vias 104 may be calculated using the thermal resistances of the inner circular holes 1041 and the outer circular ring 1042, respectively, for example, by determining the thermal resistance of the individual thermal vias 104 as the thermal resistance of the inner circular holes 1041 and the outer circular ring 1042 in parallel, as will be described in detail below.
In one embodiment, in response to determining that the heat source chip 105 is packaged by the heat dissipation pad, a rectangular parallelepiped region of the same thickness as the circuit board and the heat dissipation pad lower surface area may be determined as the physical structure equivalent model 102 according to the heat dissipation pad lower surface projection, and in response to determining that the heat source chip is not packaged by the heat dissipation pad, a rectangular parallelepiped region of the same thickness as the circuit board and the heat source chip lower surface area may be determined as the physical structure equivalent model 102 according to the heat source chip lower surface projection.
Fig. 6 illustrates a schematic diagram of a circuit board heat source chip and a simplified model of thermal vias according to some embodiments of the present disclosure. Fig. 7 illustrates an exploded view of a simplified model of a circuit board heat source chip and thermal vias according to some embodiments of the present disclosure.
As shown in fig. 6 and 7, the heat source chips 105 on the circuit board 103 can be classified into the following two types according to the package form: the chip 1051 is not pad-packaged by heat sink and the chip 1052 is pad-packaged by heat sink. For the non-heat-sink land-packaged chip 1051 and the heat-sink land-packaged chip 1052, the physical structure equivalent model 102 and the target equivalent thermal model 107 may be obtained in different ways.
In one embodiment, the non-heat-sink-pad packaged chip 1051 may be, for example, a BGA packaged chip as shown in fig. 8. Fig. 8 illustrates a schematic diagram of a packaged BGA model with heat source chip backside non-heat sink pads according to some embodiments of the present disclosure. As shown in fig. 8, the BGA package is a ball grid array package and the non-heat-sink-pad-packaged chip 1051 may include BGA package chip pins 10511. The non-heat-dissipating bond pad packaged chip 1051 and BGA packaged chip pins 10511 feature a set of small ball pads (called solder balls) at the bottom of the package for connection to corresponding bond pads on the printed circuit board. BGA packages typically have a higher number of BGA package chip pins 10511 and higher density for high performance and high integration integrated circuits. The solder balls provide reliable electrical connection and better heat dissipation properties while also facilitating the mounting and dismounting of the package.
In one embodiment, the bond pad packaged chip 1052 may be, for example, a QFN packaged chip as shown in fig. 9. Fig. 9 illustrates a schematic diagram of a packaged QFN model with heat source chips backside passed through heat spreader pads, in accordance with some embodiments of the present disclosure. As shown in fig. 9, the bond pad packaged chip 1052 may include QFN package chip pins 10521 and QFN package chip heat pads 10522. Referring to fig. 9, the heat-pad packaged chip 1052 is a flat, non-QFN packaged chip with exposed leads 10521. The bond pad packaged chip 1052 is typically composed of a lead frame and QFN package chip heat pads 10522, with the chip embedded inside the lead frame. The heat-sinking pad packaged chip 1052 is characterized by a small size, a small number of pins, and is suitable for use in space-limited applications, and typically uses soldering techniques (e.g., solder or balls) to attach the pins to a printed circuit board, providing electrical and mechanical connections. Since no leads are exposed, the heat-dissipating pad packaged chip 1052 has good heat dissipation performance, and can achieve higher density and reliability.
Thus, in the above embodiment, for the thermal via 104 on the lower circuit board of the pad packaged chip 1052 to be cooled, according to the projection of the lower surface of the heat dissipation pad 10522 of the QFN package chip, a rectangular block with the same area as the lower surface of the heat dissipation pad 10522 of the QFN package chip and the same thickness as the circuit board 103 is constructed to replace the original thermal via region 104-1 and non-thermal via region 104-2, so as to obtain the physical structure equivalent model 102 associated with the thermal via 104.
Further, for the thermal via 104 on the lower circuit board 103 of the chip 1051 that is not packaged by the heat dissipation pad, a rectangular block with the same area as the lower surface of the chip and the same thickness as the circuit board 103 can be constructed according to the projection of the lower surface of the chip to replace the original thermal via area 104-1 and non-thermal via area 104-2, so as to obtain the physical structure equivalent model 102 associated with the thermal via 104.
In one embodiment, the chip package form and the chip heat dissipation pad size may be extracted according to the heat source chip specifications and provided as input to the computing device 109.
It should be appreciated that other package types, such as QFP packages (quad flat packages), may also be employed for packages having heat dissipating pads, as this disclosure is not limited in this regard.
Fig. 10 illustrates a heat source chip and circuit board thermal via cross-sectional view showing the overall structure of circuit board 103 including a non-heat-dissipating land-packaged chip 1051, in accordance with some embodiments of the present disclosure. In some embodiments, as shown in fig. 10, the non-heat-dissipating land packaged chip 1051 is disposed on the upper surface of the circuit board 103 and includes BGA packaged chip pins 10511. The portion of the circuit board 103 not covered by the heat dissipation pad package chip 1051 is provided with a plurality of heat vias 104 designed in advance, and the apertures of the plurality of heat vias 104 may be the same or different, thereby helping the heat dissipation of the heat dissipation pad package chip 1051 in the thickness direction of the circuit board 103. The circuit board 103 is otherwise made of multiple layers of material, including for example a metal layer and an insulating material layer, and may specifically include for example a copper layer 1031 and an FR4 layer 1033, the thermal conductivity of which may be derived by superposition of the thermal conductivities of the multiple layers of material, as will be described in more detail below.
It should be appreciated that the above-described circuit board structure, packaging, heat source chip, and thermal via designs are exemplary and not limiting of the present disclosure, as any other suitable means may be employed to implement the concepts of the present disclosure.
At block 203, a first thermal resistance for the thermal via region 104-1 and a second thermal resistance for the non-thermal via region 104-2 are obtained. As mentioned above, the thermal via region 104-1 may be a set of locations of the thermal vias 104 opened in the physical structure equivalent model 102 under the heat source chip 105 of the circuit board 103, and the non-thermal via region 104-2 is a region other than the thermal via region 104-1.
In one embodiment, a first set of thermal resistances for each thermal via in the thermal via region 104-1 may be determined, for example, by a thermal resistance network method, and each thermal resistance in the first set of thermal resistances is connected in parallel to obtain a first thermal resistance for the thermal via region 104-1. Accordingly, a second set of thermal resistances of the multi-layer material of the circuit board 103 (e.g., the copper layer 1031 and the FR4 layer 1033 as shown in fig. 10) corresponding to the non-thermal via region 104-2 may be determined, for example, by a thermal resistance network method, and each thermal resistance of the second set of thermal resistances is connected in series to obtain a second thermal resistance for the non-thermal via region 104-2. Before the second thermal resistance calculation is performed, the number of layers and each layer thickness of the circuit board insulating material FR4 layer 1033 and the copper layer 1031 may be extracted according to a lamination file of the circuit board design, and the material thermal conductivity of the filling material of the insulating material FR4 layer 1033 and the copper layer 1031 may be determined.
In one embodiment, for the thermal resistance of the single thermal via 104 in the first set of thermal resistances, in conjunction with fig. 5, the thermal resistance of the inner circular hole 1041 and the thermal resistance of the outer ring 1042 may be obtained, for example, by a thermal resistance network method, and then the thermal resistances of the inner circular hole 1041 and the thermal resistance of the outer ring 1042 are connected in parallel, to obtain the thermal resistance of the single thermal via 104. Then, the thermal vias 104 in the physical structure equivalent model 102 are connected in parallel to obtain a first thermal resistance. In one embodiment, the filling material of the inner circular holes of the thermal vias may be determined from a stack file of the circuit board design, and if no filling material is present, the inner circular hole filling material is treated with air thermal conductivity.
At block 205, a target thermal conductivity for the physical structure equivalent model 102 is determined based on the first thermal resistance and the second thermal resistance. In one embodiment, the first thermal resistance and the second thermal resistance may be coupled in parallel to obtain a target thermal resistance for the physical structure equivalent model 102, and a target thermal conductivity for the physical structure equivalent model 102 based on the target thermal resistance. In another embodiment, the thermal resistance profile formed by the proportions of the portions may also be calculated based on the size of the individual components of the physical structure equivalent model 102.
It should be appreciated that after determining the target thermal resistance of the physical structure equivalent model 102, the thermal conductivity thereof may be derived based on other parameters of the physical structure equivalent model 102 (e.g., thickness of the item, thermal conductivity, etc.) and the thermal resistance, as will be described in detail below.
At block 207, a target equivalent thermal model 107 associated with the thermal via 104 is obtained based on the target thermal conductivity and the dimensional parameters.
In one embodiment, the dimensional parameters of the physical structure equivalent model 102 may be obtained, followed by applying boundary conditions on the physical structure equivalent model 102, followed by obtaining a target equivalent thermal model 107 associated with the thermal vias 104 based on the boundary conditions, the dimensional parameters, and the target thermal conductivity.
In one embodiment, as shown in fig. 7, a receiving hole 110 may be opened under the heat source chip 105, the receiving hole 110 having the same dimensional parameters as the physical structure equivalent model, and the physical structure equivalent model 102 (or the target equivalent thermal model 107) is embedded in the receiving hole with the contact thermal resistance set to zero.
The target thermal conductivity K of the target equivalent model 107 will be described below in connection with the exemplary embodiments of fig. 1 to 10 th Is a calculation method of (a).
In this embodiment, specifically, the thermal resistance of the open area is the thermal resistance of all the thermal vias from one side of the circuit board to the other side along the board thickness direction, the thermal resistance of the non-open area is the thermal resistance of the non-open area from one side of the circuit board to the other side along the board thickness direction, and the parallel heat transfer of two paths is formed, the equation of which is as follows:
Wherein R is Total (S) Representing the total thermal resistance after the first thermal resistance and the second thermal resistance are connected in parallel, R Total of holes Representing a first thermal resistance, R, of the thermal via region 104-1 Not provided with holes Representing a second thermal resistance of the non-thermal via region 104-2.
Taking the embodiment shown in fig. 10 as an example, the non-thermal via region 104-2 has a plurality of layers 1033 of insulating material FR4 and a plurality of layers 1031 of copper connected in series, and the calculation formula may be:
R not provided with holes ＝R Copper (Cu) +R Insulating material ；
The thermal resistance calculation formula of the copper layer can be:
wherein R is Copper (Cu) Is the thermal resistance of copper layer 1031, t Copper (Cu) Is the total thickness of all copper layers 1031, A Circuit board Is the total area of the un-perforated circuit board area (i.e. non-thermal via area 104-2),
similarly, insulating material (FR 4) R Insulating material The thermal resistance is calculated in the same manner as the thermal resistance of the copper layer 1031.
The first thermal resistance of the thermal via region 104-1 includes the inner circle Kong Rezu of a single thermal via, the outer circular thermal resistance with a plurality of thermal vias in parallel relationship, as follows:
wherein n is the number of thermal vias, R Single thermal via R is the thermal resistance of a single thermal via Inner round hole Is an inner circle Kong Rezu, R Outer ring Is the thermal resistance of the outer ring, R Total of holes A first thermal resistance representing the thermal via region 104-1;
the calculation formula of the thermal resistance of the inner round hole is as follows:
Wherein t is the thickness of the circuit board, k i Is the heat conductivity of the filling material of the inner circular holes, A i Is the area cross section of the inner round hole, A i ＝πd 2 4, d is the diameter of the inner circular hole;
similarly, the calculation formula of the thermal resistance of the outer circle and the thermal resistance of the inner circle hole is the same.
Next, using the relationship between the thermal conductivity and the thermal resistance, the thermal conductivity in the thickness direction of the entire circuit board 103 can be obtained, with the following formula:
wherein K is th The thermal conductivity of the circuit board in the thickness direction is obtained through theoretical calculation, and t is the thickness of the circuit board; w and L are the length and width of the thermal via region (i.e., the equivalent model of the physical structure) of the circuit board, R Total (S) Representing the total thermal resistance after the first thermal resistance and the second thermal resistance are connected in parallel.
Accordingly, in one embodiment, for the package having the heat dissipation pad under the heat source chip 105, such as QFN package (quad flat no-lead package), QFP package (quad flat package technology), and other packages, the thermal via 104 of the circuit board 103 under the heat source chip 105 is simplified to be a cuboid shape having a length equal to the length of the heat dissipation pad of the heat source chip 105 and a thickness equal to the thickness of the circuit board, and the target thermal conductivity in the thickness direction of the cuboid-area circuit board is calculated according to the thermal conductivity calculation method described above.
In yet another embodiment, for packages without heat dissipation pads under the heat source chip 105, such as BGA packages (ball grid array packages) and other packages, the thermal vias 104 of the circuit board 103 under the heat source chip 105 are reduced to a rectangular parallelepiped shape of equal length and width as the chip and thickness as the circuit board, and the target thermal conductivity of the rectangular parallelepiped region circuit board in the thickness direction is calculated according to the thermal conductivity calculation formula above.
Fig. 11 illustrates a schematic flow diagram of a thermal simulation method 1100 in accordance with some embodiments of the present disclosure. Thermal simulation method 1100 is implemented by computing device 109 shown in fig. 1. For ease of discussion, the thermal model determination method 1100 will be described in connection with other related figures, including fig. 1.
Referring to fig. 11, at block 1101, thermal simulation modeling is performed using a target equivalent thermal model, which may be target equivalent thermal model 107 shown in fig. 1, to obtain a thermal simulation model for a circuit board.
Referring to fig. 1, after the target thermal conductivity determination, the target equivalent thermal model 107 associated with the thermal vias is also built up. At this point, the parameters of the target equivalent thermal model 107 are applied to the overall model of the circuit board 103, and the junction temperature of the heat source chip on the circuit board is further obtained using the thermal simulation model at block 1013. Therefore, the heat dissipation capacity of the circuit board 103 can be accurately obtained through simulation, so that the design is simplified in the actual design, the hardware cost is reduced, and the once-through rate of the heat dissipation performance of the product is improved.
Fig. 12 illustrates a schematic block diagram of a thermal model determination device 1200 according to some embodiments of the present disclosure. As shown in fig. 12, the thermal model determining apparatus 1200 includes a thermal via equivalent model determining module 1201, a thermal resistance acquiring module 1203, a target thermal conductivity determining module 1205, and a target equivalent thermal model determining module 1207.
In the thermal model determination apparatus 1200, the thermal via equivalent model determination module 1201 is configured to determine a physical structure equivalent model associated with a thermal via disposed under a heat source chip of a circuit board, the physical structure equivalent model including a thermal via region and a non-thermal via region and having dimensional parameters associated with the circuit board and the heat source chip.
The thermal resistance acquisition module 1203 is configured to acquire a first thermal resistance for a thermal via region and a second thermal resistance for a non-thermal via region.
The target thermal conductivity determination module 1205 is configured to determine a target thermal conductivity for the physical structure equivalent model based on the first thermal resistance and the second thermal resistance.
The target equivalent thermal model determination module 1207 is configured to obtain a target equivalent thermal model associated with the thermal vias based on the target thermal conductivity and the dimensional parameters.
In some embodiments, the thermal via equivalent model determination module 1201 may be further configured to perform at least one of: in response to determining that the heat source chip is packaged by the heat dissipation pad, determining a cuboid area with the same area as the lower surface of the heat dissipation pad and the same thickness as the circuit board as a physical structure equivalent model according to the projection of the lower surface of the heat dissipation pad; and determining a cuboid area with the same area as the lower surface of the heat source chip and the same thickness as the circuit board as a physical structure equivalent model according to the lower surface projection of the heat source chip in response to determining that the heat source chip is not packaged by the heat dissipation pad.
In some embodiments, the thermal resistance acquisition module 1203 may be further configured to: determining a first set of thermal resistances for each thermal via in the thermal via region; connecting the thermal resistances in the first set of thermal resistances in parallel to obtain a first thermal resistance for the thermal via region; determining a second set of thermal resistances of the circuit board multilayer material corresponding to the non-thermal via region; each thermal resistor in the second set of thermal resistors is connected in series to obtain a second thermal resistor for the non-thermal via region.
In some embodiments, the thermal vias include an inner circular hole and an outer ring, and the thermal resistance acquisition module 1203 may be further configured to: obtaining inner circle Kong Rezu and outer circle thermal resistance; and connecting the inner circle Kong Rezu and the outer circle thermal resistor in parallel to obtain the thermal resistor of the thermal via.
In some embodiments, the target thermal conductivity determination module 1205 may be further configured to: coupling the first thermal resistance and the second thermal resistance in parallel to obtain target thermal resistance aiming at a physical structure equivalent model; and obtaining the target thermal conductivity based on the target thermal resistance.
In some embodiments, the target equivalent thermal model determination module 1207 may be further configured to: acquiring the target equivalent thermal model associated with the thermal vias may include: acquiring the size parameters of the equivalent model of the physical structure; applying boundary conditions on the physical structure equivalent model; and based on the boundary conditions, the dimensional parameters, and the target thermal conductivity, obtaining a target equivalent thermal model associated with the thermal via.
In some embodiments, the target equivalent thermal model determination module 1207 may be further configured to: forming a receiving hole under the heat source chip, wherein the receiving hole has the same size parameter as the physical structure equivalent model; and embedding the physical structure equivalent model into the receiving hole with the contact thermal resistance set to zero.
Fig. 13 illustrates a schematic block diagram of a thermal simulation apparatus 1300, according to some embodiments of the present disclosure. As shown in fig. 13, the thermal simulation apparatus 1300 includes a thermal simulation model acquisition module 1301 and a heat dissipation simulation module 1303. The thermal simulation model acquisition module 1301 is configured to perform thermal simulation modeling with a target equivalent thermal model obtained according to the thermal model determination method 200 to acquire a thermal simulation model for a circuit board. The heat dissipation simulation module 1303 is configured to perform heat dissipation simulation by using the thermal simulation model to obtain the junction temperature of the heat source chip on the circuit board.
Fig. 14 illustrates a block diagram of an example computing device 1400 capable of implementing various embodiments of the disclosure. Device 1400 may be used to implement computing device 109 of fig. 1. As shown in fig. 14, the apparatus 1400 includes a Central Processing Unit (CPU) 1401 that can perform various suitable actions and processes in accordance with computer program instructions stored in a Read Only Memory (ROM) 1402 or computer program instructions loaded from a storage unit 1408 into a Random Access Memory (RAM) 1403. In the RAM 1403, various programs and data required for the operation of the device 1400 can also be stored. The CPU 1401, ROM 1402, and RAM 1403 are connected to each other through a bus 1404. An input/output (I/O) interface 1405 is also connected to the bus 1404.
Various components in device 1400 are connected to I/O interface 1405, including: an input unit 1406 such as a keyboard, a mouse, or the like; an output unit 1407 such as various types of displays, speakers, and the like; a storage unit 1408 such as a magnetic disk, an optical disk, or the like; and a communication unit 1409 such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 1409 allows the device 1400 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunications networks.
The processing unit 1401 performs the respective methods and processes described above, such as the thermal model determination method 200 and/or the thermal simulation method 1100. For example, in some embodiments, the thermal model determination method 200 and/or the thermal simulation method 1100 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 1408. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 1400 via the ROM 1402 and/or the communication unit 1409. When the computer program is loaded into RAM 1403 and executed by CPU 1401, one or more steps of thermal model determination method 200 and/or thermal simulation method 1100 described above may be performed. Alternatively, in other embodiments, CPU 1401 may be configured to perform thermal model determination method 200 and/or thermal simulation method 1100 in any other suitable manner (e.g., by means of firmware).
The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a load programmable logic device (CPLD), etc.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
Moreover, although operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.
Claims (14)
1. A thermal model determination method, comprising:
Determining a physical structure equivalent model associated with a thermal via disposed under a heat source chip of a circuit board, the physical structure equivalent model including a thermal via region and a non-thermal via region and having dimensional parameters associated with the circuit board and the heat source chip;
acquiring a first thermal resistance for the thermal via region and a second thermal resistance for the non-thermal via region;
determining a target thermal conductivity for the physical structure equivalent model based on the first thermal resistance and the second thermal resistance; and
based on the target thermal conductivity and the dimensional parameter, a target equivalent thermal model associated with the thermal via is obtained.
2. The method of claim 1, wherein determining a physical structure equivalent model associated with a thermal via disposed under a heat source chip of a circuit board and a dimensional parameter of the physical structure equivalent model associated with the circuit board and the heat source chip comprises at least one of:
in response to determining that the heat source chip is packaged by a heat dissipation pad, determining a cuboid area with the same area as the lower surface of the heat dissipation pad and the same thickness as the circuit board as the physical structure equivalent model according to the lower surface projection of the heat dissipation pad; and
And determining a cuboid area with the same area as the lower surface of the heat source chip and the same thickness as the circuit board as the physical structure equivalent model according to the lower surface projection of the heat source chip in response to determining that the heat source chip is not packaged by the heat dissipation pad.
3. The method of claim 1, wherein obtaining a first thermal resistance for the thermal via region and a second thermal resistance for the non-thermal via region comprises:
determining a first set of thermal resistances for each thermal via in the thermal via region;
each thermal resistor in the first group of thermal resistors is connected in parallel to obtain first thermal resistors aiming at the thermal via area;
determining a second set of thermal resistances of the circuit board multilayer material corresponding to the non-thermal via region;
and connecting the thermal resistances in the second set of thermal resistances in series to obtain a second thermal resistance for the non-thermal via region.
4. The method of claim 1, wherein the thermal via comprises an inner circular hole and an outer circular ring, and wherein obtaining a first thermal resistance for the thermal via region and a second thermal resistance for the non-thermal via region comprises:
obtaining the inner circle Kong Rezu and the outer circle thermal resistance; and
And connecting the inner circle Kong Rezu and the outer circular thermal resistor in parallel to obtain the thermal resistor of the thermal via.
5. The method of claim 1, wherein determining a target thermal conductivity for the physical structure equivalent model based on the first thermal resistance and the second thermal resistance comprises:
coupling the first thermal resistance and the second thermal resistance in parallel to obtain target thermal resistance aiming at the equivalent model of the physical structure; and
and obtaining the target thermal conductivity based on the target thermal resistance.
6. The method of claim 1 or 2, wherein obtaining a target equivalent thermal model associated with the thermal via based on the target thermal conductivity and the dimensional parameter comprises:
acquiring the size parameter of the physical structure equivalent model;
applying a boundary condition on the physical structure equivalent model; and
a target equivalent thermal model associated with the thermal via is obtained based on the boundary condition, the dimensional parameter, and the target thermal conductivity.
7. The method of claim 6, wherein imposing boundary conditions on the physical structure equivalent model comprises:
forming a receiving hole under the heat source chip, wherein the receiving hole has the same size parameter as the physical structure equivalent model; and
Embedding the physical structure equivalent model into the receiving hole with the contact thermal resistance set to zero.
8. A thermal model determining device, characterized by comprising:
a thermal via equivalent model determination module configured to determine a physical structure equivalent model associated with a thermal via, the thermal via disposed under a heat source chip of a circuit board, the physical structure equivalent model including a thermal via region and a non-thermal via region and having dimensional parameters associated with the circuit board and the heat source chip;
a thermal resistance acquisition module configured to acquire a first thermal resistance for the thermal via region and a second thermal resistance for the non-thermal via region;
a target thermal conductivity determination module configured to determine a target thermal conductivity for the physical structure equivalent model based on the first thermal resistance and the second thermal resistance; and
a target equivalent thermal model determination module configured to obtain a target equivalent thermal model associated with the thermal via based on the target thermal conductivity and the dimensional parameter.
9. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 7.
10. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any of claims 1 to 7.
11. A thermal simulation method characterized by performing thermal simulation modeling with a target equivalent thermal model obtained according to the method of any one of claims 1 to 7 to obtain a thermal simulation model for a circuit board; and
and carrying out heat dissipation simulation by using the thermal simulation model to obtain the junction temperature of the heat source chip on the circuit board.
12. A thermal simulation apparatus, the apparatus comprising:
a thermal simulation model acquisition module configured to perform thermal simulation modeling with a target equivalent thermal model to acquire a thermal simulation model for a circuit board, wherein the target equivalent thermal model is obtained according to the method of any one of claims 1 to 7;
and the heat radiation simulation module is configured to perform heat radiation simulation by using the heat simulation model so as to obtain the junction temperature of the heat source chip on the circuit board.
13. An electronic device, comprising:
at least one processor; and
A memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of claim 11.
14. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of claim 11.
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