CN112152566A - Doherty power amplifier based on dynamic power distribution - Google Patents
Doherty power amplifier based on dynamic power distribution Download PDFInfo
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/04—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers
- H03F1/06—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers to raise the efficiency of amplifying modulated radio frequency waves; to raise the efficiency of amplifiers acting also as modulators
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Abstract
The invention provides a Doherty power amplifier based on dynamic power distribution, which comprises a dynamic power distributor, two paths of common source amplifiers and a power combiner, wherein the dynamic power distributor, the two paths of common source amplifiers and the power combiner are sequentially connected; the two-path common-source amplifier comprises two-path two-stage differential common-source amplifiers, eight neutralization capacitors and two inter-stage matching transformers, wherein the neutralization capacitors are arranged at the differential input and output ends of each stage of amplifier in a crossed manner, and the inter-stage matching transformers are respectively arranged between the first stage and the second stage of the main-path amplifier and the auxiliary-path amplifier; the dynamic power divider comprises three inductance coils and four capacitors, and the power combiner comprises three inductance coils. According to the dynamic power divider, the power division ratio of a signal to a main circuit amplifier and a sub-circuit amplifier is changed when an input signal changes through a load modulation effect, so that the whole linearity of a circuit is increased; the traditional quarter-wave line structure is replaced by a three-coil coupled power combiner, so that the load traction effect is generated, and the whole bandwidth of the circuit can be ensured.
Description
Technical Field
The invention relates to a Doherty power amplifier based on dynamic power distribution, belonging to the field of analog integrated circuit design.
Background
In recent years, the 5G technology has become a research hotspot. In a 5G communication system, one of the most critical components is a Power Amplifier (PA). Because the requirement of the communication system on linearity is high, a power amplifier in the communication system is often required to work in a back-off region, and a millimeter wave power amplifier with high power back-off efficiency is important for effectively transmitting a 5G modulation signal with a large peak-to-average power ratio. The linearity and efficiency of the power amplifier in the transceiver, and in particular the back-off efficiency, greatly limit the overall performance of the 5G communication system.
Among the various techniques for improving the back-off efficiency of power amplifiers, Doherty proposed Doherty power amplifier (Doherty pa) is a good choice, which can support a large modulation bandwidth and requires only a low baseband digital signal processing overhead. A conventional doherty power amplifier consists of two power amplifiers. One of the power amplifiers is biased in a class AB state and is called a main amplifier. The other power amplifier is biased in a class C state and is called a secondary amplifier. The outputs of the main and auxiliary amplifiers are combined by a quarter-wave line. After the Doherty power amplifier starts to work, the main amplifier and the auxiliary amplifier generate a dynamic load traction process due to the impedance transformation effect of the quarter-wave line, so that the main amplifier is saturated in advance, and the efficiency of the amplifier in a back-off region is improved. Since the quarter-wave line following the main amplifier will produce a 90 degree phase shift on the signal, a quarter-wave line is added to the input of the auxiliary amplifier for phase compensation.
The conventional Doherty power amplifier adopts a quarter-wavelength line structure to realize a power combining network of the main and auxiliary amplifiers, which limits the bandwidth of the conventional Doherty PA. The main circuit amplifier works in the A-class working state, and the auxiliary circuit amplifier works in the C-class working state, so that the integral gain and the saturation output power of the amplifier are not too high, and the linearity is influenced to a certain extent.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a Doherty power amplifier based on dynamic power allocation, so as to overcome the problems of poor linearity, narrow bandwidth, large chip area, and the like in the existing Doherty amplifier technology. The invention adopts the power synthesizer of the three coils to realize the load traction effect between the main amplifier and the auxiliary amplifier, so as to replace the quarter-wavelength line to bear the load conversion function, thereby solving the problem of narrow bandwidth of the quarter-wavelength line; meanwhile, the invention adopts the dynamic input power divider based on the input load impedance change, so that the power division ratio of the main circuit and the auxiliary circuit is changed along with the change of the input signal, thereby improving the linearity of the whole circuit.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a Doherty power amplifier based on dynamic power distribution, which is characterized by comprising a dynamic power distributor, two paths of common source amplifiers and a power synthesizer which are sequentially connected;
the two paths of common source amplifiers are divided into a main path amplifier and an auxiliary path amplifier, and each path of amplifier respectively comprises four neutralization capacitors, an interstage matching transformer and a path of two-stage differential common source amplifier consisting of four transistors; in the main circuit amplifier and the auxiliary circuit amplifier, a drain electrode of a first transistor is connected to a grid electrode of a second transistor through a first neutralization capacitor, a source electrode of the first transistor is connected with a source electrode of the second transistor and then grounded, and a drain electrode of the second transistor is connected to the grid electrode of the first transistor through a second neutralization capacitor; two ends of a primary coil in the two interstage matching transformers are respectively connected to drains of the first transistor and the second transistor, taps of the primary coil in the two interstage matching transformers are connected to a power supply VDD, two ends of a secondary coil in the two interstage matching transformers are respectively connected to gates of the third transistor and the fourth transistor, taps of the secondary coil in the two interstage matching transformers are respectively connected to a second-stage direct-current bias voltage VB _ M 'of the main amplifier and a second-stage direct-current bias voltage VB _ A' of the auxiliary amplifier, a drain of the third transistor is connected to a gate of the fourth transistor through a third neutralization capacitor, a drain of the fourth transistor is connected to a gate of the third transistor through a fourth neutralization capacitor, and a source of the third transistor and a source of the fourth transistor are connected and then grounded;
the dynamic power divider comprises three octagonal inductance coils and four capacitors; one end of the first inductance coil is connected to the GSG PAD, and the other end of the first inductance coil is grounded; two ends of the second inductance coil are respectively connected to the grids of the first transistor and the second transistor in the main circuit amplifier, and a tap of the second inductance coil is connected with a first-stage direct-current bias voltage VB _ M of the main circuit amplifier; two ends of a third inductance coil are respectively connected to the grids of a first transistor and a second transistor in the auxiliary circuit amplifier, and a tap of the third inductance coil is connected with a first-stage direct-current bias voltage VB _ A of the auxiliary circuit amplifier; one end of the first capacitor and one end of the third capacitor are respectively connected to the grids of the first transistor and the second transistor in the main circuit amplifier, and the other ends of the first capacitor and the third capacitor are grounded; one end of the second capacitor is connected to the grid of the transistor, and the other end of the second capacitor is grounded; one end of the second capacitor and one end of the fourth capacitor are respectively connected to the grid electrodes of the first transistor and the second transistor in the auxiliary circuit amplifier, and the other ends of the second capacitor and the fourth capacitor are grounded;
the power synthesizer comprises three octagonal inductance coils; two ends of a fourth inductance coil are respectively connected to the drain electrodes of a third transistor and a fourth transistor in the main circuit amplifier, and a tap of the fourth inductance coil is connected with a power supply VDD; two ends of a fifth inductance coil are respectively connected to the drain electrodes of a third transistor and a fourth transistor in the auxiliary circuit amplifier, and a tap of the fifth inductance coil is connected with a voltage VDD; one end of the sixth inductance coil is connected with the output GSG PAD, and the other end of the sixth inductance coil is grounded.
The invention has the technical characteristics and beneficial effects that:
1. the linearity of the Doherty power amplifier is improved. The dynamic power divider changes the power distribution ratio of the signal to the main and auxiliary amplifiers when the input signal changes through the load modulation effect. When the input signal is smaller, more signals are distributed to the main circuit amplifier, and the main circuit amplifier mainly plays a role in power amplification at the moment, so that the linearity and the gain of the circuit are ensured. When the input signal is increased, the main circuit amplifier enters a saturation state, more signals are distributed to the auxiliary circuit amplifier, and the auxiliary circuit amplifier plays a role of continuously playing the role of power amplification of the circuit, so that the linearity of the whole circuit is increased;
2. the bandwidth of the Doherty power amplifier is increased. The invention uses the three-coil coupling power synthesizer to replace the traditional quarter-wave line structure, and can ensure the whole bandwidth of the circuit while generating the load traction effect;
3. additional power consumption, chip area and chip complexity are not increased. The three-coil coupled power divider and the power combiner simultaneously and respectively play a role in matching input impedance and output impedance, so that the circuit does not need an additional matching network, and the passive loss and the area of a chip are reduced. The invention fully utilizes the structural characteristics of the three-coil structure, adopts a compact layout design and further reduces the area of a chip.
Drawings
Fig. 1 is a schematic circuit structure diagram of a Doherty power amplifier based on dynamic power allocation according to the present invention;
fig. 2 shows the relationship between the main and auxiliary input signals of the Doherty power amplifier of the present invention as a function of the power of the input signal.
Detailed Description
In order to make the objects, technical solutions and features of the present invention clearer and more clear, the following detailed description and description of specific embodiments are provided with reference to the accompanying drawings.
The circuit structure of the Doherty power amplifier based on dynamic power distribution is shown in figure 1, and the Doherty power amplifier comprises a dynamic power distributor, two paths of common source amplifiers and a power synthesizer which are connected in sequence; wherein:
the two-way common-source amplifier comprises two-way two-stage differential common-source amplifiers, eight neutralization capacitors and two interstage matching transformers, and particularly comprises eight transistors M1_ Ma, M1_ Mb, M1_ Aa, M1_ Ab, M2_ Ma, M2_ Mb, M2_ Aa and M2_ Ab, two interstage matching transformers T1 and T2, and eight neutralization capacitors C _ NEU _1, C _ NEU _2, C _ NEU _3, C _ NEU _4, C _ NEU _5, C _ NEU _6, C _ NEU _7 and C _ NEU _8, wherein the eight transistors M1_ Ma, M1_ Mb, M1_ Aa, M1_ Aa, M2_ Ma, M2_ Mb, M2_ Ab and M2_ Ab are NMOS transistors. The transistors M1_ Ma, M1_ Mb, M2_ Ma, and M2_ Mb, the neutralization capacitors C _ NEU _1, C _ NEU _2, C _ NEU _5, and C _ NEU _6, and the inter-pole matching transformer TI constitute a main amplifier biased in the class a state, with the transistors M1_ Ma and M1_ Mb as the first stage of the main amplifier, and the transistors M2_ Ma and M2_ Mb as the second stage of the main amplifier; the transistors M1_ Aa, M1_ Ab, M2_ Aa, and M2_ Ab, the neutralization capacitors C _ NEU _3, C _ NEU _4, C _ NEU _7, and C _ NEU _8, and the inter-pole matching transformer T2 constitute a secondary amplifier biased in a class C state, and the transistors M1_ Aa and M1_ Ab serve as a first stage of the secondary amplifier, and the transistors M2_ Aa and M2_ Ab serve as a second stage of the secondary amplifier. The connection relationship of each device is as follows: the drain electrode of the transistor M1_ Ma is connected to the gate electrode of the transistor M1_ Mb through a neutralization capacitor C _ NEU _1, the source electrode of the transistor M1_ Ma is connected with the source electrode of the transistor M1_ Mb and then grounded, and the drain electrode of the transistor M1_ Mb is connected to the gate electrode of the transistor M1_ Ma through a neutralization capacitor C _ NEU _ 2; two ends of a primary coil in an interstage matching transformer T1 are respectively connected to drains of transistors M1_ Ma and M1_ Mb, a tap of the primary coil in the interstage matching transformer T1 is connected to a power supply VDD, two ends of a secondary coil in the interstage matching transformer T1 are respectively connected to gates of transistors M2_ Ma and M2_ Mb, a tap of the secondary coil in the interstage matching transformer T1 is connected to a second pole direct-current bias voltage VB _ M', a drain of the transistor M2_ Ma is connected to a gate of the transistor M2_ Mb through a neutralization capacitor C _ NEU _5, a drain of the transistor M2_ Mb is connected to a gate of the transistor M2_ Ma through a neutralization capacitor C _ NEU _6, and a source of the transistor M2_ Ma and a source of the transistor M2_ Mb are connected and then grounded. The drain of the transistor M1_ Aa is connected to the gate of the transistor M1_ Ab through a neutralization capacitor C _ NEU _3, the source of the transistor M1_ Aa is connected to the source of the transistor M1_ Ab and then grounded, and the drain of the transistor M1_ Ab is connected to the gate of the transistor M1_ Aa through a neutralization capacitor C _ NEU _ 4; two ends of a primary coil in an interstage matching transformer T2 are respectively connected to drains of transistors M1_ Aa and M1_ Ab, a tap of the primary coil in the interstage matching transformer T2 is connected to a power supply VDD, two ends of a secondary coil in the interstage matching transformer T2 are respectively connected to gates of transistors M2_ Aa and M2_ Ab, a tap of the secondary coil in the interstage matching transformer T2 is connected to a second-stage direct-current bias voltage VB _ A', a drain of the transistor M2_ Aa is connected to a gate of the transistor M2_ Ab through a neutralization capacitor C _ NEU _7, a drain of the transistor M2_ Ab is connected to a gate of the transistor M2_ Aa through a neutralization capacitor C _ NEU _8, and a source of the transistor M2_ Aa and a source of the transistor M2_ Ab are connected to the ground. The gates of the transistors M1_ Ma and M1_ Mb serve as the input end of the main common-source amplifier, and the drains of the transistors M2_ Ma and M2_ Mb serve as the output end of the main common-source amplifier; gates of the transistors M1_ Aa and M1_ Ab serve as input terminals of the auxiliary common-source amplifier, and drains of the transistors M2_ Aa and M2_ Ab serve as output terminals of the auxiliary common-source amplifier. The amplifiers of the main circuit and the auxiliary circuit of the invention both adopt a two-stage differential common source amplifier structure; the differential input and output ends of the amplifiers at all levels improve the stability of the circuit by arranging cross-coupled neutralization capacitors, and avoid signal oscillation. The first stage and the second stage of the main circuit amplifier and the auxiliary circuit amplifier are respectively connected in a matching way by a transformer with two coils. The bias of the first stage of each amplifier is provided by the coil tap of the dynamic power divider, and the bias voltage of the second stage amplifier is provided by the tap of the inter-stage matching transformer.
A dynamic power divider comprising three octagonal inductors (L1_ D, L2_ D and L3_ D) and four capacitors (C1, C2, C3 and C4); in this embodiment, the inductor L1_ D is formed by M8 and M9 layers of metal, one end of the inductor L1_ D is connected to the input GSG PAD (ground-signal-ground PAD), and the other end is grounded; in this embodiment, the inductor L2_ D is formed by M8 layers of metal, two ends of the inductor L2_ D are respectively connected to the gates of the transistors M1_ Ma and M1_ Mb, and a tap of the inductor L2_ D is connected to the first-stage dc bias voltage VB _ M of the main amplifier; in this embodiment, the inductor L3_ D is formed by M9 layers of metal, two ends of the inductor L3_ D are respectively connected to the gates of the transistors M1_ Aa and M1_ Ab, and a tap of the inductor L3_ D is connected to the first-stage dc bias voltage VB _ a of the auxiliary amplifier; one end of the capacitor C1 is connected to the grid of the transistor M1_ Ma, and the other end is grounded; one end of the capacitor C3 is connected to the grid of the transistor M1_ Mb, and the other end is grounded; one end of the capacitor C2 is connected to the grid of the transistor M1_ Aa, and the other end is grounded; one end of the capacitor C4 is connected to the gate of the transistor M1_ Ab, and the other end is grounded. The dynamic power divider is used for changing the power dividing ratio of the signal to the main circuit amplifier and the auxiliary circuit amplifier when the input signal changes through the load modulation effect. The method specifically comprises the following steps: when the input signal is smaller (lower than 0dbm), more signals are distributed to the main circuit amplifier, and the main circuit amplifier mainly plays a role in power amplification, so that the linearity and the gain of the circuit are guaranteed. When the input signal becomes larger (larger than 0dbm), the main circuit amplifier enters a saturation state, the signal is more distributed to the auxiliary circuit amplifier, and the auxiliary circuit amplifier plays a role of continuously playing a role of power amplification of the circuit, so that the linearity of the whole circuit is improved. The capacitors C1-C4 are used to adjust the impedance point of the input matching network.
A power combiner comprising three octagonal inductors (L1_ C, L2_ C and L3_ C); in the embodiment, the inductor L3_ C is formed by M9 layers of metal and connected, two ends of the inductor L3_ C are respectively connected to the drains of the transistors M2_ Ma and M2_ Mb, and a tap of the inductor L3_ C is connected to the power supply VDD; in this embodiment, inductor L2_ C is made of M8 layers of metal, two ends of inductor L2_ C are connected to the drains of transistors M2_ Aa and M2_ Ab, respectively, and the tap of inductor L2_ C is connected to voltage VDD; in this embodiment, the inductor L1_ C is formed by M8 and M9 layers of metal, one end of the inductor L1_ C is connected to the output GSG PAD, and the other end is grounded.
In the Doherty power amplifier, the bias voltages VB _ M ', VB _ a', VB _ M and VB _ a are known quantities, and are respectively 0.5V, 0.6V and 0.3V in the embodiment.
The operating principle of the Doherty power amplifier of the invention is as follows:
the differential input signal is distributed to a main circuit amplifier and an auxiliary circuit amplifier of the first stage through a dynamic power distributor, and is output by a drain electrode of a transistor of the first stage fully differential common source amplifier after being amplified by the first stage fully differential amplifier; the output of the first-stage fully differential amplifier is connected to the grid of the amplifying tube of the second-stage fully differential amplifier through an interstage matching transformer, and the signal is amplified by the second-stage differential amplifier and then output by the drain electrode of the transistor of the second-stage differential common-source amplifier; the outputs of the main and auxiliary amplifiers are power combined by a three-coil power combiner.
The embodiments of the Doherty power amplifier circuit based on dynamic power allocation of the present invention are explained as follows:
in this embodiment, a 65nm CMOS process (which is a conventional fabrication process in the art) is used to fabricate a Doherty power amplifier circuit based on dynamic power allocation, and the simulation result is shown in fig. 2.
Figure 2 shows the main and auxiliary input signals as a function of the power of the input signal. It can be seen that when the dynamic power divider of the present invention is used, the power of the input signal allocated to the main circuit and the auxiliary circuit power amplifier in the circuit is obviously changed along with the change of the power of the input signal.
In summary, the invention can improve the linearity of the Doherty power amplifier.
The above examples demonstrate the correctness and effectiveness of the present invention. The above description is only for the Doherty power amplifier circuit of the invention with dynamic power distribution under a specific CMOS process and a specific frequency band, and is not intended to limit the scope of the invention.
Claims (1)
1. A Doherty power amplifier based on dynamic power distribution is characterized by comprising a dynamic power distributor, two paths of common source amplifiers and a power combiner which are sequentially connected;
the two paths of common source amplifiers are divided into a main path amplifier and an auxiliary path amplifier, and each path of amplifier respectively comprises four neutralization capacitors, an interstage matching transformer and a path of two-stage differential common source amplifier consisting of four transistors; in the main and auxiliary amplifiers, the drains of the first transistors (M1_ Ma and M1_ Aa) are connected to the gates of the second transistors (M1_ Mb and M1_ Ab) through first neutralization capacitors (C _ NEU _1 and C _ NEU _3), the sources of the first transistors (M1_ Ma and M1_ Aa) are connected to the sources of the second transistors (M1_ Mb and M1_ Ab) and then grounded, the drains of the second transistors (M1_ Mb and M1_ Ab) are connected to the gates of the first transistors (M1_ Ma and M1_ Aa) through second neutralization capacitors (C _ NEU _2 and C _ NEU _ 4); two ends of a primary coil of the two inter-stage matching transformers (T1 and T2) are respectively connected to drains of a first transistor (M1_ Ma and M1_ Aa) and a second transistor (M1_ Mb and M1_ Ab), taps of the primary coil of the two inter-stage matching transformers (T1 and T2) are respectively connected to a power supply VDD, two ends of a secondary coil of the two inter-stage matching transformers (T1 and T2) are respectively connected to gates of a third transistor (M2_ Ma and M2_ Aa) and a fourth transistor (M2_ Mb and M2_ Ab), a main tap of the secondary coil of the two inter-stage matching transformers (T1 and T588) is respectively connected to a second DC bias voltage VB _ M 'of the auxiliary circuit amplifier and a second DC bias voltage VB _ A' of the auxiliary circuit amplifier, drains of the third transistor (M6 _ Ma and M2_ NEC _ M27) are respectively connected to gates 2 and a third transistor (M27 _ Mb) and M2 of the auxiliary circuit amplifier, the drain electrodes of the fourth transistors (M2_ Mb and M2_ Ab) are connected to the gate electrodes of the third transistors (M2_ Ma and M2_ Aa) through fourth neutralization capacitors (C _ NEU _6 and C _ NEU _8), and the source electrodes of the third transistors (M2_ Ma and M2_ Aa) and the source electrodes of the fourth transistors (M2_ Mb and M2_ Ab) are connected to the ground;
the dynamic power divider comprises three octagonal inductance coils (L1_ D, L2_ D and L3_ D) and four capacitors (C1, C2, C3 and C4); one end of the first inductance coil (L1_ D) is connected to the GSG PAD, and the other end of the first inductance coil is grounded; two ends of a second inductance coil (L2_ D) are respectively connected to the grids of a first transistor (M1_ Ma) and a second transistor (M1_ Mb) in the main circuit amplifier, and a tap of the second inductance coil (L2_ D) is connected with a first-stage direct-current bias voltage VB _ M of the main circuit amplifier; two ends of the third inductance coil (L3_ D) are respectively connected to the grids of the first transistor (M1_ Aa) and the second transistor (M1_ Ab) in the auxiliary circuit amplifier, and a tap of the third inductance coil (L3_ D) is connected with the first-stage direct-current bias voltage VB _ A of the auxiliary circuit amplifier; one end of the first capacitor (C1) and one end of the third capacitor (C3) are respectively connected to the gates of the first transistor (M1_ Ma) and the second transistor (M1_ Mb) in the main amplifier, and the other ends of the first capacitor (C1) and the third capacitor (C3) are grounded; one end of the second capacitor (C2) and one end of the fourth capacitor (C4) are respectively connected to the gates of the first transistor (M1_ Aa) and the second transistor (M1_ Ab) in the auxiliary amplifier, and the other ends of the second capacitor (C2) and the fourth capacitor (C4) are grounded;
the power combiner comprises three octagonal inductive coils (L1_ C, L2_ C and L3_ C); two ends of a fourth inductance coil (L3_ C) are respectively connected with the drains of a third transistor (M2_ Ma) and a fourth transistor (M2_ Mb) in the main amplifier, and a tap of the fourth inductance coil (L3_ C) is connected with a power supply VDD; two ends of a fifth inductance coil (L2_ C) are respectively connected to the drains of a third transistor (M2_ Aa) and a fourth transistor (M2_ Ab) in the auxiliary amplifier, and a tap of the fifth inductance coil (L2_ C) is connected with the voltage VDD; one end of the sixth inductance coil (L1_ C) is connected with the output GSG PAD, and the other end is grounded.
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| CN112152566B (en) | 2022-07-05 |
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