CN112148366A

CN112148366A - FLASH acceleration method for reducing power consumption and improving performance of chip

Info

Publication number: CN112148366A
Application number: CN202010958159.XA
Authority: CN
Inventors: 时颖; 舒海军; 吴明勋
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd; Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd; Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2020-09-14
Filing date: 2020-09-14
Publication date: 2020-12-29

Abstract

The invention provides a design of a Flash acceleration controller, and adopts a data prefetching cache, an instruction field storage and a replacement algorithm controllable acceleration scheme. The acceleration scheme is selected through software configuration or self-adaptive dynamic switching, and system performance improvement under different scene requirements in embedded application is achieved. The main innovation points of the work of the method are as follows 1) Flash prefetching operation: for the sequential pre-fetching data, the pre-fetching operation is comprehensively used to realize the reading acceleration; for non-sequential pre-fetching data, an instruction cache technology and a data replacement principle of a least recently used algorithm are provided, and the pre-fetching missing cost is reduced; 2) high frequency instruction cache operation: the enabling can be controlled independently, the influence on the instruction fetching operation is reduced, and the performance is improved. 3) And the independent acceleration scheme of instruction fetching and data fetching is realized independently through a software control flow.

Description

FLASH acceleration method for reducing power consumption and improving performance of chip

Technical Field

The invention belongs to the technical field of low-power consumption chips. In particular to a FLASH acceleration method for reducing the power consumption and improving the performance of a chip.

Background

Flash is increasingly widely used as a nonvolatile memory module of instructions and data in the field of low-power-consumption and low-cost embedded chip soc (system on chip) design. In the embedded chip, a processor is responsible for tasks such as control, operating system platform and general signal processing, and Flash is used for storing instructions and data. The processor needs to access Flash to obtain the required instructions and data to complete the corresponding task operation. Usually most of the on-chip Flash space is used to store instructions, and the processor accesses the instructions more frequently. Compared with the performance of a processor which can be improved by instruction level parallelism, superscalar design and a large number of registers, the performance of the Flash can be improved only by a few methods such as process improvement. Therefore, as the performance of the processor is improved, the instruction fetching speed of Flash gradually becomes a bottleneck of the system performance. In other words, the overall performance of the embedded system chip SoC is directly affected and restricted by the speed of the Flash instruction fetching speed. Therefore, the research on how to improve the reading speed of Flash has important significance on improving the overall performance of the system.

Disclosure of Invention

The invention aims to solve the technical problem of improving the prior art, and provides a Flash acceleration controller which adopts a pre-fetching cache, an instruction field storage and a storage algorithm acceleration scheme. The acceleration scheme is selected through software configuration or self-adaptive dynamic switching, and system performance improvement under different scene requirements in embedded application is achieved.

In order to solve the above problems, the FLASH acceleration method for reducing power consumption and improving performance of the invention comprises five steps:

step 1: the high-frequency instruction is counted by software before data is written into flash or flash data is read in advance and stored in a high-frequency instruction cache region.

Step 2: and storing the prefetched flash data in a prefetching data module by the accelerated cache controller according to a least recently used algorithm LRU (least-recently used). The prefetch data module is divided into two parts: a sequential prefetch module, an LRU replacement module. When the cache controller prefetching data module has a null value, the cache controller prefetching data module can automatically fetch data from the flash and store the data in an idle position of the prefetching data module.

And step 3: and when the CPU accesses the flash data, the CPU preferentially reads the flash data from the pre-fetching data module. There is no priority distinction for the CPU access order prefetch module and the LRU replacement module. .

And 4, step 4: and when the data accessed by the CPU is not in the data pre-fetching module, storing the current jump instruction and simultaneously re-reading the data from the flash. Since data needs to be read again from the flash and the flash access speed is slow, a waiting period is inserted for the CPU access.

And 5: the data read from the flash are stored in the data pre-fetching module according to the least recently used algorithm, the data read from the flash are firstly stored in the sequential pre-fetching module, and the data of the LRU replacement module is replaced by the data of the sequential pre-fetching module according to the storage algorithm. And (5) circulating the steps 2-5.

Drawings

FIG. 1 is a block diagram of a flash acceleration method for reducing power consumption and improving performance;

FIG. 2 is a general flash read timing diagram;

FIG. 3flash accelerated read timing diagram

Detailed Description

The invention will be described in further detail with reference to the following detailed description and accompanying drawings:

the block diagram of the flash acceleration method for reducing power consumption and improving performance is shown in fig. 1 and comprises modules such as a flash, a data flow control module, an acceleration cache controller, a flash control module, a bus interface, an erasing module and the like.

Timing diagrams of the flash acceleration method for reducing power consumption and improving performance are shown in fig. 2 and fig. 3, wherein fig. 2 is a timing diagram of a delayed flash read, and fig. 3 is a timing diagram of the flash acceleration.

The method is realized by the following five steps:

And 5: and storing the data read from the flash into a data pre-fetching module according to the least recently used algorithm, storing the data read from the flash in a sequential pre-fetching module, and replacing the data of the LRU replacement module with the data of the sequential pre-fetching module according to a storage algorithm. And (5) circulating the steps 2-5.

Claims

1. A FLASH acceleration method for reducing power consumption and improving performance of a chip is characterized by mainly comprising the following steps:

step 1, an acceleration cache controller stores a command used at a high frequency in a flash in a high-frequency command cache region;

step 2, storing the prefetched flash data in a prefetching data module by an accelerated cache controller according to a least recently used algorithm LRU (least recently used);

step 3, when the CPU accesses the flash data, reading the flash data from the buffer of the data prefetching module preferentially;

step 4, when the data accessed by the CPU is not in the pre-fetching data module, storing the current jump instruction, and simultaneously reading the data from the flash again;

and 5, storing the data read from the flash into a pre-fetching data module according to the least recently used algorithm, and circulating the steps 2-5.

2. The chip power consumption reduction and performance improvement FLASH acceleration method according to claim 1, wherein the step 1: storing the instructions used at high frequency in the flash in a high-frequency instruction cache region by an acceleration cache controller:

the high-frequency instruction is counted by software before data is written into flash or flash data is read in advance and stored in a high-frequency instruction cache region.

3. The chip power consumption reduction and performance improvement FLASH acceleration method according to claim 1, wherein the step 2: according to least recently used algorithm LRU (least-recently used), the cache acceleration controller stores the prefetched flash data in the prefetching data module:

the data prefetching module is divided into two parts: the cache controller comprises a sequential prefetching module and an LRU replacement module, wherein the cache controller can automatically fetch data from a flash when the prefetching data module has a null value and store the data in an idle position of the prefetching data module.

4. The chip power consumption reduction and performance improvement FLASH acceleration method according to claims 1 and 3, characterized in that, the step 3: when the CPU accesses the flash data, the CPU preferentially reads from the prefetch data module:

wherein there is no priority distinction for the CPU access order prefetch module and the LRU replacement module.

5. The method for accelerating the FLASH with the chip power consumption reduced and the performance improved according to claim 1, wherein the step 4: when the data accessed by the CPU is not in the data pre-fetching module, the current jump instruction is stored, and simultaneously the data is read from the flash again:

in which a CPU access inserts a wait cycle because data needs to be read again from a flash and the flash access speed is slow.

6. The chip power consumption reduction and performance improvement FLASH acceleration method according to claims 1 and 3, characterized in that, the step 5: storing data read from the flash into a pre-fetching data module according to a least recently used algorithm, and circulating the steps 2-5:

the data read from the flash is firstly stored in the sequential prefetching module, and meanwhile, the data of the LRU replacement module is replaced by the data of the sequential prefetching module according to a storage algorithm.