JP2008052518A - Cpu system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the wait time of a CPU during the processing of a branch instruction in a CPU system that uses a high-speed DRAM. <P>SOLUTION: The CPU system 1 operates on condition that the operating speed of the CPU 2 is not more than the operating speed of an SDRAM 3 during a burst read. When the CPU 2 processes a branch instruction, a comparator 7 determines whether or not the instruction of a branch destination is stored in an instruction cache memory 5. If the instruction of the branch destination is stored in the instruction cache memory 5, the instruction is read from the instruction cache memory 5. Thus, when the CPU 2 processes the branch instruction, the need for the operation of reading instructions by accessing discontinuous addresses at the SDRAM 3 is eliminated. When the instruction cache memory 5 is hit as stated above, the need for the process of randomly accessing the SDRAM 3 is eliminated and the CPU 2 does not wait for operation. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a CPU system that once reads instructions of a program stored in a DRAM into a cache and supplies them to a CPU.

  In a CPU system such as a microcomputer mainly composed of a CPU (Central Processing Unit), programs read from the memory are sequentially executed. In recent years, the operating frequency of CPUs has been increased year by year in order to improve the operating speed of such CPU systems.

  Further, when a relatively low-speed DRAM (Dynamic Random Access Memory) is used as a memory in order to reduce the cost, the access of the DRAM is slow relative to the operation of the CPU, and thus the high-speed operation of the CPU system cannot be realized. For this reason, conventionally, a high-speed CPU system has been achieved by providing a cache between the CPU and a low-speed external memory (see, for example, Patent Document 1). Since the cache is a high-speed memory with a small capacity, the program and data required by the CPU are once read into the cache, and the CPU reads out necessary portions from the cache. In particular, a cache that stores program instructions is called an instruction cache (I-Cashe).

  If the necessary instruction is not in the instruction cache (if it is not hit), the CPU is in a wait (wait) state until the instruction is read from the DRAM into the instruction cache, and high-speed operation is impaired. For this reason, a method called prefetch (Pre-fetch) in which frequently required instructions are read from the DRAM in advance and read into the instruction cache using the continuity and repeatability of the instructions is used. As a result, if the CPU misses when reading a necessary instruction in the instruction cache, the necessary instruction is read from the DRAM into the prefetch buffer and the instruction is read from the prefetch buffer into the instruction cache and the CPU. Therefore, the weight of the CPU can be shortened by such an operation.

In the conventional method for accessing the instruction cache, the above operation is performed every time the CPU accesses regardless of whether the instruction is a branch (jump, branch, call, return) instruction or not.
JP 2003-162446 A (released on June 6, 2003)

  By the way, in recent years, DRAMs have been accelerated, and high-speed DRAMs such as SDRAM (Synchronous DRAM), DDR-SDRAM (Double Data Rate DRAM), RDRAM (Rumbus DRAM), and XDRDRAM (eXtreme Data Rate DRAM) have become widespread. Yes. Therefore, the use of such a high-speed DRAM in a CPU system is also being promoted.

  Further, when the CPU system is manufactured by an application specific integrated circuit (ASIC), either a full custom ASIC or a semi-custom ASIC is selected. In the case of manufacturing with a full custom ASIC, since high integration is possible, the operating frequency of the CPU can be increased to 1 GHz, but the design cost increases. On the other hand, when a semi-custom ASIC such as a gate array or a cell base is used, the design cost can be reduced by using standard gates and function blocks prepared in advance, but the degree of integration is inferior to that of a full custom ASIC. The operating frequency of the CPU is as low as 100 MHz.

  When a high-speed DRAM is incorporated in a CPU system manufactured with such a semi-custom ASIC, the operation speed of the CPU may be lower than the burst read operation speed by performing the burst read operation of the high-speed DRAM. Under these conditions, when program instructions are read sequentially and sequentially from the DRAM, the instructions are read by the burst read operation of the DRAM and read into the CPU via the prefetch buffer. Can be read. Therefore, in this case, no instruction cache is required. On the other hand, when the instruction is a branch instruction, in the DRAM, the discontinuous address is accessed and the instruction is read, so that the continuity of processing including processing in the CPU (pipeline processing) is lost. At this time, since it is necessary to perform RAS (Row Address Strobe) or CAS (Column Address Strobe) processing for the DRAM, the CPU operation waits during this time.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to shorten the wait time of a CPU when processing a branch instruction in a CPU system using a high-speed DRAM.

  The CPU system according to the present invention stores at least a high-speed DRAM capable of storing a program and capable of a burst read operation and a branch destination instruction specified by a branch instruction in the program, and the instruction is stored in the high-speed DRAM. An instruction cache memory that stores an address to be designated, a CPU that processes an instruction of the program read from the instruction cache memory, and that operates at an operation speed lower than the operation speed of the high-speed DRAM during a burst read operation; Determining means for determining whether or not the branch destination instruction specified by the branch instruction is stored in the instruction cache memory when the CPU processes the branch instruction read from the high-speed DRAM; When it is determined that the previous instruction is stored in the instruction cache memory It is characterized by comprising an instruction output means for outputting the branch target instruction read from the instruction cache memory to the CPU.

  In the above configuration, the CPU operates at an operation speed lower than the operation speed of the high-speed DRAM during the burst read operation. Under these operating conditions, when instructions (non-branch instructions) read from the high-speed DRAM are successively processed sequentially by the CPU, the instructions are continuously read by the DRAM burst read operation and read into the CPU 2. . As a result, the CPU can read the instruction without waiting. Therefore, in this case, there is no need to read an instruction from the instruction cache memory.

  On the other hand, when the CPU processes the branch instruction, the determination unit determines whether or not the branch destination instruction specified by the branch instruction is stored in the instruction cache memory. If it is determined that the branch destination instruction is stored in the instruction cache memory, the instruction output unit outputs the branch destination instruction read from the instruction cache memory to the CPU. As a result, if the branch destination instruction is stored in the instruction cache memory, the CPU does not wait for the operation of the CPU even when the branch instruction is processed by reading the branch destination instruction into the CPU.

  In the CPU system, the CPU outputs an address designating the branch instruction, and when the CPU system determines that the branch destination instruction is not stored in the instruction cache memory, the CPU reads the address from the high-speed DRAM to the address. It is preferable that a read control unit is provided for reading the branch destination instruction based on the instruction cache memory, and the instruction cache memory stores the branch destination instruction read from the high-speed DRAM.

  In the above configuration, when the determination result by the determination unit is negative, the read control unit reads the branch destination instruction from the high-speed DRAM based on the address output from the CPU, and the branch destination instruction is read from the instruction cache. Stored in memory. In this case, since the branch destination instruction cannot be read from the instruction cache memory when the CPU processes the branch instruction, the CPU operation waits until the branch destination instruction is stored in the instruction cache memory from the high-speed DRAM. End up. However, once a branch destination instruction that is read relatively repeatedly is stored in the instruction cache memory, when the subsequent branch instruction designates the branch destination instruction, the branch destination instruction is read from the instruction cache memory. It can be read immediately.

  As described above, the CPU system according to the present invention includes the above-described high-speed DRAM, instruction cache memory, CPU, determination means, and instruction output means, so that when the CPU processes a branch instruction, In a high-speed DRAM, an operation of accessing a discontinuous address and reading an instruction becomes unnecessary. Therefore, it is possible to maintain the continuity of the processing of the entire CPU system including the processing in the CPU.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 3 as follows.

  As shown in FIG. 1, the CPU system 1 includes a CPU 2, an SDRAM 3, an instruction cache memory 5, a prefetch buffer 6, a comparator 7, a selector 8, an octal counter 9, an RS flip-flop 10, an AND Gates 11 and 12 and an adder 13 are provided. The CPU system 1 is manufactured by, for example, a semi-custom ASIC.

  Note that in FIG. 1, among the connection lines between the circuits, a thick solid line represents a multi-bit signal line, and a thin solid line represents a 1-bit signal line.

  The CPU 2 has a CPU core 2a that processes input program instructions (program codes) in parallel by pipeline processing. The operation speed (operation frequency) of the CPU 2 is equal to or less than the operation speed (operation frequency) at the time of burst read operation of the SDRAM 3 described later. The CPU core 2a outputs a jump destination address JumpAdd and a branch instruction identification signal BranchSig. The jump destination address JumpAdd is a branch destination instruction specified by the branch instruction, and is an address of an area in which the instruction is stored in the SDRAM 3. The branch instruction identification signal BranchSig is a signal for identifying whether or not the instruction processed by the CPU core 2 is a branch instruction. When executing the branch instruction, the CPU core 2a outputs a jump destination address JumpAdd and a branch instruction identification signal BranchSig. That is, the branch instruction identification signal BranchSig is “1” when the instruction is a branch instruction, and is “0” when the instruction is not a branch instruction.

  The SDRAM 3 stores programs and data, and reading and writing of the programs and data are controlled by the control of the DRAM controller 4. The SDRAM 3 is provided in the CPU system 1 as a high-speed DRAM. However, as the high-speed DRAM, the above-described DDR-SDRAM, RDRAM, XDRDRAM, or the like may be provided instead of the SDRAM 3.

  The DRAM controller 4 is a control circuit that controls reading and writing of programs and data by the SDRAM 3. Here, reading and writing of the program of the DRAM controller 4 will be described.

  The DRAM controller 4 receives the jump address JumpAdd and the branch instruction identification signal BranchSig as control signals. When the jump destination address JumpAdd is input from the adder 13 when the branch instruction identification signal BranchSig is “1”, the DRAM controller 4 performs a preparatory operation for reading the program (program code) to the SDRAM 3. Read the instruction of the jump destination address JumpAdd. Specifically, the above preparation operation includes an output of a RAS signal for designating a row address of an access destination memory cell, an output of a CAS signal for designating a column address of the memory cell, and the like.

  The instruction cache memory 5 is a small-capacity cache memory that can operate at a higher speed than the SDRAM 3. The instruction cache memory 5 has an area for storing an instruction (program code) for 8 steps read from the SDRAM 3, an address of a storage area of the instruction in the SDRAM 3, and a valid / write bit. . The valid / write bit is “1” when a valid instruction is stored in the instruction cache memory 5, and when a valid instruction is not stored in the instruction cache memory 5 (when the instruction is writable). ) Becomes “0”. The instruction cache memory 5 is written with the same instruction as the instruction read from the SDRAM 3 and written to the prefetch buffer 6 when the branch instruction identification signal BranchSig is “1” and there is no hit.

  The prefetch buffer 6 is a buffer memory for prefetching to the instruction cache memory 5, and is constituted by, for example, a FIFO (First In First Out) memory. The prefetch buffer 6 is written with the instruction read from the SDRAM 3 when the branch instruction identification signal BranchSig is “1” and the instruction cache memory 5 is hit.

  The selector 8 outputs the instruction read from the prefetch buffer 6 input from the input terminal A to the CPU 2 from the output terminal Y when the hit determination signal Hit is “0”. The selector 8 outputs the instruction read from the instruction cache memory 5 input from the input terminal B to the CPU 2 from the output terminal Y when the hit determination signal Hit is “1”. The hit determination signal Hit is a signal indicating whether or not the instruction cache memory 5 has been hit, and becomes “1” when hit and becomes “0” when it does not hit.

  The comparator 7 compares the above jump destination address JumpAdd output from the CPU core 2a with all the addresses stored in the instruction cache memory 5, and uses the branch instruction identification signal BranchSig output from the CPU core 2a. The valid / write bit stored in the instruction cache memory 5 is compared. As a result of the comparison, the comparator 7 outputs a hit determination signal Hit of “1” when both addresses match and the branch instruction identification signal BranchSig and the valid / write bit are both “1”. In other cases, a hit discrimination signal Hit of “0” is output.

  The octal counter 9 is provided to detect that instructions are written in the instruction cache memory 5 for 8 steps. The octal counter 9 counts a pulse output every time an instruction is written from the instruction cache memory 5 and outputs a count-up signal ("1") and resets itself when counting eight pulses. To do.

  The RS flip-flop 10 is set when the branch instruction identification signal BranchSig output from the CPU core 2a changes from “0” to “1”, and changes the value of the output terminal Q from “0” to “1”. Let The RS flip-flop 10 is reset when the count-up signal output from the octal counter 9 changes from “0” to “1”, and the value of the output terminal Q is changed from “1” to “0”. Change. As a result, when the instruction cache memory 5 is hit, the value of the branch instruction identification signal BranchSig is held until the instruction is read and all the instructions for eight steps in the instruction cache memory 5 are rewritten, and the instruction When the rewriting is completed, the input to the comparator 7 is set to “0” until the next new branch instruction identification signal BranchSig is output.

  The AND gate 11 outputs a logical product of the inverted signal of the hit determination signal Hit and the output from the RS flip-flop 10. This logical product is input to the CPU core 2a as a wait signal wait. When a wait signal wait of “1” is input, the CPU core 2a enters a wait (wait) state and stops pipeline processing. On the other hand, when a wait signal wait of “0” is input, the CPU core 2a operates. Perform line processing.

  The AND gate 12 outputs a logical product of the hit determination signal Hit from the comparator 7 and data indicating “8”. Thus, when the hit determination signal Hit is “1” (when hit), the input data is output as it is, while when the hit determination signal Hit is “0” (when no hit occurs), the input data Is not output.

  The adder 13 adds the jump destination address JumpAdd and the output data from the AND gate 12 and outputs the result to the DRAM controller 4.

  Next, the operation of the CPU system 1 configured as described above will be described.

  First, when the CPU core 2a processes an arithmetic instruction other than a branch instruction, the instruction read from the SDRAM 3 by the burst read operation is temporarily stored in the prefetch buffer 6 and then given to the CPU 2 via the selector 8. .

  When instructions (non-branch instructions) read from the SDRAM 3 are sequentially processed sequentially by the CPU 2, the instructions are continuously read by the burst read operation of the SDRAM 3 and read into the CPU 2 via the prefetch buffer 6. It is. As a result, the CPU 2 can read an instruction without waiting. Therefore, in this case, there is no need to read an instruction from the instruction cache memory 5.

  At this time, since the RS flip-flop 10 is in a reset state, the comparator 7 determines that the valid / write bit (“1”) of the output “0” of the RS flip-flop 10 does not match, Since the jump address JumpAdd is not output from the CPU core 2a, the hit determination signal Hit output from the comparator 7 is "0".

  Thereby, the selector 8 connects the prefetch buffer 6 and the CPU 2. Since the output of the S flip-flop 10 is “0”, the wait signal wait is also “0”. At this time, the branch instruction identification signal BranchSig output from the CPU core 2a is "0".

  As shown in FIG. 2, when the CPU core 2a processes the branch instruction BR50 obtained from the prefetch buffer 6, since the branch instruction identification signal BranchSig becomes “1”, the RS flip-flop 10 is set to “1”. 1 "is output. Further, the jump address JumpAdd is output from the CPU core 2a. At this time, the CPU core 2a interrupts the processing of the instruction following the branch instruction BR50 and stops the pipeline processing.

  Specifically, the operation up to the pipeline stop proceeds as shown in FIG. First, in stage 1, branch instruction BR50 is read (fetched) at time T1, and in subsequent stage 2, address calculation instruction Add is read at time T1, and branch instruction BR50 is decoded at time T2. Further, in stage 3, the load instruction LD is read at time T1, the address calculation instruction Add is decoded at time T2, and the branch instruction BR50 is executed at time T3. Thus, the CPU core 2a stops the pipeline processing and changes the branch instruction identification signal BranchSig from “0” to “1”.

  As described above, a time lag occurs after the branch instruction BR50 is read into the CPU core 2a by pipeline processing until the value of the branch instruction identification signal BranchSig changes as described above. There are also conditional branch instructions, and such branch instructions may not jump depending on the condition.

  On the other hand, the comparator 7 compares the jump destination address JumpAdd with the address registered in the instruction cache memory 5 and compares the output of the RS flip-flop 10 with the valid / write bit. When the output of the RS flip-flop 10 and the valid / write bit are both “1”, if the same address as the jump destination address JumpAdd is registered in the instruction cache memory 5, as shown in FIG. The hit determination signal Hit output is “1” and hits.

  Thereby, the selector 8 connects the instruction cache memory 5 and the CPU 2. Therefore, the branch destination instruction SUB designated by the jump destination address JumpAdd read from the instruction cache memory 5 and the instructions for the subsequent 7 steps are sequentially read and given to the CPU 2.

  When an instruction for 8 steps is read from the instruction cache memory 5, a new instruction following it is required. For this reason, when the instruction is read from the instruction cache memory 5 as described above, the adder 13 adds the jump destination address JumpAdd and the data “8” output via the AND gate 12. The resulting address (eight addresses after the jump address JumpAdd) is given to the DRAM controller 4. The DRAM controller 4 sequentially reads instructions from the SDRAM 3 based on the address. The read instruction is temporarily stored in the prefetch buffer 6 and waits for reading to the CPU 2.

  At this time, that is, when the hit determination signal Hit is “1” (when hit), it is not necessary to read into the instruction cache memory 5 a branch destination instruction for hitting, as in the case of no hit as will be described later. . Therefore, the instruction read from the SDRAM 3 is not written in the instruction cache memory 5.

  In the comparison of the comparator 7 described above, if the same address as the jump destination address JumpAdd is not registered in the instruction cache memory 5, the hit determination signal Hit output from the comparator 7 is “0” and does not hit. At this time, since the wait signal wait output from the AND gate 11 is “1”, the CPU 2 enters a wait state. The jump address JumpAdd is stored and registered in the instruction cache memory 5 and is output to the DRAM controller 4 via the adder 13 as it is.

  Based on the jump destination address JumpAdd, the DRAM controller 4 sequentially reads the branch destination instruction and the subsequent instruction from the SDRAM 3. The read instruction is temporarily stored in the prefetch buffer 6 and waits for reading to the CPU 2. At this time, since the hit determination signal Hit is “0”, it is necessary to read into the instruction cache memory 5 a branch destination instruction to be hit. Therefore, the instruction read from the SDRAM 3 is also written in the instruction cache memory 5.

  As a result, in the comparison by the comparator 7, the jump destination address JumpAdd and the address registered in the instruction cache memory 5 match, so the hit determination signal Hit becomes “1”. Therefore, in this case, the newly written branch destination instruction and the subsequent instruction are read from the instruction cache memory 5 and are given to the CPU 2 via the selector 8. At this time, since the wait signal wait is “1”, the CPU 2 processes the input instruction.

  As described above, the CPU system 1 according to the present embodiment operates under the condition that the operation speed of the CPU 2 is equal to or lower than the operation speed at the time of burst read of the SDRAM 3, and the CPU 2 branches to the instruction cache memory 5 when processing the branch instruction. If the previous instruction is stored, the instruction is read from the instruction cache memory 5. This eliminates the need for the SDRAM 3 to access discontinuous addresses and read the instructions when the CPU 2 processes a branch instruction. Therefore, the continuity of processing including processing in the CPU 2 (pipeline processing) is eliminated. Can be maintained. Further, when the instruction cache memory 5 is hit as described above, the SDRAM 3 does not need to be subjected to RAS or CAS processing, and the operation of the CPU 2 is not waited.

  Further, in the CPU system 1, since the instruction cache memory 5 stores instructions for 8 steps of the branch destination instruction and the subsequent instruction, a general instruction cache memory for storing a memory block (128-byte unit) in a certain degree. Does not require a large capacity.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  In the CPU system of the present invention, when the CPU processes a branch instruction, if the instruction at the branch destination is stored in the instruction cache memory, the instruction is read from the instruction cache memory, thereby further improving the continuity of processing. Therefore, it can be suitably used for a system such as a microcomputer manufactured by a semi-custom ASIC.

1 is a block diagram illustrating a configuration of a CPU system according to an embodiment of the present invention. It is a timing chart which shows operation | movement of the said CPU system. It is a figure which shows the pipeline operation | movement of CPU when processing the branch instruction in the said CPU system.

Explanation of symbols

1 CPU system 2 CPU
2a CPU core 3 SDRAM (high-speed DRAM)
4 DRAM controller 5 Instruction cache memory 6 Prefetch buffer 7 Comparator 8 Selector 9 Octal counter 10 RS flip-flops 11 and 12 AND gate 13 Adder

Claims (2)

A high-speed DRAM that stores a program and is capable of burst read operation;
An instruction cache memory that stores at least a branch destination instruction specified by a branch instruction in the program and stores an address that specifies the instruction in the high-speed DRAM;
A CPU that processes an instruction of the program read from the instruction cache memory and operates at an operation speed equal to or lower than an operation speed of the high-speed DRAM during a burst read operation;
Determining means for determining whether or not the branch destination instruction designated by the branch instruction is stored in the instruction cache memory when the CPU processes the branch instruction read from the high-speed DRAM;
When it is determined that the branch destination instruction is stored in the instruction cache memory, an instruction output unit that outputs the branch destination instruction read from the instruction cache memory to the CPU is provided. CPU system. The CPU outputs an address designating the branch instruction;
The CPU system includes a read control unit that reads the branch destination instruction from the high-speed DRAM based on the address when it is determined that the branch destination instruction is not stored in the instruction cache memory.
The CPU system according to claim 1, wherein the instruction cache memory stores the branch destination instruction read from the high-speed DRAM.

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