CN116627335A - Low-power eFlash reading acceleration system - Google Patents

Low-power eFlash reading acceleration system Download PDF

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Publication number
CN116627335A
CN116627335A CN202310601810.1A CN202310601810A CN116627335A CN 116627335 A CN116627335 A CN 116627335A CN 202310601810 A CN202310601810 A CN 202310601810A CN 116627335 A CN116627335 A CN 116627335A
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module
prefetch
instruction
bus interface
request address
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CN202310601810.1A
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Inventor
姜良超
彭崇梅
郗盛凯
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN202310601810.1A priority Critical patent/CN116627335A/en
Publication of CN116627335A publication Critical patent/CN116627335A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

The application relates to a reading acceleration system of low-power eFlash, belongs to the field of memory control, and solves the problems of low data hit rate, poor acceleration effect of prefetching operation and introduction of extra power consumption in a prefetching register in the prior art. The system comprises: the AHB bus interface module is used for receiving the request address and sending the request address to the prefetch control module and the cache module; the prefetch control module comprises a buffer module, and the buffer module and the cache module judge whether matched instructions exist according to the request address; when the instructions in the buffer module and the Cache module are not matched with the request address, the AHB bus interface module sends an instruction missing signal to the prefetch control module, the prefetch control module outputs the updated prefetch line number, the instructions are obtained from the eFlash memory according to the prefetch line number, the instructions corresponding to the request address are sent to the CPU and stored in the Cache module, and meanwhile the instructions of the prefetch line number after the request address are stored in the buffer module. The prefetching speed is accelerated, the prefetching length can be dynamically adjusted, and the power consumption is reduced.

Description

Low-power eFlash reading acceleration system
Technical Field
The application relates to the technical field of memory control, in particular to a reading acceleration system of low-power eFlash.
Background
The reading speed of eFlash is the key to influence the overall performance, taking a microcontroller (Microcontroller Unit; MCU) as an example, the working frequency of the high-performance MCU can reach hundreds of megahertz at present, which is far higher than the reading speed of the main current eFlash by tens of megahertz, and the low-speed eFlash reading speed influences the instruction fetching speed of the CPU and restricts the performance of the CPU.
According to the spatial locality and the temporal locality of the software program, the common practice for solving the problem of eFlash acceleration is to add a prefetch module and a Cache (Cache) and select eFlash with high bit width. When the CPU sends out the command of reading the command, the pre-fetching operation reads the current command and reads the next continuously stored command line of the command into the pre-fetching register, and when the subsequent CPU accesses the pre-fetched command, the subsequent CPU can directly read the command from the pre-fetching register without access delay; the cache memory is used for solving the problem of missing the jump instruction, the sequential prefetching has higher hit rate only when the spatial locality of the program is better, the jump instruction cannot be accurately prefetched when the jump instruction occurs, the jump instruction is stored in the cache memory at the moment, and the instruction can be hit through the cache memory when the next jump instruction occurs. The eFlash with high bit width can fetch a plurality of instructions at a time, thereby reducing access delay in instruction prefetching.
Disclosure of Invention
In view of the above analysis, the embodiment of the present application aims to provide a low-power eFlash read acceleration system, which is used for solving the problems of low data hit rate, poor prefetch operation acceleration effect and additional power consumption introduced in the prefetch register in the prior art.
In one aspect, an embodiment of the present application provides a low power consumption eFlash read acceleration system, where the acceleration system includes: the system comprises an AHB bus interface module, a prefetch control module, a cache module and an eFlash memory;
the AHB bus interface module is used for receiving a request address of an external CPU and sending the request address to the prefetch control module and the cache module;
the prefetch control module comprises a buffer module, wherein the buffer module and the cache module judge whether the respective stored instructions have instructions matched with the request address according to the request address, and if so, the instructions are transmitted to the CPU through the AHB bus interface module;
when the instructions in the buffer module and the Cache module are not matched with the request address, the AHB bus interface module sends an instruction missing signal to the prefetch control module, the prefetch control module outputs the updated prefetch line number according to the request address and the instruction corresponding to the instruction in the buffer module, acquires the instruction of the request address and the subsequent prefetch line number from the eFlash memory according to the prefetch line number, sends the instruction corresponding to the request address to the CPU through the AHB interface module, stores the instruction in the Cache module, and stores the instruction of the prefetch line number after the request address to the buffer module.
Further, the prefetch control module further includes: prefetch control logic and an adaptive prefetch control module;
the prefetching control logic is connected with the AHB bus interface module and is used for sending information to the AHB bus interface module or receiving information sent by the AHB bus interface module;
the self-adaptive prefetch control module is used for calculating the minimum difference value between the request address and the address corresponding to the instruction in the buffer module, and outputting the updated prefetch line number based on the minimum difference value and the current prefetch line number of the self-adaptive prefetch control module.
Further, the adaptive prefetch control module outputs the prefetch line number in a state machine mode, specifically:
when the minimum difference value of the address is greater than 4, the updated prefetch line number is kept unchanged;
when the minimum difference value of the address is less than or equal to 8, the updated prefetch line number is 4 lines, and when the minimum difference value of the address is more than 8, the updated prefetch line number is 1 line;
the current prefetch line number is 4 lines, and the updated prefetch line number is converted into 2 lines.
Further, the number of prefetch lines of the adaptive prefetch control module is 1 line, 2 lines and 4 lines.
Further, the minimum difference between the calculated request address and the address corresponding to the instruction in the buffer module is specifically: and calculating the minimum difference between the tag part in the request address and the tag part in the address corresponding to the instruction in the buffer module.
Furthermore, the acceleration system further comprises an eFlash controller, wherein the eFlash controller receives a request address input by the prefetch control module and the prefetch line number to generate a corresponding working time sequence, the corresponding working time sequence is input to the eFlash memory, the eFlash memory waits for a read instruction, the instruction is returned to the eFlash controller, and the eFlash controller sends the corresponding instruction to the prefetch control logic or the cache module.
Further, when the tag part in a certain instruction address in the buffer module is matched with the tag part in the request address, the buffer module sends hit information to the AHB bus interface module through the prefetch control logic, namely 1, when the tag parts in all the instruction addresses in the buffer module are not matched with the tag part in the request address, the buffer module sends miss information to the AHB bus interface module through the prefetch control logic, namely 0;
when the tag part in a certain instruction address in the cache module is matched with the tag part in the request address, the cache module sends hit information to the AHB bus interface module, namely 1, and when the tag parts in all instruction addresses in the cache module are not matched with the tag part in the request address, the cache module sends miss information to the AHB bus interface module, namely 0.
Further, the AHB bus interface module judges whether to send an instruction missing signal to the prefetch control logic according to hit or miss signals sent by the buffer module and the cache module;
when the buffer module sends 1 to the AHB bus interface module, and the cache module sends 0 to the buffer module, the AHB bus interface module reads an instruction corresponding to the request address in the buffer module;
when the buffer module sends 0 to the AHB bus interface module, and the cache module sends 1 to the buffer module, the AHB bus interface module reads an instruction corresponding to the request address in the cache module;
when the buffer module sends 0 to the AHB bus interface module, the cache module sends 0 to the buffer module and the AHB bus interface module, and the AHB bus interface module sends an instruction missing signal to the prefetch control logic.
Further, the buffer module includes 4 rows of memory cells, each row of 128bits, and follows the first-in first-out principle.
Further, the bit width of the eFflash memory is 128bits, that is, each row of eFflash contains 4 32-bit instructions.
Compared with the prior art, the application has at least one of the following beneficial effects:
1. the self-adaptive prefetch control module is used for dynamically detecting the spatial locality of the program, dynamically adjusting the prefetch line number, improving the instruction hit probability, reducing the invalid prefetch times and reducing the power consumption;
2. the application adopts the cache module, is a cache 2-way group connection structure and is used for processing jump instructions, when the address accessed by the CPU is lost, the lost instruction line is read and then returned to the CPU and simultaneously stored in the cache module, and when the CPU jumps to the address next time, the instruction of the corresponding address is directly extracted from the cache module without waiting time, thereby reducing the running time.
In the application, the technical schemes can be mutually combined to realize more preferable combination schemes. Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the application, like reference numerals being used to designate like parts throughout the drawings;
FIG. 1 is a schematic diagram of a read acceleration system;
FIG. 2 is a state transition diagram of an adaptive prefetch control module.
Detailed Description
The following detailed description of preferred embodiments of the application is made in connection with the accompanying drawings, which form a part hereof, and together with the description of the embodiments of the application, are used to explain the principles of the application and are not intended to limit the scope of the application.
In one embodiment of the present application, a low power eFlash read acceleration system is disclosed, as shown in FIG. 1. The acceleration system includes: the system comprises an AHB bus interface module, a prefetch control module, a cache module and an eFlash memory;
the AHB bus interface module is used for receiving a request address of an external CPU and sending the request address to the prefetch control module and the cache module;
the prefetch control module comprises a buffer module, wherein the buffer module and the cache module judge whether the respective stored instructions have instructions matched with the request address according to the request address, and if so, the instructions are transmitted to the CPU through the AHB bus interface module;
when the instructions in the buffer module and the Cache module are not matched with the request address, the AHB bus interface module sends an instruction missing signal to the prefetch control module, the prefetch control module outputs the updated prefetch line number according to the request address and the instruction corresponding to the instruction in the buffer module, acquires the instruction of the request address and the subsequent prefetch line number from the eFlash memory according to the prefetch line number, sends the instruction corresponding to the request address to the CPU through the AHB interface module, stores the instruction in the Cache module, and stores the instruction of the prefetch line number after the request address to the buffer module.
Specifically, comparing the tag part of each instruction corresponding address in the buffer module and the cache module with the tag part in the CPU request address, and when the tag part of a certain instruction corresponding address in the buffer module or the cache module is equal to the tag part in the CPU request address, indicating that the instruction in the buffer module or the cache module is matched with the instruction in the CPU request address, namely hit;
when the tag part in the corresponding addresses of all instructions in the buffer module or the cache module is not equal to the tag part in the CPU request address, the instruction in the buffer module and the instruction in the cache module are not matched with the instruction in the CPU request address, namely, the miss is indicated.
Specifically, when the instruction hits, the AHB bus interface module directly reads the instruction to the CPU, and the current CPU requests the instruction reading process to end.
Specifically, the cache module adopts a 2-way set association structure, the replacement strategy adopts a least recently used strategy (LRU), the cache module is mainly used for caching jump instructions, when a request address accessed by an external CPU is missed, the missed instruction is read from the eFlash memory and then sequentially returned to the external CPU through the prefetch control module and the AHB bus interface module, the instruction is stored in the cache module, and when the external CPU accesses the address next time, the instruction of the corresponding address is directly extracted from the cache module without waiting time.
Further, the prefetch control module further includes: prefetch control logic and an adaptive prefetch control module;
the prefetching control logic is connected with the AHB bus interface module and is used for sending information to the AHB bus interface module or receiving information sent by the AHB bus interface module;
the self-adaptive prefetch control module is used for calculating the minimum difference value between the request address and the address corresponding to the instruction in the buffer module, and outputting the updated prefetch line number based on the minimum difference value and the current prefetch line number of the self-adaptive prefetch control module.
Specifically, when the request address is not hit, the prefetch control module pauses instruction prefetching and directly fetches the instruction from the eFlash memory.
Specifically, the information sent by the prefetch control logic to the AHB bus interface module includes: buffer module instruction matching information 1, buffer module instruction mismatch information 0, cache module instruction matching information 1, and cache module instruction mismatch information 0;
the prefetch control logic receiving information sent by the AHB bus interface module comprises: instruction miss signal.
Further, the adaptive prefetch control module outputs the prefetch line number in a state machine mode, specifically:
when the minimum difference value of the address is greater than 4, the updated prefetch line number is kept unchanged;
when the minimum difference value of the address is less than or equal to 8, the updated prefetch line number is 4 lines, and when the minimum difference value of the address is more than 8, the updated prefetch line number is 1 line;
the current prefetch line number is 4 lines, and the updated prefetch line number is converted into 2 lines.
Specifically, when the current prefetch line number is 1 line, the prefetch line number is updated to 2 lines when instruction deletion occurs and the minimum address difference value is less than or equal to 4, at the moment, the program space is relatively good, the prefetch line number is increased, 2 lines are better, when the instruction deletion occurs and the minimum address difference value is greater than 4, the current program space is relatively poor, the prefetch line number is not excessive, so that resources are not wasted, and the updated prefetch line number is kept unchanged or is 1 line;
when the current prefetching line number is 2 lines, updating the prefetching line number into 4 lines when instruction deletion occurs and the minimum address difference value is less than or equal to 8, wherein the program space is better, the prefetching line number is increased, 4 lines are better, when the instruction deletion occurs and the minimum address difference value is greater than 8, updating the prefetching line number into 1 line, wherein the program space is worse, the prefetching line number is reduced, 1 line is better, and the power consumption waste caused when the prefetching line number encounters a jump instruction is reduced;
when the current prefetch line number is 4 lines, the prefetch line number is updated to be 2 lines as long as instruction deletion occurs, and the power consumption waste caused when the prefetch line number encounters a jump instruction is reduced.
Specifically, the prefetch control module prefetches instructions stored in the buffer module, the better the program space, the larger the prefetch line number, the higher the performance of the external CPU instruction fetch, but the larger prefetch line number can cause the waste of power consumption when encountering a jump instruction.
Further, the number of prefetch lines of the adaptive prefetch control module is 1 line, 2 lines or 4 lines.
Specifically, the number of prefetch lines of the power-on default adaptive prefetch control module is 2 lines.
Further, the bit width of the eFflash memory is 128bits, that is, each row of eFflash contains 4 32-bit instructions.
Specifically, the prefetch 2 line instruction includes 8 32-bit instructions.
Further, the minimum difference between the calculated request address and the address corresponding to the instruction in the buffer module is specifically: and calculating the minimum difference between the tag part in the request address and the tag part in the address corresponding to the instruction in the buffer module.
Furthermore, the acceleration system further comprises an eFlash controller, wherein the eFlash controller receives a request address input by the prefetch control module and the prefetch line number to generate a corresponding working time sequence, the corresponding working time sequence is input to the eFlash memory, the eFlash memory waits for a read instruction, the instruction is returned to the eFlash controller, and the eFlash controller sends the corresponding instruction to the prefetch control logic or the cache module.
Specifically, the acceleration system further comprises an eFlash control register, wherein the eFlash control register receives a request sent by an external CPU through an AHB bus interface and is used for configuring the working state and power of the eFlash controller, and the eFlash controller receives external read, write and erase requests.
Further, when the tag part in a certain instruction address in the buffer module is matched with the tag part in the request address, the buffer module sends hit information to the AHB bus interface module through the prefetch control logic, namely 1, when the tag parts in all the instruction addresses in the buffer module are not matched with the tag part in the request address, the buffer module sends miss information to the AHB bus interface module through the prefetch control logic, namely 0;
when the tag part in a certain instruction address in the cache module is matched with the tag part in the request address, the cache module sends hit information to the AHB bus interface module, namely 1, and when the tag parts in all instruction addresses in the cache module are not matched with the tag part in the request address, the cache module sends miss information to the AHB bus interface module, namely 0.
Further, the AHB bus interface module judges whether to send an instruction missing signal to the prefetch control logic according to hit or miss signals sent by the buffer module and the cache module;
when the buffer module sends 1 to the AHB bus interface module, and the cache module sends 0 to the buffer module, the AHB bus interface module reads an instruction corresponding to the request address in the buffer module;
when the buffer module sends 0 to the AHB bus interface module, and the cache module sends 1 to the buffer module, the AHB bus interface module reads an instruction corresponding to the request address in the cache module;
when the buffer module sends 0 to the AHB bus interface module, the cache module sends 0 to the buffer module and the AHB bus interface module, and the AHB bus interface module sends an instruction missing signal to the prefetch control logic.
Further, the buffer module includes 4 rows of memory cells, each row of 128bits, and follows the first-in first-out principle.
The prefetch control logic of the prefetch control module may prefetch instructions based on the output of the adaptive prefetch control module, e.g., prefetch 2 lines when the adaptive prefetch control module output is 2. The traditional structural working mode is fixed prefetching, which can be understood as that the output of the prefetching control module is always 2, and the possible values of the design are 1, 2 and 4. The self-adaptive prefetching control module outputs the updated prefetching line number according to the minimum difference value and the current prefetching line number by calculating the minimum difference value between the request address and the corresponding address of the instruction in the buffer, and can adjust the prefetching line number in real time according to the spatial locality of the program instruction, thereby ensuring the hit probability of the request address and further improving the reading speed.
Compared with the prior art, the reading acceleration system of the low-power eFlash provided by the embodiment dynamically detects the spatial locality of the program through the self-adaptive prefetch control module, dynamically adjusts the prefetch line number, improves the instruction hit probability, reduces the ineffective prefetch times, and reduces the power consumption; the application adopts the cache module, is a cache 2-way group connection structure and is used for processing jump instructions, when the address accessed by the CPU is lost, the lost instruction line is read and then returned to the CPU and simultaneously stored in the cache module, and when the CPU jumps to the address next time, the instruction of the corresponding address is directly extracted from the cache module without waiting time, thereby reducing the running time.
Those skilled in the art will appreciate that all or part of the flow of the methods of the embodiments described above may be accomplished by way of a computer program to instruct associated hardware, where the program may be stored on a computer readable storage medium. Wherein the computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory, etc.
The present application is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application.

Claims (10)

1. A low power eFlash read acceleration system, the acceleration system comprising: the system comprises an AHB bus interface module, a prefetch control module, a cache module and an eFlash memory;
the AHB bus interface module is used for receiving a request address of an external CPU and sending the request address to the prefetch control module and the cache module;
the prefetch control module comprises a buffer module, wherein the buffer module and the cache module judge whether the respective stored instructions have instructions matched with the request address according to the request address, and if so, the instructions are transmitted to the CPU through the AHB bus interface module;
when the instructions in the buffer module and the Cache module are not matched with the request address, the AHB bus interface module sends an instruction missing signal to the prefetch control module, the prefetch control module outputs the updated prefetch line number according to the request address and the instruction corresponding to the instruction in the buffer module, acquires the instruction of the request address and the subsequent prefetch line number from the eFlash memory according to the prefetch line number, sends the instruction corresponding to the request address to the CPU through the AHB interface module, stores the instruction in the Cache module, and stores the instruction of the prefetch line number after the request address to the buffer module.
2. The low power eFlash read acceleration system of claim 1 in which the prefetch control module further comprises: prefetch control logic and an adaptive prefetch control module;
the prefetching control logic is connected with the AHB bus interface module and is used for sending information to the AHB bus interface module or receiving information sent by the AHB bus interface module;
the self-adaptive prefetch control module is used for calculating the minimum difference value between the request address and the address corresponding to the instruction in the buffer module, and outputting the updated prefetch line number based on the minimum difference value and the current prefetch line number of the self-adaptive prefetch control module.
3. The system of claim 2, wherein the adaptive prefetch control module outputs the number of prefetch lines by using a state machine, and the method is specifically as follows:
when the minimum difference value of the address is greater than 4, the updated prefetch line number is kept unchanged;
when the minimum difference value of the address is less than or equal to 8, the updated prefetch line number is 4 lines, and when the minimum difference value of the address is more than 8, the updated prefetch line number is 1 line;
the current prefetch line number is 4 lines, and the updated prefetch line number is converted into 2 lines.
4. The system of claim 3, wherein the adaptive prefetch control module has a prefetch line count of 1 line, 2 lines, and 4 lines.
5. The system of claim 4, wherein the minimum difference between the calculated request address and the address corresponding to the instruction in the buffer module is specifically: and calculating the minimum difference between the tag part in the request address and the tag part in the address corresponding to the instruction in the buffer module.
6. The system of claim 5 further comprising an eFlash controller, wherein the eFlash controller receives the request address and the number of prefetch lines from the prefetch control module, generates a corresponding operation time sequence, and inputs the operation time sequence to the eFlash memory, wherein the eFlash memory waits for a read command, returns the command to the eFlash controller, and sends the corresponding command to the prefetch control logic or the cache module.
7. The system for accelerating the read of a low power eFlash of claim 6, wherein,
when the tag part in a certain instruction address in the buffer module is matched with the tag part in the request address, the buffer module sends hit information to the AHB bus interface module through the prefetch control logic, namely 1, when the tag part in all the instruction addresses in the buffer module is not matched with the tag part in the request address, the buffer module sends miss information to the AHB bus interface module through the prefetch control logic, namely 0;
when the tag part in a certain instruction address in the cache module is matched with the tag part in the request address, the cache module sends hit information to the AHB bus interface module, namely 1, and when the tag parts in all instruction addresses in the cache module are not matched with the tag part in the request address, the cache module sends miss information to the AHB bus interface module, namely 0.
8. The system of claim 7 wherein the AHB bus interface module determines whether to send an instruction miss signal to the prefetch control logic based on hit or miss signals sent by the buffer module and the cache module;
when the buffer module sends 1 to the AHB bus interface module, and the cache module sends 0 to the buffer module, the AHB bus interface module reads an instruction corresponding to the request address in the buffer module;
when the buffer module sends 0 to the AHB bus interface module, and the cache module sends 1 to the buffer module, the AHB bus interface module reads an instruction corresponding to the request address in the cache module;
when the buffer module sends 0 to the AHB bus interface module, the cache module sends 0 to the buffer module and the AHB bus interface module, and the AHB bus interface module sends an instruction missing signal to the prefetch control logic.
9. The system of claim 8, wherein the buffer module comprises 4 rows of memory cells, each row being 128bits, following a first-in-first-out principle.
10. The system of claim 9 wherein the eFflash memory has a bit width of 128bits, i.e., each row of eFflash contains 4 32-bit instructions.
CN202310601810.1A 2023-05-25 2023-05-25 Low-power eFlash reading acceleration system Pending CN116627335A (en)

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