CN112117376A - Superconducting nanowire structure and preparation method thereof - Google Patents
Superconducting nanowire structure and preparation method thereof Download PDFInfo
- Publication number
- CN112117376A CN112117376A CN202011019119.5A CN202011019119A CN112117376A CN 112117376 A CN112117376 A CN 112117376A CN 202011019119 A CN202011019119 A CN 202011019119A CN 112117376 A CN112117376 A CN 112117376A
- Authority
- CN
- China
- Prior art keywords
- based oxide
- superconducting nanowire
- sacrificial layer
- nanowire structure
- superconducting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002070 nanowire Substances 0.000 title claims abstract description 88
- 238000002360 preparation method Methods 0.000 title abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000005516 engineering process Methods 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 238000004140 cleaning Methods 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 10
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- SXGROPYLQJYUST-UHFFFAOYSA-N iron(2+);selenium(2-) Chemical compound [Fe+2].[Se-2] SXGROPYLQJYUST-UHFFFAOYSA-N 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 229910052688 Gadolinium Inorganic materials 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 6
- PZKRHHZKOQZHIO-UHFFFAOYSA-N [B].[B].[Mg] Chemical compound [B].[B].[Mg] PZKRHHZKOQZHIO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052790 beryllium Inorganic materials 0.000 claims description 6
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims description 6
- UIWYJDYFSGRHKR-UHFFFAOYSA-N gadolinium atom Chemical compound [Gd] UIWYJDYFSGRHKR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052735 hafnium Inorganic materials 0.000 claims description 6
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052746 lanthanum Inorganic materials 0.000 claims description 6
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 6
- 239000010955 niobium Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052727 yttrium Inorganic materials 0.000 claims description 6
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052726 zirconium Inorganic materials 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 230000001939 inductive effect Effects 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000009279 wet oxidation reaction Methods 0.000 claims description 4
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 3
- 239000000395 magnesium oxide Substances 0.000 claims description 3
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 9
- 238000000407 epitaxy Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/80—Constructional details
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0128—Manufacture or treatment of composite superconductor filaments
Abstract
The invention discloses a superconducting nanowire structure and a preparation method thereof, wherein the invention provides a preparation method of the superconducting nanowire structure by using a bottom-up mode and a side wall technology, and the preparation method comprises the following steps: depositing a sacrificial layer on a substrate, removing part of the sacrificial layer, and forming a plurality of remaining partial sacrificial layers with preset intervals; depositing an isolation dielectric layer on the surface of each remaining part of the sacrificial layer and the surface of the substrate with the removed part of the sacrificial layer, removing part of the isolation dielectric layer, and forming a plurality of remaining part isolation dielectric layers with preset intervals; removing the plurality of remaining portions of the sacrificial layer by an etching method; and cleaning the surface of the substrate, and extending the superconducting nanowire on the surface of the substrate to obtain the superconducting nanowire structure.
Description
Technical Field
The invention relates to the technical field of semiconductor integration, in particular to a superconducting nanowire structure and a preparation method thereof.
Background
The superconducting nanowire single-photon detector is one type of single-photon detector, has the advantages of rapidness, accuracy, high efficiency, low dark count, corresponding spectral width and the like, and has important application prospect and research value in the field of single-photon detection.
The traditional superconducting nanowire single photon detector adopts a top-down method, and realizes the superconducting nanowire by epitaxial deposition of a superconducting material, electron beam exposure and etching, wherein the superconducting nanowire is damaged by etching, and the electron beam exposure also has the problems of proximity effect and the like. How to realize a superconducting nanowire structure with high quality and high duty ratio is a problem which must be considered.
Disclosure of Invention
In view of this, in order to realize a high-quality and high-duty-ratio superconducting nanowire structure, the invention provides a superconducting nanowire structure and a preparation method thereof, so that the realized high-quality and high-duty-ratio superconducting nanowire structure can be directly used for preparing a high-performance superconducting single photon detector, and has important application value in the aspect of the high-performance superconducting single photon detector.
In order to achieve the above object, in one aspect, the present invention provides a method for preparing a superconducting nanowire structure by using a sidewall technology in a bottom-up manner, including: depositing a sacrificial layer on a substrate, removing part of the sacrificial layer, and forming a plurality of remaining partial sacrificial layers with preset intervals; depositing an isolation dielectric layer on the surface of each remaining part of the sacrificial layer and the surface of the substrate with the removed part of the sacrificial layer, removing part of the isolation dielectric layer, and forming a plurality of remaining part isolation dielectric layers with preset intervals; removing the plurality of remaining portions of the sacrificial layer by an etching method; and cleaning the surface of the substrate, and extending the superconducting nanowire on the surface of the substrate to obtain the superconducting nanowire structure.
According to an embodiment of the invention, wherein the substrate material comprises one of: single crystals of strontium titanate, silicon or magnesium oxide.
According to the embodiment of the invention, the superconducting nanowires are epitaxially grown on the surface of the substrate uncovered by the isolation medium layer by means of molecular beam epitaxy, and the superconducting nanowires are separated by the isolation medium layer.
According to the embodiment of the invention, the deposition method of the sacrificial layer and the isolation medium layer comprises at least one of the following steps: atomic layer deposition, plasma enhanced chemical vapor deposition, magnetron sputtering, molecular beam epitaxy, metal organic chemical vapor deposition, dry oxidation and wet oxidation; the etching method of the sacrificial layer and the isolation medium layer comprises at least one of the following steps: reactive ion etching technology and inductive coupling plasma etching technology.
According to an embodiment of the invention, wherein the material of the sacrificial layer comprises at least one of: silicon-based oxide, aluminum-based oxide, zirconium-based oxide, hafnium-based oxide, gadolinium-based oxide, gallium-based oxide, lanthanum-based oxide, tantalum-based oxide, beryllium-based oxide, titanium-based oxide, yttrium-based oxide, silicon nitride; the material of the sacrificial layer has corrosion selectivity; the thickness of the sacrificial layer is between 1nm and 300nm, and the width of the sacrificial layer is between 1nm and 200 nm.
According to an embodiment of the present invention, wherein the material of the isolation dielectric layer comprises at least one of: silicon-based oxide, aluminum-based oxide, zirconium-based oxide, hafnium-based oxide, gadolinium-based oxide, gallium-based oxide, lanthanum-based oxide, tantalum-based oxide, beryllium-based oxide, titanium-based oxide, yttrium-based oxide, silicon nitride; the thickness of the isolation medium layer is between 1nm and 300nm, and the width of the isolation medium layer is between 1nm and 200 nm.
According to an embodiment of the invention, wherein the material of the superconducting nanowires comprises at least one of: niobium nitride (NbN), niobium (Nb), ferrous selenide (FeSe), tantalum nitride (TAN), magnesium boride (MgB)2) (ii) a The thickness of the superconductive nanometer line is between 1nm and 30nm, and the width of the superconductive nanometer line is between 1nm and 200 nm.
According to the embodiment of the invention, the etching method comprises wet etching, and the plurality of parts of the sacrificial layer are selectively removed by using the wet etching method.
In another aspect, the present invention also provides a superconducting nanowire structure manufactured by any one of the above methods of manufacturing a superconducting nanowire structure.
According to an embodiment of the present invention, a superconducting nanowire structure includes: substrate, superconductive nano wire, isolation dielectric layer.
According to the technical scheme, the superconducting nanowire structure prepared by the invention has the following beneficial effects:
(1) according to the invention, the superconducting nanowires are selectively epitaxial in a bottom-up manner, so that photoresist contamination and etching damage introduced in the etching process are avoided;
(2) the distance between the prepared superconducting nanowires is determined by the width of the isolation medium, and the advantages of the side wall technology are utilized, so that the distance is very small, the distance limit of electron beam lithography is avoided, and the duty ratio is favorably improved;
(3) the superconducting nanowire prepared by the method does not need to etch a strontium titanate substrate, can keep an atomic-level flatness surface, and is beneficial to the epitaxy of superconducting materials.
Drawings
FIG. 1 schematically illustrates a flow diagram of a method of fabricating a superconducting nanowire structure according to an embodiment of the invention;
FIG. 2 schematically shows a structural diagram after forming a remaining portion of a sacrificial layer on a substrate, in accordance with an embodiment of the present invention;
FIG. 3 schematically shows a schematic structure diagram after forming a remaining portion of an isolation dielectric layer according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a structure after selectively removing a portion of a sacrificial layer according to an embodiment of the invention;
fig. 5 schematically illustrates a structural view of a superconducting nanowire structure according to an embodiment of the present invention.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
On one hand, the invention aims to prepare the superconducting nanowire from bottom to top, adopts the side wall technology and adopts the isolation medium to perform selective epitaxy and isolation of the superconducting nanowire, and provides a superconducting nanowire structure and a preparation method thereof. The superconducting nanowire structure can be directly used for preparing a high-performance superconducting single-photon detector and has important application value in the aspect of the high-performance superconducting single-photon detector.
Fig. 1 schematically shows a flow diagram of a method of fabricating a superconducting nanowire structure according to an embodiment of the present invention.
As shown in fig. 1, the method includes operations S101 to S104.
In operation S101, a sacrificial layer is deposited on a substrate, and a portion of the sacrificial layer is removed to form a plurality of remaining partial sacrificial layers having a predetermined pitch.
According to embodiments of the present invention, the substrate material used by the present invention may comprise at least one of: single crystals of strontium titanate, silicon or magnesium oxide. In a specific embodiment of the present invention, the substrate material used is strontium titanate.
According to an embodiment of the present invention, the deposition method of the sacrificial layer may include at least one of: atomic layer deposition, plasma enhanced chemical vapor deposition, magnetron sputtering, molecular beam epitaxy, metal organic chemical vapor deposition, dry oxidation and wet oxidation. In an embodiment of the invention, the deposition method used is plasma enhanced chemical vapor deposition.
According to the embodiment of the invention, the material of the sacrificial layer can be one or more oxide stacks of silicon-based, aluminum-based, zirconium-based, hafnium-based, gadolinium-based, gallium-based, lanthanum-based, tantalum-based, beryllium-based, titanium-based and yttrium-based oxides, the material of the sacrificial layer can also be silicon nitride, and the material of the sacrificial layer has corrosion selectivity. In an embodiment of the present invention, the material of the sacrificial layer is silicon nitride.
According to the embodiment of the invention, the removing of the part of the sacrificial layer is realized by adopting a dry etching method, and the dry etching method can comprise at least one of the following steps: reactive ion etching technology and inductive coupling plasma etching technology. In an embodiment of the present invention, an etching method used for removing a portion of the sacrificial layer is an inductively coupled plasma etching technique.
According to the embodiment of the invention, part of the sacrificial layer is removed by adopting an etching method, the unetched residual sacrificial layer is left on the substrate, and the unetched residual sacrificial layer forms a plurality of residual sacrificial layers with preset intervals, so that support is provided for forming the isolation dielectric layer by adopting a side wall technology in the following step S102.
According to the embodiment of the invention, the plurality of remaining partial sacrificial layers with the preset spacing are respectively between 1nm and 300nm in thickness and between 1nm and 200nm in width.
According to an embodiment of the present invention, the predetermined distance is a distance between two portions of the sacrificial layer that are not etched.
After forming the remaining portion of the sacrificial layer on the substrate, the structure of fig. 2 is formed, according to an embodiment of the present invention.
Fig. 2 schematically shows a structural diagram after a remaining portion of a sacrificial layer is formed on a substrate according to an embodiment of the present invention.
As shown in fig. 2, in an embodiment of the present invention, a sacrificial layer of silicon nitride is deposited on a strontium titanate substrate 1 by using a plasma enhanced chemical vapor deposition method, a portion of the sacrificial layer of silicon nitride is etched by using an inductively coupled plasma etching technique, and remaining portions of the sacrificial layer of silicon nitride 2, which are not etched and have a predetermined pitch, are left on the strontium titanate substrate 1, and each of the remaining portions of the sacrificial layer of silicon nitride 2 has a thickness of 40nm and a width of 10 nm.
In operation S102, an isolation dielectric layer is deposited on the surface of each remaining portion of the sacrificial layer and the substrate surface from which the remaining portion of the sacrificial layer is removed, and a plurality of remaining portion isolation dielectric layers having a predetermined pitch are formed by removing a portion of the isolation dielectric layer.
According to the embodiment of the invention, the remaining isolation dielectric layers with the preset spacing are formed and positioned at two sides of the remaining sacrificial layer, and the side walls are formed and used for realizing the extension and isolation of the superconducting nanowire in the invention.
According to the embodiment of the invention, the width of the rest of the isolation medium layer determines the spacing of the superconducting nanowires in the invention.
According to the embodiment of the invention, the deposition method of the isolation dielectric layer comprises at least one of the following steps: atomic layer deposition, plasma enhanced chemical vapor deposition, magnetron sputtering, molecular beam epitaxy, metal organic chemical vapor deposition, dry oxidation and wet oxidation.
According to the embodiment of the invention, the material of the isolation dielectric layer may be one of silicon-based, aluminum-based, zirconium-based, hafnium-based, gadolinium-based, gallium-based, lanthanum-based, tantalum-based, beryllium-based, titanium-based, yttrium-based oxides or a stack of multiple oxides thereof, and the material of the isolation dielectric layer may also be silicon nitride.
According to the embodiment of the invention, the method for removing part of the isolation dielectric layer is dry etching, and may include at least one of the following steps: reactive ion etching technology and inductive coupling plasma etching technology.
According to the embodiment of the invention, the thickness of the residual isolation dielectric layer is between 1nm and 300nm, and the width of the residual isolation dielectric layer is between 1nm and 200 nm.
After depositing the isolation dielectric layer, the structure of fig. 3 is formed according to an embodiment of the present invention.
Fig. 3 schematically shows a structural diagram after forming the remaining portion of the isolation dielectric layer according to an embodiment of the present invention.
As shown in fig. 3, an isolation dielectric layer is deposited on the remaining sacrificial layer 2 and the substrate surface covered by the removed portion of the sacrificial layer by plasma enhanced chemical vapor deposition, an unnecessary isolation dielectric layer is etched by an inductively coupled plasma etching technique, a plurality of remaining isolation dielectric layers 3 having the same thickness as the remaining sacrificial layer 2 are formed, the remaining isolation dielectric layers 3 are located at two sides of the remaining sacrificial layer, side walls are formed, and the thickness of each remaining isolation dielectric layer is 40 nm.
In operation S103, the plurality of remaining portions of the sacrificial layer are removed by an etching method.
According to the embodiment of the invention, the plurality of remaining portions of the sacrificial layer are selectively removed by a wet etching method.
After removing the remaining portion of the sacrificial layer, the structure of fig. 4 is formed, according to an embodiment of the present invention.
Fig. 4 schematically shows a structure diagram after selectively removing a part of the sacrificial layer according to an embodiment of the present invention.
After removing the remaining part of the sacrificial layer, a structure consisting of a strontium titanate substrate 1 and a plurality of remaining part of the isolation dielectric layer 3 is formed, as shown in fig. 4. The remaining isolation medium layers 3 are used for controlling the extension and isolation of the superconducting nanowires, the distance between the remaining isolation medium layers 3 is used for selecting the extension superconducting nanowires, and the width of each remaining isolation medium layer 3 determines the distance between two superconducting nanowires.
In operation S104, the surface of the substrate is cleaned, and the superconducting nanowire is extended on the surface of the substrate to obtain a superconducting nanowire structure.
According to the embodiment of the invention, after the surface of the substrate is cleaned, the epitaxial superconducting nanowire is selected by adopting a molecular beam epitaxy mode.
According to an embodiment of the present invention, selective epitaxy refers to an epitaxial process in which an epitaxial layer is grown on a specific region of a substrate surface, while other regions do not grow the epitaxial layer.
According to the embodiment of the invention, the selective epitaxy is realized by adopting a molecular beam epitaxy mode, namely, the epitaxial superconducting nanowire is selected on the surface of the substrate uncovered by the rest part of the isolation medium layer.
According to an embodiment of the present invention, the epitaxially grown superconducting nanowires and the remaining portion of the isolation dielectric layer are stacked on the substrate, and the superconducting nanowires are separated by each remaining portion of the isolation dielectric layer. Furthermore, the superconducting nanowire is epitaxially grown on the surface of the substrate between the two remaining portions of the isolation dielectric layer.
According to an embodiment of the present invention, the material of the superconducting nanowire includes niobium nitride (NbN), niobium (Nb), ferrous selenide (FeSe), tantalum nitride (TaN), magnesium boride (MgB)2) One or more single crystal materials of (a).
According to an embodiment of the invention, the superconducting nanowires have a thickness between 1nm and 30nm and a width between 1nm and 200 nm.
According to an embodiment of the present invention, a molecular beam epitaxy superconducting nanowire is used to form the structure of fig. 5.
Fig. 5 schematically illustrates a structural view of a superconducting nanowire structure according to an embodiment of the present invention.
As shown in fig. 5, in the embodiment of the present invention, a molecular beam epitaxy method is adopted to select the epitaxial superconducting nanowire material as ferrous selenide (FeSe), the thickness is 15nm, and the width is 100 nm.
According to the embodiment of the invention, the superconducting nanowires are prepared from the bottom to the top by providing the preparation method of the superconducting nanowire structure, the side wall technology is adopted, and the isolation medium is adopted for selective epitaxy and isolation of the superconducting nanowires, so that the problems of damage to the superconducting nanowires in the traditional preparation process of exposing and etching an electronic book and the like by adopting a top-down method and the proximity effect in electron beam exposure are solved, the spacing of the superconducting nanowires is determined by the width of the isolation medium, the spacing can be very small by utilizing the advantages of the side wall technology, the spacing limit of electron beam lithography is avoided, and the duty ratio is favorably improved; the strontium titanate substrate does not need to be etched, the atomic-level flatness surface can be reserved, the epitaxy of a superconducting material is facilitated, and therefore the superconducting nanowire structure with high quality and high duty ratio is achieved.
In another aspect of the present invention, a superconducting nanowire structure is provided, which is manufactured by the above method for manufacturing a superconducting nanowire structure. A schematic diagram of a superconducting nanowire structure is shown in fig. 5.
Fig. 5 schematically illustrates a structural view of a superconducting nanowire structure according to an embodiment of the present invention.
In a specific embodiment of the present invention, as shown in fig. 5, the superconducting nanowire structure comprises a strontium titanate substrate 1, a remaining portion of an isolation medium layer 3, and a superconducting nanowire 4.
For the specific description of each component in the superconducting nanowire structure, reference may be made to the description of each step of the above-mentioned method for preparing the superconducting nanowire structure, and details are not repeated here.
According to the embodiment of the invention, the superconducting nanowire structure prepared by the preparation method of the superconducting nanowire structure can also be directly used for preparing a high-performance superconducting single-photon detector, and has important application value in the aspect of the high-performance superconducting single-photon detector.
The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, and it should be understood that the above embodiments are only examples of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method of preparing a superconducting nanowire structure, comprising:
depositing a sacrificial layer on a substrate, removing part of the sacrificial layer, and forming a plurality of remaining partial sacrificial layers with preset intervals;
depositing an isolation dielectric layer on the surface of each remaining part of the sacrificial layer and the surface of the substrate with the removed part of the sacrificial layer, removing part of the isolation dielectric layer, and forming a plurality of remaining part isolation dielectric layers with preset intervals;
removing a plurality of the remaining portions of the sacrificial layer by an etching method;
and cleaning the surface of the substrate, and extending the superconducting nanowire on the surface of the substrate to obtain the superconducting nanowire structure.
2. The method of fabricating a superconducting nanowire structure of claim 1, wherein:
the substrate material comprises one of: single crystals of strontium titanate, silicon or magnesium oxide.
3. The method of fabricating a superconducting nanowire structure of claim 1, wherein:
and extending the superconducting nanowires on the surface of the substrate which is not covered by the isolation medium layer in a molecular beam epitaxy mode, wherein the superconducting nanowires are separated by the isolation medium layer.
4. The method of fabricating a superconducting nanowire structure of claim 1, wherein:
the deposition method of the sacrificial layer and the isolation medium layer comprises at least one of the following steps: atomic layer deposition, plasma enhanced chemical vapor deposition, magnetron sputtering, molecular beam epitaxy, metal organic chemical vapor deposition, dry oxidation and wet oxidation;
the etching method of the sacrificial layer and the isolation medium layer comprises at least one of the following steps: reactive ion etching technology and inductive coupling plasma etching technology.
5. The method of fabricating a superconducting nanowire structure of claim 1, wherein:
the material of the sacrificial layer comprises at least one of the following: silicon-based oxide, aluminum-based oxide, zirconium-based oxide, hafnium-based oxide, gadolinium-based oxide, gallium-based oxide, lanthanum-based oxide, tantalum-based oxide, beryllium-based oxide, titanium-based oxide, yttrium-based oxide, silicon nitride;
the material of the sacrificial layer has corrosion selectivity;
the thickness of the sacrificial layer is between 1nm and 300nm, and the width of the sacrificial layer is between 1nm and 200 nm.
6. The method of fabricating a superconducting nanowire structure of claim 1, wherein:
the material of the isolation dielectric layer comprises at least one of the following materials: silicon-based oxide, aluminum-based oxide, zirconium-based oxide, hafnium-based oxide, gadolinium-based oxide, gallium-based oxide, lanthanum-based oxide, tantalum-based oxide, beryllium-based oxide, titanium-based oxide, yttrium-based oxide, silicon nitride;
the thickness of the isolation medium layer is between 1nm and 300nm, and the width of the isolation medium layer is between 1nm and 200 nm.
7. The method of fabricating a superconducting nanowire structure of claim 1, wherein:
the material of the superconducting nanowire comprises at least one of the following: niobium nitride (NbN), niobium (Nb), ferrous selenide (FeSe), tantalum nitride (TaN), magnesium boride (MgB)2)；
The thickness of the superconducting nanowire is between 1nm and 30nm, and the width of the superconducting nanowire is between 1nm and 200 nm.
8. The method of fabricating a superconducting nanowire structure of claim 1, wherein:
the etching method comprises wet etching, and the plurality of remaining sacrificial layers are selectively removed by adopting the wet etching method.
9. A superconducting nanowire structure produced by the method of producing a superconducting nanowire structure according to any one of claims 1 to 8.
10. The superconducting nanowire structure of claim 9, comprising: substrate, superconductive nano wire, isolation dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011019119.5A CN112117376A (en) | 2020-09-24 | 2020-09-24 | Superconducting nanowire structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011019119.5A CN112117376A (en) | 2020-09-24 | 2020-09-24 | Superconducting nanowire structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112117376A true CN112117376A (en) | 2020-12-22 |
Family
ID=73800754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011019119.5A Pending CN112117376A (en) | 2020-09-24 | 2020-09-24 | Superconducting nanowire structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112117376A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01283887A (en) * | 1988-05-11 | 1989-11-15 | Nippon Telegr & Teleph Corp <Ntt> | Forming method for pattern of oxide superconductor |
| JPH0244784A (en) * | 1988-08-05 | 1990-02-14 | Canon Inc | Superconductive pattern forming method |
| US5446016A (en) * | 1993-02-15 | 1995-08-29 | Sumitomo Electric Industries, Ltd. | Method for forming a patterned oxide superconductor thin film |
| US5650377A (en) * | 1990-11-30 | 1997-07-22 | International Business Machines Corporation | Selective epitaxial growth of high-TC superconductive material |
| US20100048025A1 (en) * | 2008-08-25 | 2010-02-25 | Seoul National University Industry Foundation | Nanostructures and nanostructure fabrication |
| CN109309004A (en) * | 2017-07-26 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
-
2020
- 2020-09-24 CN CN202011019119.5A patent/CN112117376A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01283887A (en) * | 1988-05-11 | 1989-11-15 | Nippon Telegr & Teleph Corp <Ntt> | Forming method for pattern of oxide superconductor |
| JPH0244784A (en) * | 1988-08-05 | 1990-02-14 | Canon Inc | Superconductive pattern forming method |
| US5650377A (en) * | 1990-11-30 | 1997-07-22 | International Business Machines Corporation | Selective epitaxial growth of high-TC superconductive material |
| US5446016A (en) * | 1993-02-15 | 1995-08-29 | Sumitomo Electric Industries, Ltd. | Method for forming a patterned oxide superconductor thin film |
| US20100048025A1 (en) * | 2008-08-25 | 2010-02-25 | Seoul National University Industry Foundation | Nanostructures and nanostructure fabrication |
| CN109309004A (en) * | 2017-07-26 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110009107B (en) | Method for forming a qubit device | |
| TWI248677B (en) | Method of fabricating an ultra-narrow channel semiconductor device | |
| US9437443B2 (en) | Low-temperature sidewall image transfer process using ALD metals, metal oxides and metal nitrides | |
| JP2009505421A5 (en) | ||
| CN106711194B (en) | A kind of ring grid field effect transistor and preparation method thereof | |
| CN109860035A (en) | The manufacturing method of semiconductor element | |
| Banerjee et al. | Submicron patterning of epitaxial PbZr0. 52Ti0. 48O3 heterostructures | |
| US20150376778A1 (en) | Graphene growth on sidewalls of patterned substrate | |
| US20180261456A1 (en) | Substantially defect-free polysilicon gate arrays | |
| US7514282B2 (en) | Patterned silicon submicron tubes | |
| CN112117376A (en) | Superconducting nanowire structure and preparation method thereof | |
| CN109690786B (en) | Heterojunction tunneling field effect transistor and preparation method thereof | |
| CN112117375A (en) | Superconducting nanowire structure and preparation method thereof | |
| CN107946354A (en) | A kind of SOI FinFETs of anti-integral dose radiation and preparation method thereof | |
| CN110556453B (en) | Ordered Si-based Al1-xGaxControllable epitaxial growth method of N quantum dots | |
| CN103676491A (en) | Method for reducing roughness of photoresist during electron beam lithography | |
| CN109841675A (en) | Vertical nanowire transistor and forming method thereof | |
| JP2010283206A (en) | Method of forming fine pattern of superconductor | |
| CN111223928B (en) | Gate finger gradually-widening GaN FinFET structure and preparation method thereof | |
| CN111682096B (en) | Preparation method of planar superconducting nano bridge junction | |
| CN110620033B (en) | Method for manufacturing metal nanowire or sheet and nanowire or sheet | |
| CN111312819B (en) | Stacked nanowire or sheet gate-all-around device and preparation method thereof | |
| CN114284349A (en) | Graphene transistor and method of manufacturing graphene transistor | |
| WO2014164878A1 (en) | Forming graphene devices using self-limited reactions | |
| CN103676493B (en) | Mixed photolithography method capable of reducing line roughness |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |