CN112115095A - Reconfigurable hardware for Hash algorithm and operation method - Google Patents
Reconfigurable hardware for Hash algorithm and operation method Download PDFInfo
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Abstract
The invention provides a reconfigurable hardware for a hash algorithm and an operation method, wherein the hardware comprises: the system comprises a state controller, an arithmetic unit, a plurality of selectors and a state register, wherein the arithmetic unit is used for executing a Hash calculation process; the operation unit is embedded with a plurality of selectors and is used for selecting input parameters of each operation step in the operation flow; the arithmetic unit outputs the arithmetic result of the Hash arithmetic flow to the state register for storage; the state controller controls the operation states of the arithmetic unit, each selector and the state register. The invention can complete the 'multiplication-addition-shift-multiplication' calculation of the strips and the residual data of the hash algorithm by using only one reconfigurable computing unit, thereby reducing the hardware cost.
Description
Technical Field
The invention belongs to the technical field of Hash calculation, and particularly relates to a reconfigurable hardware machine operation method for a Hash algorithm.
Background
The hash algorithm utilizes input data to perform hash calculation to obtain a hash value, the data and the corresponding hash value are transmitted through a network, the data and the corresponding hash value are recalculated by utilizing the same hash function at a receiving party, and the received hash value and the recalculated hash value are compared, so that the data integrity is judged. The method is widely applied to the fields of information encryption, data verification, load balancing and the like.
The hash algorithm generally uses platform software to perform operations. In the field of embedded mobile computing, a software computing hash algorithm may not meet the requirements of system performance and other indexes. Particularly, the hardware implementation and hardware optimization of the hash algorithm have high practical application requirements for a system with strict requirements on ultra-low power consumption, high throughput rate and data security. When the existing non-reconfigurable hardware executes the hash algorithm operation, 4 strip data computing units and 2 residual data computing units are needed, and 12 multipliers +6 adders +6 shifters are needed in total. Such an implementation would consume more hardware resources and would have a higher hardware cost.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a reconfigurable hardware for hash algorithm to solve the above-mentioned technical problems.
The embodiment of the application provides a reconfigurable hardware for a hash algorithm, which comprises:
the system comprises a state controller, an arithmetic unit, a plurality of selectors and a state register, wherein the arithmetic unit is used for executing a Hash calculation process; the operation unit is embedded with a plurality of selectors and is used for selecting input parameters of each operation step in the operation flow; the arithmetic unit outputs the arithmetic result of the Hash calculation flow to the state register for storage; the state controller controls the operation states of the arithmetic unit, each selector and the state register.
Further, the reconfigurable hardware for the hash algorithm further includes:
the arithmetic unit comprises a first multiplier, an adder, a cycle left shifter and a second multiplier, and the plurality of selectors comprise a first selector, a second selector, a third selector and a fourth selector; the state controller is respectively and electrically connected with the second selector, the third selector, the circulating left shifter, the fourth selector and the state register; the input end of the first selector is respectively connected with the data input end and the state register; the output end of the second selector and the output end of the first selector are both connected with the input end of the multiplier; the output end of the third selector and the output end of the multiplier are both connected with the input end of the adder; the input end of the third selector is respectively connected with the initialization parameter channel and the state register; the output end of the adder is connected with the input end of the circulation left shifter; the output end of the circulation left shifter and the fourth selector are both connected with the input end of the second multiplier; the output end of the second multiplier is respectively connected with the output data end and the state register.
Further, the selectable parameters of the second selector include PRIME32_2 ═ 0x85EBCA77U, PRIME32_3 ═ 0xC2B2AE3DU, PRIME32_5 ═ 0x165667B1U, and constant 1; optional parameters of the fourth selector include PRIME32_1 ═ 0x9E3779B1U, PRIME32_4 ═ 0x27D4EB2FU, and constant 1.
Further, the status register includes four register blocks, and the four register blocks store the operation results of the four data channels respectively.
The invention also provides an operation method of the reconfigurable hardware for the hash algorithm, which comprises the following steps:
the state controller monitors the total byte length of effective input data in real time and selects a calculation mode according to the total byte length, wherein the calculation mode comprises a strip data processing mode, a channel aggregation accumulation mode, a first residual data processing mode and a second residual data processing mode;
the state controller switches output parameters by controlling the selector, and sets the calculation mode to be a selected target calculation mode;
and the state controller sets displacement parameters of the cyclic shifter according to the target calculation mode and controls the operation unit to execute the operation on the input data in the target calculation mode.
Further, the selecting a calculation mode according to the total byte length includes:
if the total byte length is not less than 16 bytes, selecting a stripe data processing mode;
if the total bytes are lower than 16 bytes, selecting a channel aggregation accumulation mode, and judging whether the total bytes are not lower than 4 bytes after the execution of the channel aggregation accumulation mode is finished:
if so, selecting a first residual data processing mode;
if not, selecting a second residual data processing mode.
Further, the method further comprises:
the stripe data processing mode comprises a stripe data processing starting step and a stripe data processing circulating step; the configuration parameters of the stripe data processing starting step comprise input data selected by a first selector, PRIME32_2 selected by a second selector, initialization parameters selected by a third selector, setting of a cyclic shifter to be shifted left by 13 bits, and PRIME32_1 selected by a fourth selector; the configuration parameters of the stripe data processing loop step comprise input data selected by a first selector, PRIME32_2 selected by a second selector, an accumulation feedback loop of a state register selected by a third selector, a loop shifter set to shift left by 13 bits, and PRIME32_1 selected by a fourth selector;
the configuration parameters of the channel convergence accumulation mode comprise a channel convergence loop of a state register selected by a first selector, a constant 1 selected by a second selector, an accumulation feedback loop of the state register selected by a third selector, a constant 1 selected by a fourth selector, and a non-displacement setting of a cyclic shifter;
the first residual data processing mode comprises a first residual data processing starting step and a first residual data processing circulating step, the configuration parameters of the first residual data processing starting step comprise first selector selection input data, second selector selection PRIME32_3, third selector selection initialization parameters, circulation shifter setting to shift left by 17 bits, and fourth selector selection PRIME32_ 4; the configuration parameters of the first remaining data processing loop step include first selector selected input data, second selector selected PRIME32_3, accumulation feedback loop of state register selected by third selector, setting of loop shifter to left shift by 17 bits, fourth selector selected PRIME32_ 4;
the second residual data processing mode comprises a second residual data processing starting step and a second residual data processing circulating step, the configuration parameters of the second residual data processing starting step comprise first selector selected input data, second selector selected PRIME32_5, third selector selected initialization parameters, circulating shifter set to shift left by 11 bits, and fourth selector selected PRIME32_ 1; the configuration parameters for the second remaining data processing cycle step include first selector selected input data, second selector selected PRIME32_5, third selector selected status register accumulation feedback loop, cycle shifter set to shift left 11 bits, fourth selector selected PRIME32_ 1.
Further, the method further comprises:
and the state controller performs validity check on the input data and the output data and outputs a check result.
The beneficial effect of the invention is that,
the reconfigurable hardware and the operation method for the Hash algorithm provided by the invention can quickly construct different overall structures according to the index requirements of different systems on Hash calculation by designing the reconfigurable hardware. The typical 'multiplication-addition-shift-multiplication' calculation in the processing of the strip data and the residual data can be completed by one hardware calculation unit, and an adder in the unit can be further multiplexed to complete four-channel convergence accumulation operation. The hardware unit has enough flexibility and constructability, and is beneficial to performing safe hardware xxHash calculation on a special chip or an FPGA platform by adopting low-cost hardware. The reconstruction is realized by switching operands of multiplication and shift operation in the operation unit by the state controller according to the length of the residual data. The invention can complete the 'multiplication-addition-shift-multiplication' calculation of the strips and the residual data of the hash algorithm by using only one reconfigurable computing unit, thereby reducing the hardware cost.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of reconfigurable hardware for a hash algorithm according to an embodiment of the present application.
Fig. 2 is an exemplary flowchart of a method for operating reconfigurable hardware for a hashing algorithm according to one embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, shall fall within the scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
In the description of the present invention, it is to be understood that the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it should be noted that unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art through specific situations.
The term is defined as:
hash: hash (also called hash function, hash), an algorithm that maps input data of arbitrary length to fixed length;
xxHash: an ultra-fast, non-cryptographic hash algorithm invented and sourced by Yann collelet;
checksum: a checksum for a verified set of data;
and (3) hash value: an output value of the hash algorithm;
prime number: among natural numbers greater than 1, a number that cannot be divisionally divided by other natural numbers except 1 and the number itself;
PRIME 32: the 32-bit-wide PRIME numbers used in xxHash, which are 5 in total, are represented by PRIME32_ 1/2/3/4/5;
LZ 4: the invention and open source of a rapid lossless data compression format by Yann Collet;
strip: a group of adjacent 16 bytes of input data;
lane: the lanes, 16 bytes in the stripe, are divided into four lanes lane1/lane2/lane3/lane4, each lane containing 4 bytes of data.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
Example 1
Referring to fig. 1, the present embodiment provides a reconfigurable hardware for a hash algorithm, which includes the following structures:
the circuit comprises a state controller, an arithmetic unit, a plurality of selectors (selector 0, selector 1, selector 2 and selector 3) and a state register, wherein the arithmetic unit comprises a first multiplier, an adder, a loop left shifter and a second multiplier. The state controller is respectively and electrically connected with the selector 1, the selector 2, the circulation left shifter, the selector 3 and the state register; the input end of the selector 0 is respectively connected with the data input end and the state register; the output end of the selector 1 and the output end of the selector 0 are both connected with the input end of the multiplier; the output end of the selector 2 and the output end of the multiplier are both connected with the input end of the adder; the input end of the selector 2 is respectively connected with an initialization parameter channel and a state register; the output end of the adder is connected with the input end of the circulation left shifter; the output end of the circulation left shifter and the selector 3 are both connected with the input end of the second multiplier; the output end of the second multiplier is respectively connected with the output data end and the state register. Wherein the selectable parameters of the selector 1 include PRIME32_2 ═ 0x85EBCA77U, PRIME32_3 ═ 0xC2B2AE3DU, PRIME32_5 ═ 0x165667B1U, and constant 1; optional parameters of the selector 3 include PRIME32_1 ═ 0x9E3779B1U, PRIME32_4 ═ 0x27D4EB2FU, and constant 1.
The state register is divided into four storage blocks and respectively stores the operation results of the input data of the four channels.
Example 2
The embodiment provides reconfigurable hardware for a hash algorithm, which comprises a state controller, an arithmetic unit, a plurality of selectors and a state register, wherein the arithmetic unit is used for carrying out a hash calculation flow of 'multiply-add-shift-multiply'. The selector is embedded in the operation unit and used for selecting input parameters in the operation process. And the arithmetic unit outputs the arithmetic result to the state register for saving. The state controller controls the operation states of the operation unit, each selector and the state register.
Example 3
Referring to fig. 2, the present embodiment provides a method for operating reconfigurable hardware for a hash algorithm, including the following steps:
s1, the state controller determines whether the input data is valid, and if so, obtains the total byte length of the input data (the total byte length is continuously reduced along with the operation of the hardware, so the total byte length needs to be updated in real time). If the total byte length is not less than 16 bytes, the starting step of the stripe data processing mode is executed first, the state controller controls the selector 0 to select the input data, the selector 1 to select the PRIME32_2, the selector 2 to select the initialization parameter, the circular shifter to be set to shift left by 13 bits, and the selector 3 to select the PRIME32_ 1. Since the stripe data is 16 bytes, the input data of each channel is 4 bytes from four input data, assuming that the input data of the channel 1 is subjected to the operation of 'multiply-add-shift-multiply', an operation value is obtained, the operation value is stored in the storage block 1 corresponding to the channel 1 in the state register, and then the input data of the channel 2, the channel 3 and the channel 4 are operated, so that the operation of one stripe data is completed and the operation result is stored.
After the initial step of the first stripe data is completed, when the subsequent stripe data is processed, the control hardware executes a stripe data processing loop step, and specifically includes that the state controller controls the input data selected by the first selector, the PRIME32_2 selected by the second selector, the accumulation feedback loop of the state register selected by the third selector, the loop shifter is set to shift left by 13 bits, and the PRIME32_1 selected by the fourth selector. In this step, the historical operation value in each memory block in step S1 is substituted into the input data to perform operations such as accumulated displacement until the total byte length of the input data is less than 16 bytes, and a unique operation value corresponding to each channel is obtained.
And S2, when the total byte length of the input data acquired by the state controller is less than 16 bytes, the state controller selects and executes a channel convergence accumulation mode, namely the state controller controls a channel convergence loop of the state register selected by the first selector, a second selector selection constant 1, an accumulation feedback loop of the state register selected by the third selector and a cyclic shifter to be set as no-shift and a fourth selector selection constant 1. In this mode, the operation values of the four channels are accumulated into one accumulated operation value.
After the channel convergence accumulation mode is executed, the state controller selects to execute the remaining data processing mode,
s3, if the initial total byte length of the input data is [4,15], executing a first residual data processing mode, which starts with the following steps: the state controller controls the first selector to select input data, the second selector to select PRIME32_3, the third selector to select initialization parameters, the cyclic shifter to be set to shift left by 17, and the fourth selector to select PRIME32_ 4. At this time, the initial step processes 4 bytes of input data, if the total byte length of the processed input data is not lower than 4 bytes, the loop step is executed, the state controller controls the first selector to select the input data, the second selector to select PRIME32_3, the accumulation feedback loop of the state register selected by the third selector, the loop shifter to be set to shift left by 17 bits, and the fourth selector to select PRIME32_ 4. If the total byte length range of the remaining input parameters is [1,3], executing the step of the second remaining data processing mode.
S4, if the initial input data total byte length range is [1,3], executing a second residual data processing mode starting step, and controlling the first selector to select the input data, the second selector to select PRIME32_5, the third selector to select the initialization parameter, the cyclic shifter to be set to shift left by 11 bits, and the fourth selector to select PRIME32_1 by the state controller. After the initial processing, the remaining input data total byte length range is [1,2], and then the second remaining data processing mode loop step is executed.
The second remaining data processing mode loop step is specifically that the state controller controls the first selector to select the input data, the second selector to select PRIME32_5, the third selector to select the accumulation feedback loop of the state register, the loop shifter to set to shift left by 11 bits, and the fourth selector to select PRIME32_ 1.
As can be seen from fig. 2, the control state machine of the individual reconfigurable computing unit mainly implements control of the following states: the method comprises the steps of resetting state, initial state of strip data processing, initial state of residual data processing 1, initial state of residual data processing 2, circular state of strip data processing, four-channel aggregation accumulation state, circular state of residual data processing 1 and circular state of residual data processing 2.
After each state is processed, the length of the data to be processed is reduced in an accumulated mode according to the data consumption, and if all the data are processed, the state can be returned to the reset state. The switching of each state is entirely determined by the remaining data byte length.
In the stripe data processing, the result can be cached in different state registers each time the operation of one channel is processed. After all the stripe data are processed, the hardware unit can be configured into a four-channel convergence accumulation mode, and the results of all the channels are read from the state register to carry out successive accumulation operation.
The result of the aggregation accumulation also needs to be stored in a state register, then the hardware unit enters a residual data processing state, and the result of each residual data processing is stored in the state register again and fed back to the next residual data processing.
The complete controller state jump includes: the jump condition length represents the byte length of the input data to be processed, and different lengths of the data to be processed determine different calculation states. "continue aggregate accumulation" means to remain in the four-channel aggregate accumulation state until the four-channel accumulation calculation is completed.
On the system application level, especially an embedded platform, the number of required hardware computing units is evaluated according to different input data bit widths and rates, and on the premise of meeting the system performance requirement, the same hardware is reused to the maximum extent to carry out stripe data processing, channel aggregation accumulation and residual data processing. The reconfiguration and system adaptation work of the hardware computing unit can be completed only by adjusting the state controller.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and the spirit of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A reconfigurable hardware for hash algorithms, comprising:
the system comprises a state controller, an arithmetic unit, a plurality of selectors and a state register, wherein the arithmetic unit is used for executing a Hash calculation process; the operation unit is embedded with a plurality of selectors and is used for selecting input parameters of each operation step in the operation flow; the arithmetic unit outputs the arithmetic result of the Hash arithmetic flow to the state register for storage; the state controller controls the operation states of the arithmetic unit, each selector and the state register.
2. The reconfigurable hardware for hash algorithms according to claim 1, wherein said hardware further comprises:
the arithmetic unit comprises a first multiplier, an adder, a cycle left shifter and a second multiplier, and the plurality of selectors comprise a first selector, a second selector, a third selector and a fourth selector; the state controller is respectively and electrically connected with the second selector, the third selector, the circulating left shifter, the fourth selector and the state register; the input end of the first selector is respectively connected with the data input end and the state register; the output end of the second selector and the output end of the first selector are both connected with the input end of the multiplier; the output end of the third selector and the output end of the multiplier are both connected with the input end of the adder; the input end of the third selector is respectively connected with the initialization parameter channel and the state register; the output end of the adder is connected with the input end of the circulation left shifter; the output end of the circulation left shifter and the fourth selector are both connected with the input end of the second multiplier; the output end of the second multiplier is respectively connected with the output data end and the state register.
3. The reconfigurable hardware for hash algorithms according to claim 2, wherein the selectable parameters of the second selector include PRIME32_ 2-0 x85EBCA77U, PRIME32_ 3-0 xC2B2AE3DU, PRIME32_ 5-0 x165667B1U and constant 1; optional parameters of the fourth selector include PRIME32_1 ═ 0x9E3779B1U, PRIME32_4 ═ 0x27D4EB2FU, and constant 1.
4. The reconfigurable hardware for hash algorithms according to claim 1, wherein the status register comprises four register blocks, the four register blocks storing the operation results of four data lanes, respectively.
5. A method of operating reconfigurable hardware for hash algorithms, the method comprising:
the state controller monitors the total byte length of effective input data in real time and selects a calculation mode according to the total byte length, wherein the calculation mode comprises a strip data processing mode, a channel aggregation accumulation mode, a first residual data processing mode and a second residual data processing mode;
the state controller switches output parameters by controlling the selector, and sets the calculation mode to be a selected target calculation mode;
and the state controller sets displacement parameters of the cyclic shifter according to the target calculation mode and controls the operation unit to execute the operation on the input data in the target calculation mode.
6. The method of claim 5, wherein selecting the calculation mode based on the total byte length comprises:
if the total byte length is not less than 16 bytes, selecting a stripe data processing mode;
if the total bytes are lower than 16 bytes, selecting a channel aggregation accumulation mode, and judging whether the total bytes are not lower than 4 bytes after the execution of the channel aggregation accumulation mode is finished:
if so, selecting a first residual data processing mode;
if not, selecting a second residual data processing mode.
7. The method of claim 5, further comprising:
the stripe data processing mode comprises a stripe data processing starting step and a stripe data processing circulating step; the configuration parameters of the stripe data processing starting step comprise input data selected by a first selector, PRIME32_2 selected by a second selector, initialization parameters selected by a third selector, setting of a cyclic shifter to be shifted left by 13 bits, and PRIME32_1 selected by a fourth selector; the configuration parameters of the stripe data processing loop step comprise input data selected by a first selector, PRIME32_2 selected by a second selector, an accumulation feedback loop of a state register selected by a third selector, a loop shifter set to be shifted left by 13 bits, and PRIME32_1 selected by a fourth selector;
the configuration parameters of the channel convergence accumulation mode comprise a channel convergence loop of a state register selected by a first selector, a constant 1 selected by a second selector, an accumulation feedback loop of the state register selected by a third selector, a constant 1 selected by a fourth selector, and a non-displacement setting of a cyclic shifter;
the first residual data processing mode comprises a first residual data processing starting step and a first residual data processing circulating step, the configuration parameters of the first residual data processing starting step comprise first selector selected input data, second selector selected PRIME32_3, third selector selected initialization parameters, a circulating shifter set to shift left by 17 bits, and fourth selector selected PRIME32_ 4; the configuration parameters of the first remaining data processing loop step include first selector selected input data, second selector selected PRIME32_3, accumulation feedback loop of state register selected by third selector, setting of loop shifter to left shift by 17 bits, fourth selector selected PRIME32_ 4;
the second residual data processing mode comprises a second residual data processing starting step and a second residual data processing circulating step, the configuration parameters of the second residual data processing starting step comprise first selector selected input data, second selector selected PRIME32_5, third selector selected initialization parameters, a circulating shifter set to be shifted left by 11 bits, and fourth selector selected PRIME32_ 1; the configuration parameters for the second remaining data processing cycle step include first selector selected input data, second selector selected PRIME32_5, third selector selected status register accumulation feedback loop, cycle shifter set to shift left 11 bits, fourth selector selected PRIME32_ 1.
8. The method of claim 5, further comprising:
and the state controller performs validity check on the input data and the output data and outputs a check result.
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| CN113655992A (en) * | 2021-08-16 | 2021-11-16 | Oppo广东移动通信有限公司 | Hash function circuit, chip and communication equipment |
| CN113655992B (en) * | 2021-08-16 | 2024-03-15 | Oppo广东移动通信有限公司 | Hash function circuit, chip and communication equipment |
| CN116094691A (en) * | 2022-12-26 | 2023-05-09 | 声龙(新加坡)私人有限公司 | Data processing method, device and chip based on workload certification |
| CN116094691B (en) * | 2022-12-26 | 2023-11-03 | 声龙(新加坡)私人有限公司 | Data processing method, device and chip based on workload certification |
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