CN112115081A

CN112115081A - DMA transmission system and method between securities future field Fpga and computer

Info

Publication number: CN112115081A
Application number: CN202010973982.8A
Authority: CN
Inventors: 秦轶轩; 王松华; 朱志文
Original assignee: Nanjing Accelecom Information Technology Co ltd
Current assignee: Nanjing Accelecom Information Technology Co ltd
Priority date: 2020-09-16
Filing date: 2020-09-16
Publication date: 2020-12-22

Abstract

The invention belongs to the field of security finance, and relates to a system and a method for transmitting Fpga and computer in the field of security futures. A DMA transfer system between a coupon domain Fpga and a computer, comprising: the device comprises a PIO engine, a DMA package module, a DMA unpacking module, an arbitration module, a register module and a PCIE IP core. In the DMA package module, if the number of effective bytes is lower than the specific length, zero padding operation is carried out to supplement the specific length, if the number of effective bytes is larger than the specific length, segmentation operation is carried out to segment the message into a plurality of messages with specific message length, the specific length is set to be a multiple of 128 bytes, and the address starts from a 4K boundary. The invention also provides a transmission method of the low-delay transmission system between the Fpga in the security field and the computer, the dma transmission system and the method between the FPGA in the security futures field and the computer provided by the invention omit three times of interaction, data are directly transmitted, and delay is reduced.

Description

DMA transmission system and method between securities future field Fpga and computer

Technical Field

The invention belongs to the field of security finance, and relates to a system and a method for transmitting Fpga and computer in the field of security futures.

Background

The traditional Fpga DMA uplink transmission or downlink transmission generally needs three times of interaction; and (3) uplink transmission: step 1: initiating a DMA read request by Fpga for acquiring the content of an available descriptor in a memory; step 2: fpga receives data returned by the DMA read request, and analyzes the information of the available descriptor; and step 3: when data needs to be transmitted, Fpga initiates a DMA write request and sends the data to a cache space corresponding to the idle descriptor; and 4, step 4: after the data transmission is finished, Fpga initiates a DMA write request, updates the status bit of the descriptor and tells the CPU that the data is completely updated; downlink transmission: step 1: initiating a dma read request by Fpga for obtaining the descriptor content with data cache in the memory; step 2: fpga receives data returned by the DMA read request, and descriptor information of the data needing to be carried is analyzed; and step 3: initiating a DMA read request by Fpga, and carrying data in a cache space corresponding to the descriptor to the Fpga; and 4, step 4: after the data transmission is finished, Fpga initiates a DMA write request, updates the status bit of the descriptor and tells the CPU that the data is taken away. If the delay of each step is denoted by DN, the delay time of the uplink transmission is calculated as: d1+ D2+ D3+ D4. If the delay of each step is denoted by dN, the delay time of the downlink transmission is calculated as: d1+ d2+ d3+ d 4.

Disclosure of Invention

1. The technical problem to be solved is as follows:

the existing FPGA-DMA uplink transmission or downlink transmission needs three times of interaction and has long delay time.

2. The technical scheme is as follows:

in order to solve the above problems, a system for DMA transfer between a securities domain Fpga and a computer, comprising: the system comprises a PIO engine, a DMA package module, a DMA unpacking module, an arbitration module, a register module and a PCIE IP core, wherein the PCIE IP core is used for interaction between Fpga and a PCIE bus; the PIO engine comprises PIO read-write and DMA downlink transmission data, and PCIE opens up two spaces, wherein one space is used for a PIO read-write control register and a status register; the other is used for DMA downlink data transmission; the DMA engine performs DMA uplink data transmission and PIO read data return, and forms a message format according with a PCIE protocol according to the transmission length and the transmission address; an arbitration module: the DMA packed data is selected through an arbitration module, and the data which is passed through is uploaded; a register module: a series of control registers and status registers for controlling the DMA package and unpacking, including system reset control, DMA enable, channel enable, DMA initialization control, and the initial address of each channel; the size of the memory space, the read-write pointer and statistical information of the memory, and the state information; a DMA package module: a message to be sent is composed into a message with a specific length and a specific structure to be sent. The structure comprises effective byte number, supplementary ineffective byte and packet information; the packet information contains a packet head mark, a packet tail mark, effective byte number and a message serial number; calculating the transmission address of the uplink DMA according to the message serial number; DMA unpack module: unpacking according to the format of the packet following information and the effective bytes, analyzing the packet following information in the message, acquiring the channel number, the effective length, the address, the header mark and the effective byte number information, and then analyzing the effective bytes.

In the DMA package module, if the number of effective bytes is lower than the specific length, zero padding operation is carried out to supplement the specific length, if the number of effective bytes is larger than the specific length, segmentation operation is carried out to segment the message into a plurality of messages with specific message length, the specific length is set to be a multiple of 128 bytes, and the address starts from a 4K boundary.

The invention also provides a transmission method of a low-delay transmission system between the securities field Fpga and a computer, which comprises uplink transmission and downlink transmission and is characterized in that: in the uplink transmission, when DMA (direct memory access) packets are packed, uplink data are cut or filled to form a fixed load, and packet following information is added at the same time, wherein the packet following information comprises a serial number, an effective byte number, packet header and packet tail information and is used for software interaction; and the software extracts effective bytes, a packet head and a packet tail according to the packet following information.

3. Has the advantages that:

the dma transmission system and method between the FPGA and the computer in the field of securities futures provided by the invention omit three times of interaction, directly transmit data and reduce delay.

Drawings

Fig. 1 is a schematic diagram of a transmission system according to the present invention.

Fig. 2 is a diagram illustrating data transmission in an uplink direction.

Fig. 3 is a schematic diagram of data transmission in the lower direction.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings.

As shown in fig. 1, a system for DMA transfer between a securities domain Fpga and a computer, comprises: the system comprises a PIO engine, a DMA package module, a DMA unpacking module, an arbitration module, a register module and a PCIE IP core, wherein the PCIE IP core is used for interaction between Fpga and a PCIE bus; the PIO engine comprises PIO read-write and DMA downlink transmission data, and PCIE opens up two spaces, wherein one space is used for a PIO read-write control register and a status register; the other is used for DMA downlink data transmission; the DMA engine performs DMA uplink data transmission and PIO read data return, and forms a message format according with a PCIE protocol according to the transmission length and the transmission address; an arbitration module: the DMA packed data is selected through an arbitration module, and the data which is passed through is uploaded; a register module: a series of control registers and status registers for controlling the DMA package and unpacking, including system reset control, DMA enable, channel enable, DMA initialization control, and the initial address of each channel; the size of the memory space, the read-write pointer and statistical information of the memory, and the state information; a DMA package module: a message to be sent is composed into a message with a specific length and a specific structure to be sent. The structure comprises effective byte number, supplementary ineffective byte and packet information; the packet information contains a packet head mark, a packet tail mark, effective byte number and a message serial number; calculating the transmission address of the uplink DMA according to the message serial number; DMA unpack module: unpacking according to the format of the packet following information and the effective bytes, analyzing the packet following information in the message, acquiring the channel number, the effective length, the address, the header mark and the effective byte number information, and then analyzing the effective bytes.

To prevent problems with 4K boundaries, 64 or 128 byte alignment, etc.; the specific length is set to a multiple of 128 bytes and the address starts at a 4K boundary.

The invention also provides a transmission method of a low-delay transmission system between the securities field Fpga and a computer, which comprises uplink transmission and downlink transmission, as shown in fig. 2, in the uplink transmission, when DMA (direct memory access) packets are packaged, uplink data are cut or filled to form fixed load, and at the same time, packet following information is added, wherein the packet following information comprises a serial number, an effective byte number, a packet header and packet tail information and is used for software interaction; and the software extracts effective bytes, a packet head and a packet tail according to the packet following information.

Compared with the existing DMA, in the transmission method provided by the invention, the DMA transmission time is reduced by the time of D1, D2 and D4: the delay time of uplink transmission is: D3.

DMA uplink transmission has two modes, one mode is that the back pressure of a computer is ignored, and a message is directly sent upwards; one is that in response to the back pressure of the computer, the computer maintains a read pointer and the Fpga maintains a write pointer, both of which are stored in an internal register of the Fpga. The computer informs the read pointer of the Fpga computer through write operation, and compares the read pointer with the write pointer maintained by the Fpga computer to judge whether the effective storage space is contained.

As shown in fig. 3, in the downlink transmission, the computer actively writes the packet information into Fpga, where the packet information includes byte number, packet header indication, packet tail indication, packet sequence number, timestamp, channel number, address information, and the Fpga knows the role of the packet according to the information. Downlink transmission is not interactive, and compared with the existing DMA downlink transmission, the delay time of d1, d2 and d4 is reduced; the delay time of downlink transmission is: d3

And in the downlink transmission, a PIO (packet input offset) writing mode is adopted.

Starting from the memory address addr, the computer opens up N128-byte cache spaces with continuous addresses, wherein the address of the first cache space is addr, and the address of the second cache space is addr + 128; the address of the Nth cache space is addr + 128 × N; when the Fpga carries out DMA uplink transmission, the Fpga stores in a buffer space one by one and is used in a polling way; the information of the second round is contained in the packet information, and the field starts from 0, and the value is added with 1 once in each polling; the software calculates a register of a plurality of rounds by itself; default value is-1, and 1 is increased once polling; after the computer opens up N cache spaces, the field of each cache space is initialized to a value of-1. The value of the field in the register and the memory of the initial software is-1; when Fpga sends a first message, the segment corresponding to addr + 128 x 0 of the 0 th round becomes 0, after software comparison, the value-1 of the register is found not to be equal to 0, which shows that data is updated, then effective byte length information in the information of the following packet is extracted, and the corresponding data is taken away.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A system for DMA transfer between a securities domain Fpga and a computer, characterized by: the method comprises the following steps: the system comprises a PIO engine, a DMA package module, a DMA unpacking module, an arbitration module, a register module and a PCIE IP core, wherein the PCIE IP core is used for interaction between Fpga and a PCIE bus; the PIO engine comprises PIO read-write and DMA downlink transmission data, and PCIE opens up two spaces, wherein one space is used for a PIO read-write control register and a status register; the other is used for DMA downlink data transmission; the DMA engine performs DMA uplink data transmission and PIO read data return, and forms a message format according with a PCIE protocol according to the transmission length and the transmission address; an arbitration module: the DMA packed data is selected through an arbitration module, and the data which is passed through is uploaded; a register module: a series of control registers and status registers for controlling the DMA package and unpacking, including system reset control, DMA enable, channel enable, DMA initialization control, and the initial address of each channel; the size of the memory space, the read-write pointer and statistical information of the memory, and the state information; a DMA package module: a message to be sent is composed into a message with a specific length and a specific structure, and the structure comprises effective byte number, supplementary invalid byte and information of a packet; the packet information contains a packet head mark, a packet tail mark, effective byte number and a message serial number; calculating the transmission address of the uplink DMA according to the message serial number; DMA unpack module: unpacking according to the format of the packet following information and the effective bytes, analyzing the packet following information in the message, acquiring the channel number, the effective length, the address, the header mark and the effective byte number information, and then analyzing the effective bytes.

2. A system for DMA transfer between a securities area Fpga and a computer, according to claim 1, characterized in that: in the DMA package module, if the number of effective bytes is lower than the specific length, zero padding operation is carried out to supplement the specific length, if the number of effective bytes is larger than the specific length, segmentation operation is carried out to segment the message into a plurality of messages with specific message length, the specific length is set to be a multiple of 128 bytes, and the address starts from a 4K boundary.

3. The transmission method of a system for low-delay transmission between the securities domain Fpga and a computer according to claim 1 or 2, comprising an upstream transmission and a downstream transmission, characterized in that: in the uplink transmission, when DMA (direct memory access) packets are packed, uplink data are cut or filled to form a fixed load, and packet following information is added at the same time, wherein the packet following information comprises a serial number, an effective byte number, packet header and packet tail information and is used for software interaction; and the software extracts effective bytes, a packet head and a packet tail according to the packet following information.

4. The method of claim 3, wherein: DMA uplink transmission has two modes, one mode is that the back pressure of a computer is ignored, and a message is directly sent upwards; one is that responding to the back pressure of the computer, the computer maintains a read pointer, Fpga maintains a write pointer, the read pointer and the search write pointer both exist in the internal register of Fpga, the computer tells the read pointer of Fpga computer through write operation, and compares with the write pointer maintained by Fpga itself to judge whether there is a valid storage space.

5. The method of claim 3, wherein: in the downlink transmission, the computer actively writes the information along with the packet into Fpga, the information along with the packet comprises byte number, packet head indication, packet tail indication, message serial number, timestamp, channel number and address information, and the Fpga acquires the effect of the message according to the information.

6. The method of claim 5, wherein: and in the downlink transmission, a PIO (packet input offset) writing mode is adopted.

7. The method of any one of claims 3-6, wherein: starting from the memory address addr, the computer opens up N128-byte cache spaces with continuous addresses, wherein the address of the first cache space is addr, and the address of the second cache space is addr + 128; the address of the Nth cache space is addr + 128 × N; when the Fpga carries out DMA uplink transmission, the Fpga stores in a buffer space one by one and is used in a polling way; the information of the second round is contained in the packet information, and the field starts from 0, and the value is added with 1 once in each polling; the software calculates a register of a plurality of rounds by itself; default value is-1, and 1 is increased once polling; after the computer opens up N cache spaces, initializing the field of each cache space, wherein the value of the field is-1, and the values of the field in a register of the software and a memory at the beginning are-1; when Fpga sends a first message, the segment corresponding to addr + 128 x 0 of the 0 th round becomes 0, after software comparison, the value-1 of the register is found not to be equal to 0, which shows that data is updated, then effective byte length information in the information of the following packet is extracted, and the corresponding data is taken away.