CN112103289A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN112103289A
CN112103289A CN202010169087.0A CN202010169087A CN112103289A CN 112103289 A CN112103289 A CN 112103289A CN 202010169087 A CN202010169087 A CN 202010169087A CN 112103289 A CN112103289 A CN 112103289A
Authority
CN
China
Prior art keywords
gate
spacer
gate electrode
dielectric layer
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010169087.0A
Other languages
English (en)
Inventor
杨正宇
陈彦廷
李威养
杨复凯
陈燕铭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112103289A publication Critical patent/CN112103289A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

本文公开一种半导体装置及其制造方法。一种范例性半导体装置包括基板以及设置在基板上的至少两个栅极结构。每个上述至少两个栅极结构包括栅极电极以及沿着栅极电极的侧壁设置的一间隔物。上述间隔物包括再填充部分以及底部部分，其中上述间隔物的再填充部分具有漏斗形状，使得上述间隔物的再填充部分的顶部表面大于上述间隔物的再填充部分的底部表面。且源极/漏极接点被设置在基板上以及上述至少两个栅极结构的上述间隔物之间。

Description

半导体装置
技术领域
本公开涉及一种半导体装置，特别涉及一种具有漏斗状间隔物的半导体装置。
背景技术
集成电路(integrated circuit,IC)工业已经历了指数性的成长。IC的材料及设计在技术上的进步已经产生了好几世代的IC，其中每一代比起前一代，都具有更小、更复杂的电路。在IC发展的过程中，功能密度(functional density,例如：每单位芯片面积的互连装置的数量)通常会增加，而几何尺寸(例如：使用制造工艺所能产生的最小组件(或线路))则会缩小。这种微缩的过程通常会通过提高生产效率及降低相关成本来提供益处。然而，这种微缩也增加了IC加工及制造的复杂性，且若要实现这些进步，需要在IC加工及制造方面有着类似的发展。举例来说，已经观察到由于在源极/漏极(S/D)接点(contact)以及源极/漏极接点的倾斜(tilting)轮廓(源极/漏极接点的顶部表面大于源极/漏极接点的底部表面)的形成期间，硬遮罩覆盖层产生了偏移(shift)，因此在金属栅极与源极/漏极接点之间可能会产生较短的通道。可能由于较短的路径而发生电流泄漏(current leakage)，这可能会在电路测试(circuit probing)期间导致较低的良率，并因此降低半导体装置的性能。因此，需要有所改进。
发明内容
本公开实施例提供一种半导体装置，包括基板以及设置在基板上的至少两个栅极结构。每个上述至少两个栅极结构包括一栅极电极以及沿着上述栅极电极的侧壁设置的一间隔物。上述间隔物包括再填充部分以及底部部分，其中上述间隔物的再填充部分具有漏斗形状，使得上述间隔物的再填充部分的顶部表面大于上述间隔物的再填充部分的底部表面。上述半导体装置还包括源极/漏极接点，设置在基板上以及上述至少两个栅极结构的上述间隔物之间。
本公开实施例提供一种半导体装置，包括基板以及设置于基板上的隔离层。上述半导体装置亦包括设置于隔离层上的栅极结构。栅极结构包括栅极电极以及沿着栅极电极的侧壁设置的一间隔物。栅极电极的顶部表面小于栅极电极的底部表面。上述间隔物包括顶部部分及底部部分，且上述间隔物的顶部部分的顶部表面大于上述间隔物的顶部部分的底部表面。
本公开实施例提供一种半导体装置的形成方法，包括在基板上形成至少两个栅极结构，其中每个上述至少两个栅极结构包括栅极电极以及沿着栅极电极的侧壁的一间隔物。上述方法亦包括在基板上以及上述至少两个栅极结构之间形成层间介电层；蚀刻每个上述至少两个栅极结构的上述间隔物的顶部部分，以在栅极电极与层间介电层之间形成一沟槽，其中上述沟槽包括低于层间介电层的顶部表面的底部表面，且上述沟槽包括一倾斜侧壁，使得上述沟槽的顶部表面大于上述沟槽的底部表面；以及填充上述沟槽以形成上述间隔物的再填充部分。
附图说明
本公开从后续实施方式及附图可优选理解。须强调的是，依据产业的标准作法，各种特征并未按比例绘制，并仅用于说明的目的。事实上，各种特征的尺寸可能任意增加或减少以清楚论述。
图1是根据本公开一些实施例所示，制造半导体装置的范例性方法的流程图。
图2是根据本公开一些实施例所示，范例性半导体装置的三维透视图。
图3是根据本公开一些实施例所示，范例性半导体装置在图1的方法的中间阶段沿着图2所示的平面A-A的截面图。
图4是根据本公开一些实施例所示，范例性半导体装置在图1的方法的中间阶段沿着图2所示的平面A-A的截面图。
图5是根据本公开一些实施例所示，范例性半导体装置在图1的方法的中间阶段沿着图2所示的平面A-A的截面图。
图6是根据本公开一些实施例所示，范例性半导体装置在图1的方法的中间阶段沿着图2所示的平面A-A的截面图。
图7是根据本公开一些实施例所示，范例性半导体装置在图1的方法的中间阶段沿着图2所示的平面A-A的截面图。
图8是根据本公开一些实施例所示，范例性半导体装置在图1的方法的中间阶段沿着图2所示的平面A-A的截面图。
图9是根据本公开一些实施例所示，范例性半导体装置在图1的方法的中间阶段沿着图2所示的平面A-A的截面图。
图10是根据本公开一些实施例所示，范例性半导体装置在图1的方法的中间阶段沿着图2所示的平面A-A的截面图。
图11是根据本公开一些实施例所示，范例性半导体装置在图1的方法的中间阶段沿着图2所示的平面A-A的截面图。
附图标记说明：
100：方法
102～114：操作
200：半导体装置
202：基板
204：鳍片
208：隔离结构
210：栅极结构
212：栅极电极
214：栅极间隔物
216：栅极介电层
250：源极/漏极特征
270：层间介电层
A-A：平面
H1：高度
H2：深度
H3：高度
280：硬遮罩层
240：沟槽
H4：深度
H5：高度差
H6：高度
W1,W2,W3：宽度
214’：间隔物再填充部分
224：再填充间隔物结构
W4,W5,W6：宽度
290：源极/漏极接点
270’：第二层间介电层
270”：第三层间介电层
275：通孔
285：金属导线
具体实施方式
以下的公开提供许多不同实施例或范例，用以实施本公开的不同特征。本公开的各部件及排列方式，其特定范例叙述于下以简化说明。理所当然的，这些范例并非用以限制本公开。举例来说，若叙述中有着第一特征成形于第二特征之上或上方，其可能包含第一特征与第二特征以直接接触成形的实施例，亦可能包含有附加特征形成于第一特征与第二特征之间，而使第一特征与第二特征间并非直接接触的实施例。
此外，本公开可在多种范例中重复参考数字及/或字母。该重复的目的为简化及清晰易懂，且本身并不规定所讨论的多种实施例及/或配置间的关系。除此之外，本公开于下文所述的将一个特征形成于另一个特征上、连接至另一个特征、及/或耦接至另一个特征，可包括特征的形成是直接接触的实施例，以及亦可包括有额外特征被插入形成于特征之间，使得特征并未直接接触的实施例。此外，例如“较低”、“较高”、“水平”、“垂直”、“上方”、“上”、“下”、“下方”、“向上”、“向下”、“顶部”、“底部”等、及其衍生词(例如：“水平地”、“向下地”、“向上地”等)的空间相对术语被使用，以使本公开的一个特征与另一个特征之间的关系易于理解。空间相对术语旨于涵盖包含特征的装置的不同方向。再进一步来说，而当一数字或一数字范围以“大约”、“大概”或类似的用语描述，该用语旨在涵盖包括所述数字在内的合理数字，例如所述数字的+/-10％或于本技术领域中技术人员所理解的其他数值。举例来说，用语“约5nm”涵盖自4.5nm至5.5nm的尺寸范围。
本公开涉及半导体装置及其制造方法。由于半导体装置的微缩，半导体装置的不同组件之间的几何尺寸变得越来越小，这可能会引起一些问题并降低半导体装置的性能。举例来说，在传统的工艺中，因为硬遮罩的覆盖偏移(shifting)及/或制造偏差(deviation)，金属栅极与源极/漏极接点之间的空间可能会非常小，特别是在金属栅极与源极/漏极接点的顶部部分之间，因为源极/漏极接点可能会具有顶部部分较大而底部部分较小的漏斗(funnel)/倾斜(tilting)轮廓。当金属栅极与源极/漏极接点之间的空间太小时，在它们之间可能会发生电流泄漏(current leakage)，这可能导致低产率(yield)并损害半导体装置的性能。
本公开提供一种位在金属栅极与源极/漏极接点之间的漏斗状间隔物，以在金属栅极与源极/漏极接点之间(特别是顶部部分)提供安全之间隔，因此在操作期间将不会发生电流泄漏，且半导体装置的性能得以改善。理所当然地，这些优点仅仅是范例性的，且对于任何特定的实施例都不需要特定的优点。
图1是根据本公开一些实施例所示，用于制造半导体装置200(之后简称为装置200)的方法100的流程图。方法100仅为范例，且并非旨于将本公开内容限制于权利要求中明确记载的范围之外。可在方法100之前、之中、以及之后执行其他操作，且对于该方法的其他实施例，可以替换、移除、或移动所述的一些操作。下文结合其他附图描述方法100，这些附图显示了在方法100的中间阶段期间，装置200的各种三维及截面附图。具体来说，图2显示了装置200的三维附图。图3至图11显示沿图2所示的平面A-A(即沿X方向)截取的装置200的截面图。
装置200可为在集成电路(integrated circuit,IC)或其一部分的工艺期间制造的中间装置，装置200可包括静态随机存取存储器(static random-access memory,SRAM)及/或其他逻辑电路、无源元件(passive component)，例如电阻器、电容器和电感器、以及包括主动元件(active component)，例如p型FET(PFET)、n型FET(NFET)、鳍式FET(FinFET)、金属氧化物半导体场效晶体管(metal-oxide semiconductor field effecttransistors,MOSFET)、互补式金属氧化物半导体(complementary metal-oxidesemiconductor,CMOS)晶体管、双极性晶体管(bipolar transistor)、高压(high voltage)晶体管、高频(high frequency)晶体管、及/或其他存储器单元。装置200可为集成电路(IC)的下列区域的一部分：核心区域(通常被称为逻辑区域)、存储器区域(例如：静态随机存取存储器(SRAM)区域)、模拟区域、周边(peripheral)区域(通常被称为输入/输出(I/O)区域)、虚拟区域、其他合适的区域、或其组合。在一些实施例中，装置200可为IC芯片的一部分、系统单芯片(system on chip,SoC)、或其一部分。本公开不限于任何特定数量的装置或装置区域，也不限于任何特定的装置配置。举例来说，尽管所示的装置200是三维FET装置(例如：FinFET)，但本公开亦可提供用于制造平面FET装置的实施例。
参照图1及图2，在操作102中，方法100提供包括一或多个栅极结构210的半导体装置200。半导体装置200亦可包括一或多个鳍片204，自基板202突出并由隔离结构208所分隔。一或多个栅极结构210被设置于基板202及鳍片204上。栅极结构210定义鳍片204的通道区域(由栅极结构210所覆盖)、源极区域、以及漏极区域。栅极结构210可包括栅极电极212，以及沿着栅极电极212的侧壁设置的栅极间隔物214。栅极结构210可包括其他组件，例如一或多个栅极介电层216、阻挡层(barrier layer)、胶黏层(glue layer)、覆盖层(cappinglayer)、其他合适的薄层、或其组合，其中栅极介电层216被设置在隔离结构208上与栅极电极212下，及/或栅极电极212与栅极间隔物214之间。各种栅极硬遮罩层可被设置在栅极电极212上，且可被视作栅极结构210的一部分。装置200亦可包括在鳍片204的源极/漏极区域上外延(epitaxially)生长的源极/漏极特征250。装置200亦可以包括设置在基板202及鳍片204上，以及栅极结构210之间的层间介电(interlayer dielectric,ILD)层270。应理解的是，装置200中所包括的组件并不限于如图2所示的数量及配置。装置200中可包括更多或更少的组件，举例来说，更多或更少的鳍片以及栅极结构。在一些其他实施例中，装置200可为不具备鳍片结构的金属氧化物半导体场效晶体管(MOSFET)装置。
在图2所绘的实施例中，装置200包括基板(晶圆)202。在所绘实施例中，基板202是包括硅的体基板(bulk substrate)。替代地或附加地，体基板包括另一种元素半导体、化合物半导体、合金半导体、或其组合。替代地，基板202是绝缘层上半导体基板，例如绝缘层上硅(silicon-on-insulator,SOI)基板、绝缘层上硅锗(silicon germanium-on-insulator,SGOI)基板、或绝缘层上锗(germanium-on-insulator,GOI)基板。可使用布植氧分离(separation by implantation of oxygen,SIMOX)、晶圆接合(bonding)、及/或其他合适的方法来制造绝缘层上半导体基板。基板202可包括各种掺杂区域。在一些实施例中，基板202包括以n型掺杂物掺杂的n型掺杂区域(例如：n型井)，n型掺杂物例如磷(例如：31P)、砷、其他n型掺杂物、或其组合。在一些实施例中，基板202包括以p型掺杂物掺杂的p型掺杂区域(例如：p型井)，p型掺杂物例如硼(例如：11B、BF2)、铟、其他p型掺杂物、或其组合。可执行离子布植(ion implantation)工艺、扩散(diffusion)工艺、及/或其他合适的掺杂工艺，以形成各种掺杂区域。
半导体的鳍片204被形成在基板202上。每个鳍片204可适用于提供n型FET或p型FET。鳍片204的指向基本上彼此平行。每个鳍片204具有沿着它们在X方向上的长度定义的至少一个通道区域，以及至少一个源极区域与漏极区域(共同被称为源极/漏极区域)，其中至少一个通道区域被栅极结构所覆盖，被并设置于源极/漏极区域之间。在一些实施例中，鳍片204是基板202的一部分(例如：基板202的材料层的一部分)。举例来说，在所绘实施例中，在基板202包括硅的情况下，鳍片204包括硅。或者，在一些实施例中，鳍片204被定义于覆盖基板202的材料层中，例如一或多个半导体材料层。举例来说，鳍片204可包括半导体层堆叠，半导体层堆叠具有设置在基板202上的各种半导体层(例如：异质结构)。半导体层可包括任何合适的半导体材料，例如硅、锗、硅锗、其他合适的半导体材料、或其组合。根据装置200的设计需求，半导体层可包括相同或不同的材料、蚀刻速率、组成原子百分比(atomicpercentage)、组成重量百分比(weight percentage)、厚度、及/或配置。通过任何合适的工艺以形成鳍片204，包括各种沉积、光刻(photolithography)、及/或蚀刻工艺。
隔离结构208被形成在基板202上，并隔离鳍片204的下方部分。隔离结构208电性隔离装置200的主动装置区域及/或被动装置区域。隔离结构208可被配置为不同的结构，例如浅沟槽隔离(shallow trench isolation,STI)结构、深沟槽隔离(deep trenchisolation,DTI)结构、硅局部氧化(local oxidation of silicon,LOCOS)结构、或其组合。隔离结构208包括隔离材料，例如氧化硅、氮化硅、氮氧化硅、其他合适的隔离材料、或其组合。隔离结构208通过下列方法沉积：CVD、物理气相沉积(physical vapor deposition,PVD)、原子层沉积(atomic layer deposition,ALD)、高密度等离子体CVD(high densityplasma,HDPCVD)、金属有机CVD(metal organic CVD,MOCVD)、远程等离子体CVD(remoteplasma CVD,RPCVD)、PECVD、LPCVD、原子层CVD(ALCVD)、常压CVD(atmospheric pressureCVD,APCVD)、其他合适的沉积工艺、或其组合。在一些实施例中，隔离结构208的形成先于鳍片204的形成(隔离先制(isolation-first)方法)。在一些实施例中，鳍片204的形成会先于隔离结构208的形成(鳍片先制(fin-first)方法)。可在隔离结构208上执行平坦化工艺，例如化学机械研磨(chemical mechanical polishing,CMP)工艺。
在图2所绘实施例中，各种栅极结构210被形成在鳍片204上。栅极结构210沿着Y方向延伸，并横贯对应的鳍片204。栅极结构210接合(engage)对应的鳍片204的通道区域，使得电流可在操作期间于鳍片204的对应源极/漏极区域之间流动。每个栅极结构210可包括栅极介电层216及栅极电极212。栅极介电层216可包括高k值介电材料，高k值介电材料是所具有的介电常数大于二氧化硅(SiO2)的介电常数(约为3.9)的材料。在替代性实施例中，高k值栅极介电质可包括ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5、HfErO、HfLaO、HfYO、HfGdO、HfAlO、HfZrO、HfTiO、HfTaO、或SrTiO。栅极电极212可包括含金属材料。在一些实施例中，金属的栅极电极212可包括功函数(work function)金属组件及填充金属组件。功函数金属组件被配置以调谐其对应的FET的功函数，以达到期望的临界电压Vt。在各种实施例中，功函数金属组件可包含TiAl、TiAlN、TaCN、TiN、WN、W、其他合适的材料、或其组合。填充金属组件被配置以作为功能栅极结构的主要导电部分。在各种实施例中，填充金属组件可包含铝(Al)、钨(W)、铜(Cu)、或其组合。
栅极间隔物214被沿着栅极电极212及/或栅极介电层216的侧壁设置。栅极间隔物214可包括各种薄层，例如一或多个介电层及图案层。在一些实施例中，介电层顺应性地(conformally)形成在基板202上。图案层顺应性地形成在介电层上。介电层可包括任何合适的介电材料，例如硅、氧、碳、氮、其他合适的材料、或其组合(例如：氧化硅(SiO)、氮化硅(SiN)、氮氧化硅(SiON)、或碳化硅(SiC)、低k值介电质(k<3.9))，且可通过任何合适的方法形成，例如ALD、CVD、PVD、其他合适的方法、或其组合。图案层可包括具有与介电层不同的蚀刻速率的任何合适的材料，例如氮化硅(SiN)、碳氮氧化硅(SiOCN)、其他合适的介电材料、或其组合。图案层可通过任何合适的方法(例如：ALD)沉积到任何合适的厚度。之后，通过蚀刻工艺或任何其他合适的工艺移除介电层及图案层的顶部部分。蚀刻工艺可为干式蚀刻工艺、湿式蚀刻工艺、反应式离子蚀刻(reactive ion etching,RIE)工艺、或其组合。介电层及图案层的剩余部分沿着栅极电极212及/或栅极介电层216的侧壁形成栅极间隔物214。在一些实施例中，栅极间隔物214的每一层沿着X方向的厚度为约1纳米(nm)至约5nm。
在一些实施例中，在制造装置200的其他组件(例如：外延的源极/漏极特征250及层间介电层270)后，通过栅极替换工艺形成栅极结构210。在栅极替换工艺中，形成虚拟栅极结构以包裹各别鳍片204的通道区域。每个虚拟栅极结构可包括虚拟栅极电极(包括多晶硅)以及各种其他薄层，例如设置在虚拟栅极电极上的硬遮罩层，以及设置在鳍片204与基板202上且在虚拟栅极电极下的界面层。然后通过上述任何合适的方法，沿着虚拟栅极结构的侧壁形成栅极间隔物214。在形成外延的源极/漏极特征250以及层间介电层270后，使用一或多种蚀刻工艺(例如：湿式蚀刻、干式蚀刻、RIE、或其他蚀刻技术)沿着栅极间隔物214移除虚拟栅极结构，因此在鳍片204的通道区域上留下开口以取代被移除的虚拟栅极结构。接着通过各种工艺以介电材料填充开口来形成介电层216，各种工艺例如ALD、CVD、PVD、及/或其他合适的工艺。然后，将金属栅极材料沉积在介电层216上，以形成栅极结构210的金属栅极电极212。栅极电极212通过各种沉积工艺形成，例如ALD、CVD、PVD、及/或其他合适的工艺。可执行CMP工艺以移除栅极介电层216、栅极电极212、及/或栅极间隔物214的任何多余材料，以平坦化栅极结构210。
图3显示沿着图2所示的平面A-A的半导体装置200的截面图(意即沿着X方向)。在一些实施例中，栅极结构210沿Z方向的高度H1为约10nm至约60nm。
仍旧参照图2，装置200亦包括形成在鳍片204的源极/漏极区域中的外延的源极/漏极特征250。举例来说，半导体材料(例如硅锗(SiGe)、磷化硅(SiP)、或碳化硅(SiC))在鳍片204上外延生长，进而在鳍片204上形成外延的源极/漏极特征250。在一些实施例的进一步改进中，外延源极/漏极特征250(亦称为源极/漏极特征250)沿着Y方向横向延伸(生长)，使得外延源极/漏极特征250被合并为跨越一个以上鳍片的外延源极/漏极特征。在一些实施例中，外延源极/漏极特征250包括部分合并的部分及/或完全合并的部分。外延工艺可执行CVD沉积技术(例如：气相外延(vapor-phase epitaxy,VPE)、超高真空CVD(UHV-CVD)、LPCVD、及/或PECVD)、分子束外延、其他合适的SEG工艺、或其组合。外延工艺可使用气态及/或液态前驱物，这些前驱物与鳍片204的成分相互作用。在一些实施例中，根据在它们各自的FET装置区域中所制造的FET的类型，外延源极/漏极特征250被以n型掺杂物及/或p型掺杂物掺杂。在一些实施例中，外延源极/漏极特征250包括在通道区域中达到所期望的张应力(tensile stress)及/或压应力(compressive stress)的材料及/或掺杂物。在一些实施例中，在沉积期间通过将杂质添加到外延工艺的源材料中来掺杂外延源极/漏极特征250。在一些实施例中，在沉积工艺后，通过离子布植工艺来掺杂外延源极/漏极特征250。在一些实施例中，执行退火工艺以活化装置200的外延源极/漏极特征250中的掺杂物。
仍旧参照图2及图3，装置200包括形成在基板202(包括隔离结构208及源极/漏极特征250)上的层间介电(ILD)层270，且层间介电层270位于栅极结构210之间。层间介电层270包括介电材料，该介电材料包括例如氧化硅(SiO)、氮化硅(SiN)、氮氧化硅(SiON)、四乙氧基硅烷(tetraethylorthosilicate,TEOS)形成的氧化物、未掺杂的硅酸盐玻璃、或是掺杂的氧化硅，例如硼磷硅酸盐玻璃(borophosphosilicate glass,BPSG)、熔融石英玻璃(fused silica glass,FSG)、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼掺杂硅玻璃(boron doped silicon glass,BSG)、低k值介电材料、其他合适的介电材料、或其组合。在一些实施例中，层间介电层270具有包含多种介电材料的多层结构。在一些实施例中，可通过沉积工艺(例如：CVD、FCVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、电镀、其他合适的方法、或其组合)来形成层间介电层270，以覆盖隔离结构208、源极/漏极特征250、以及虚拟栅极结构。在沉积层间介电层270后，可执行CMP工艺及/或其他平坦化工艺以曝露虚拟栅极结构。在此之后，可执行上述金属栅极替换工艺，以用金属的栅极结构210替换虚拟栅极结构。
现在参照图1及图4，在操作104中，层间介电层270被掘入(recess)到深度H2，使得被掘入的层间介电层270的顶部表面位在栅极结构210的顶部表面下方。如图4所示，被掘入的深度H2低于栅极的高度H1。换句话说，高度为高度H3(等于高度H1与深度H2的差)的层间介电层270的下方部分被保留在基板202上。在一些实施例中，被掘入的深度H2为栅极的高度H1的约10％至约50％。因此，被掘入的层间介电层270沿着Z方向的高度H3为栅极的高度H1的约50％至约90％。在一些进一步的实施例中，被掘入的深度H2为约5nm至约20nm。被掘入的层间介电层270的高度H3为约10nm至约40nm。层间介电层270可通过任何合适的工艺来掘入。在一些实施例中，层间介电层270被以蚀刻工艺掘入，包括湿式蚀刻、干式蚀刻、其他合适的蚀刻工艺、或其组合。举例来说，通过选择性湿式蚀刻工艺掘入层间介电层270，其中仅移除层间介电层270的顶部部分，沿着层间介电层270的侧壁的栅极间隔物214基本上不会有变。根据装置200的设计要求，利用时间控制来控制蚀刻的程度，即被掘入的深度H2。
现在参照图1及图5，在操作106中，硬遮罩层280被沉积在基板202上，例如在层间介电层270、栅极结构210、以及源极/漏极特征250(亦称为外延源极/漏极特征250)上。在一些实施例中，硬遮罩层280可包括一或多层材料，例如硅(Si)、碳化硅(SiC)、氮化硅(SiN)、碳氧化硅(SiOC)、碳氮氧化硅(SiOCN)、其他合适的材料、或其组合。在一些实施例中，通过诸如ALD、CVD、PVD、及/或其他合适的工艺的沉积工艺以设置硬遮罩层280。如图5所示，沉积硬遮罩层280以覆盖被掘入的层间介电层270及栅极结构210。
参照图1及图6，仍旧是操作106，执行CMP工艺或其他平坦化工艺以移除硬遮罩层280的顶部部分，直到抵达并曝露栅极结构210。在一些实施例中，在平坦化工艺后，硬遮罩层280的顶部表面与栅极结构210的顶部表面基本共面(co-planar)。
现在参照图1及图7，在操作108中，移除栅极间隔物214的顶部部分以形成具有漏斗形状的沟槽240，意即，沟槽240的顶部表面大于沟槽240的底部表面。在移除栅极间隔物214的顶部部分后，被掘入的栅极间隔物214(栅极间隔物214的剩余的底部部分)的顶部表面位在被掘入的层间介电层270的顶部表面下方。在一些实施例中，操作108仅移除栅极间隔物214的顶部部分，且栅极介电层216基本上不会有变。在一些其他实施例中，如图7所示，在操作108中，不仅移除了栅极间隔物214的顶部部分，还移除了栅极介电层216的顶部部分。因此，栅极介电层216的顶部表面位在被掘入的层间介电层270的顶部表面下方，且栅极介电层216的高度基本上等于被掘入的栅极间隔物214的高度。在一些实施例中，栅极间隔物214被掘入到深度H4，例如约5nm至约25nm。在一些进一步的实施例中，每个被掘入的栅极间隔物214(栅极间隔物214的剩余底部部分)具有高度H6，且被掘入的栅极间隔物214的顶部表面比被掘入的层间介电层270的顶部表面低一个高度差H5。换句话说，高度差H5加上被掘入的栅极间隔物214的高度H6等于被掘入的层间介电层270的高度H3。在一些实施例中，高度差H5为被掘入的层间介电层270的高度H3的约20％至约50％。也就是说，被掘入的栅极间隔物214的高度H6，是被掘入的层间介电层270的高度H3的约50％至约80％。在一些进一步的实施例中，被掘入的栅极间隔物214的顶部表面与被掘入的层间介电层270的顶部表面之间的高度差H5为约3nm至约10nm。
在一些实施例中，在操作108中，栅极电极212的顶部部分亦在操作108中被横向地移除，以形成栅极电极212的顶部部分的倾斜侧壁。如图7所示，栅极电极212的顶部部分的每一侧的顶部表面被横向移除了宽度W1。沿着栅极电极212的侧壁向下，横向移除的宽度变得较小(向内渐缩)，且横向移除止于被掘入的栅极间隔物214的顶部表面。在一些实施例中，横向移除的宽度在被掘入的栅极间隔物214的顶部表面处基本变为零。因此，栅极电极212的顶部部分具有倾斜的侧壁。在一些进一步的实施例中，在操作108中，亦从横向地移除硬遮罩层280及被掘入的层间介电层270的一些部分。如图7所绘，硬遮罩层280的每一侧的顶部表面被横向移除了宽度W2。在一些实施例中，可相对于栅极电极212的顶部表面对称地移除硬遮罩层280的顶部表面，意即宽度W2等于宽度W1。在一些其他实施例中，可相对于栅极电极212的顶部表面不对称地移除硬遮罩层280的顶部表面，意即宽度W2大于或小于宽度W1。宽度W1及宽度W2的蚀刻程度与栅极电极212及硬遮罩层280的材料有关。不同的材料可能具有不同的蚀刻速率，这可能导致不同的蚀刻程度。相似地，沿着硬遮罩层280的侧壁以及被掘入的层间介电层270的侧壁向下，硬遮罩层280被横向移除的宽度变小(向内渐缩)，且横向移除止于被掘入的栅极间隔物214的顶部表面。在一些实施例中，横向移除的宽度在被掘入的栅极间隔物214的顶部表面处基本变为零。因此，硬遮罩层280以及被掘入的栅极间隔物214上的被掘入的层间介电层270的一部分，具有倾斜的侧壁，并与栅极电极212的倾斜侧壁对称或不对称(取决于装置200的设计要求及制造工艺)。在图7所绘的实施例中，栅极电极212的倾斜侧壁，与硬遮罩层280及被掘入的层间介电层270的倾斜侧壁对称。在一些实施例中，栅极电极212在X方向上的宽度W3为约10nm至约30nm，栅极电极212或硬遮罩层280的顶部表面的每一侧被横向移除的宽度W1为约1nm至约3nm。在一些其他实施例中，横向移除的宽度W1为栅极电极的宽度W3的约10％至约20％。在移除栅极间隔物214的顶部部分并横向移除栅极电极212、硬遮罩层280、以及被掘入的层间介电层270的侧面部分后，沟槽240由被掘入的栅极间隔物214的顶部表面以及栅极电极212、硬遮罩层280、与被掘入的层间介电层270的倾斜侧壁所形成，如图7所示。沟槽240具有漏斗形状，其中沟槽240的顶部表面大于沟槽240的底部表面。且栅极电极212在被掘入的栅极间隔物214上方的部分(栅极电极212的顶部部分)具有锥形轮廓，其中栅极电极212的顶部部分的顶部表面小于栅极电极212的顶部部分的底部表面，栅极电极212的顶部部分的底部表面基本上等于栅极电极212的底部表面。
在一些实施例中，通过适当的蚀刻工艺(例如干式蚀刻、湿式蚀刻、其他合适的蚀刻工艺、或其组合)移除栅极间隔物214、栅极电极212、硬遮罩层280、以及被掘入的层间介电层270的顶部部分。在一些实施例中，蚀刻工艺包括多个操作。举例来说，在第一操作中，对栅极间隔物214的顶部表面以及栅极电极212和硬遮罩层280的一些部分的顶部表面，执行反应式离子蚀刻(RIE)。在RIE期间，化学反应被施加以削弱栅极间隔物214的材料以及栅极电极212和硬遮罩层280的材料的顶部部分的键结(bonding)。削弱材料的键结可帮助后续的蚀刻工艺。在一些实施例中，可用约10瓦(watt,W)至约300W的功率轰击(bombard)等离子体(例如：氩基等离子体)以释放氩离子。氩离子可与栅极间隔物214的顶部部分以及栅极电极212、硬遮罩层280、和层间介电层270的侧面部分反应，使得栅极间隔物214的顶部部分以及栅极电极212、硬遮罩层280、和层间介电层270的侧面部分被破坏。在第二操作中，可施加干式蚀刻工艺，以自栅极间隔物214，栅极电极212、以及硬遮罩层280的受损部分的顶部表面向内逐渐变细，并在被掘入的栅极间隔物214(栅极间隔物214的剩余的底部部分)上形成漏斗状的沟槽240。在一些实施例中，干式蚀刻的施加，是使用氟化氢(hydrogenfluoride,HF)或三氟化氮(nitrogen trifluoride,NF3)作为化学气体，并以约10W至约200W的电极功率，在约50帕(Pa,等于100毫托(mTorr))至约200Pa下执行。在一些实施例中，可在室温至约摄氏200度的温度下施加干式蚀刻。通过时间来控制蚀刻的深度H4，使得可通过上述的蚀刻工艺来实现根据装置200的设计要求的漏斗状沟槽240。
现在参照图1及图8，在操作110中，间隔物再填充部分214’被沉积在基板202上以及漏斗状的沟槽240中。如图8所绘，间隔物再填充部分214’被设置在被掘入的栅极间隔物214、被掘入的栅极介电层216、锥形的栅极电极212、锥形的硬遮罩层280、以及锥形的层间介电层270上。在一些实施例中，间隔物再填充部分214’可包括一或多层材料，例如碳化硅(SiC)、氮化硅(SiN)、碳氧化硅(SiOC)、碳氮氧化硅(SiOCN)、其他合适的材料、或其组合。在一些实施例中，间隔物再填充部分214’可包括与硬遮罩层280相同的材料。在一些实施例中，间隔物再填充部分214’可包括具有与层间介电层270的材料不同的蚀刻选择性的材料，因此在随后的源极/漏极接点290的制造期间，即使接点开口图案发生了偏移，也仅有层间介电层270会被移除，且间隔物再填充部分214’将基本上不受影响，以在栅极电极212与源极/漏极接点290之间提供安全的空间。间隔物再填充部分214’可通过任何合适的沉积方法来形成，例如ALD、CVD、PVD、其他合适的方法、或其组合。
现在参照图1及图9，仍旧是操作110，诸如CMP的平坦化工艺被执行，以平坦化装置200的顶部表面。平坦化工艺移除间隔物再填充部分214’的顶部部分、硬遮罩层280、以及栅极电极212的顶部部分(在被掘入的层间介电层270上)，直到曝露出被掘入的层间介电层270。剩余之间隔物再填充部分214’以及被掘入的栅极间隔物214被称为再填充间隔物结构224。如图9所示，栅极电极212的剩余部分的高度，基本上等于被掘入的层间介电层270的高度H3。在一些实施例中，被掘入的层间介电层270的高度H3为约10nm至约40nm。剩余之间隔物再填充部分214’的高度H5为约3nm至约10nm，高度H5为再填充间隔物结构224(包括间隔物再填充部分214’以及被掘入的栅极间隔物214)的高度H3的约20％至约50％。如图9所绘，栅极电极212的顶部部分具有锥形轮廓，意即栅极电极212的顶部表面小于栅极电极212的底表面。在一些实施例中，栅极电极212的底部表面的宽度W3(或称为底部宽度W3)为约10nm至约30nm，而栅极电极212的顶部表面的宽度W4(或称为顶部宽度W4)为约8nm至约26nm，宽度W4为栅极电极212的底部宽度W3的约80％至约90％。同时，间隔物再填充部分214’(再填充间隔物结构224的顶部部分)具有漏斗轮廓，意即间隔物再填充部分214’的顶部表面大于间隔物再填充部分214’的底部表面。与传统的半导体装置结构相比，栅极电极212的锥形轮廓以及间隔物再填充部分214’的漏斗轮廓，可扩大金属栅极与后续形成的源极/漏极接点之间的空间，特别是在顶部表面。因此，可以减轻由金属栅极与源极/漏极接点之间的短路径(short path)所引起的电流泄漏，并且可以改善半导体装置的性能。在一些实施例中，间隔物再填充部分214’的底部表面的宽度W5(或称为底部宽度W5)为约2nm至约8nm，而间隔物再填充部分214’的顶部表面的宽度W6(或称为顶部宽度W6)为约3nm至约14nm，顶部宽度W6是间隔物再填充部分214’的底部宽度W5的约1.5倍至约2倍。
现在参照图1及图10，在操作112中，源极/漏极(S/D)接点290被形成在装置200的源极/漏极区域中。源极/漏极接点290可包括任何合适的导电材料，例如Ta、Ti、Al、Cu、Co、W、TiN、TaN、其他合适的导电材料、或其组合。可组合各种导电材料以为源极/漏极接点290提供各种薄层，例如一或多个阻挡层(barrier layer)、粘着层(adhesion layer)、衬垫层(liner layer)、块状层(bulk layer)、其他合适的薄层、或其组合。
源极/漏极接点290的形成可包括多个工艺，包括各种光刻、蚀刻、及/或沉积工艺。在一些实施例中，层间介电层270的一些部分可被移除，以形成用于沉积源极/漏极接点290的接点开口。举例来说，首先执行光刻工艺。光刻工艺可包括在装置200上形成光刻胶层(抗蚀层)、将光刻胶曝光以形成图案、执行曝后烤(ost-exposure bake)工艺、以及显影光刻胶以形成包括光刻胶的遮蔽元件。接着，遮蔽元件被用于蚀刻层间介电层270以形成接点开口。然后执行选择性蚀刻工艺，以移除层间介电层270在接点开口中的部分。蚀刻工艺可包括干式蚀刻工艺(例如：反应式离子蚀刻(RIE)工艺)、湿式蚀刻工艺、其他合适的蚀刻工艺、或其组合。因为再填充间隔物结构224(包括被掘入的栅极间隔物214以及间隔物再填充部分214’)的材料具有与层间介电层270的材料不同的蚀刻选择性，因此即使用于形成接点开口的遮蔽元件在制造过程中发生偏移，也仅有层间介电层270的部分会被移除，再填充间隔物结构224(包括被掘入的栅极间隔物214以及间隔物再填充部分214’)基本上不会有变。在一些实施例中，层间介电层270在沿着层间介电层270的侧壁下降的接点开口中向内渐缩。可在蚀刻工艺之前或之后移除图案化的光刻胶层。在一些实施例中，曝光工艺可执行无掩模光刻、电子束写入、离子束写入、及/或纳米印刷(nanoprint)技术。
替代地或附加地，通过选择性蚀刻工艺形成接点开口，其中层间介电层270基本上被完全移除，且由于不同的蚀刻选择性，再填充间隔物结构224(包括被掘入的栅极间隔物214以及间隔物再填充部分214’)基本上不受影响。
随后，将金属材料填充在接点开口中以形成源极/漏极接点290。通过以一或多种导电材料填充接点开口来形成源极/漏极接点290。可通过PVD、CVD、ALD、电镀、无电电镀(electroless plating)、其他合适的沉积工艺、或其组合来沉积导电材料。在一些实施例中，源极/漏极接点290填充在具有漏斗形状的接点开口中。因此，源极/漏极接点290具有漏斗/倾斜轮廓，其中源极/漏极接点290的顶部表面大于源极/漏极接点290的底部表面。之后，可执行一或多个研磨工艺(例如：CMP)，以移除任何多余的导电材料，并平坦化装置200的顶部表面。
如图10所绘，再填充间隔物结构224的顶部部分(即间隔物再填充部分214’)具有漏斗轮廓(较大的顶部表面及较小的底部表面)，而栅极电极212的顶部部分具有锥形轮廓(较小的顶部表面及较大的底部表面)。与间隔物及金属栅极的传统轮廓(即基本相等的顶部表面与底部表面面积(在XZ平面中为矩形))相比，本公开的再填充间隔物结构224以及栅极电极212可扩大金属栅极(例如：栅极电极212)与源极/漏极接点(例如：源极/漏极接点290)之间的距离，因此，尽管源极/漏极接点可能具有漏斗/倾斜轮廓及/或在源极/漏极接点的制造过程中遮蔽元件可能发生偏移，但金属栅极与源极/漏极接点之间的短路径问题仍可得到缓解。因此，电流泄漏得以降低且半导体装置的性能得以改善。
参照图1及图11，在操作114中，方法100执行进一步的处理以完成装置200的制造。举例来说，如图11所示，第二层间介电层270’被沉积在基板202上。可在沉积第二层间介电层270’之前沉积蚀刻停止层。蚀刻停止层及第二层间介电层270’的沉积，可包括任何适当的沉积工艺以及用于平坦化薄层的顶部表面的CMP。接着在第二层间介电层270’上形成图案化的光刻胶遮罩。随后，经由光刻胶遮罩蚀刻第二层间介电层270’，以在其中形成通孔切口(via cut)。在移除光刻胶遮罩后，以导电材料填充形成于第二层间介电层270’中的通孔切口，以形成源极/漏极通孔及/或栅极通孔(均称为通孔275)。通孔275的材料可包括任何合适的导电材料，例如铝(Al)、铜(Cu)、钨(W)、钌(Ru)、镍(Ni)、或其组合。可在通孔275与第二层间介电层270’之间形成阻挡层。阻挡层的材料可包括氮化钛(TiN)/钛(Ti)、氮化钽(TaN)/钽(Ta)、或其组合。之后，与第二层间介电层270’相似，可在基板202上沉积第三层间介电层270”。与通孔275的形成类似，可在第三层间介电层270”内形成金属导线285及其他通孔275。并且，根据装置200的设计要求，可在基板上形成其他层间介电层、金属导线、通孔、以及接点。装置200上的各种接点、通孔、导线、以及多层互连特征(例如：金属层及层间介电质)被配置来连接各种特征，以形成可包括一或多个多栅极装置的功能电路。在所绘实施例中，由于间隔物再填充部分214’，源极/漏极通孔与栅极电极之间的距离也得到了扩大，因此得以减轻由光刻胶遮罩偏移(覆盖偏移)所引起的漏电问题，且装置性能可得到改善。
尽管并非旨于限制，但本公开一或多个实施例为半导体装置及其形成工艺提供了诸多益处。举例来说，本公开实施例提供一种半导体装置，包括具有漏斗形的顶部部分之间隔物，以及具有锥形的顶部部分的金属栅极电极。间隔物的漏斗轮廓及金属栅极的锥形轮廓，扩大了源极/漏极接点与金属栅极之间的空间。因此，得以减轻由于源极/漏极接点与栅极电极之间的短路径所引起的电流泄漏问题，并且得以改善半导体装置的性能。
本公开提供许多不同实施例。具有漏斗状间隔物的半导体装置及其制造方法于本文中被公开。一种范例性半导体装置包括基板以及设置在基板上的至少两个栅极结构。每个上述至少两个栅极结构包括一栅极电极以及沿着上述栅极电极的侧壁设置的一间隔物。上述间隔物包括再填充部分以及底部部分，其中上述间隔物的再填充部分具有漏斗形状，使得上述间隔物的再填充部分的顶部表面大于上述间隔物的再填充部分的底部表面。上述半导体装置还包括源极/漏极接点，设置在基板上以及上述至少两个栅极结构的上述间隔物之间。
在一些实施例中，每个上述至少两个栅极结构的上述栅极电极包括顶部部分以及底部部分，其中上述栅极电极的顶部部分具有锥形形状，使得上述栅极电极的顶部部分的顶部表面小于上述栅极电极的顶部部分的底部表面。
在一些实施例中，包括再填充部分及底部部分的上述间隔物的高度，处于约10纳米至约40纳米，而上述间隔物的再填充部分的高度则处于约3纳米至约10纳米。
在一些实施例中，上述间隔物的再填充部分的高度对上述间隔物的高度的比例，处于约20％至约50％。
在一些实施例中，上述间隔物的再填充部分的材料是选自下列材料：碳化硅(SiC)、氮化硅(SiN)、碳氧化硅(SiOC)、碳氮氧化硅(SiOCN)、或其组合。
在一些实施例中，上述半导体装置还包括层间介电层，设置在上述间隔物与源极/漏极接点之间，其中上述间隔物的再填充部分的材料不同于层间介电层的材料。
在一些实施例中，上述间隔物的再填充部分的材料不同于上述间隔物的底部部分的材料。
另一种半导体装置包括基板以及设置于基板上的隔离层。上述半导体装置亦包括设置于隔离层上的栅极结构。栅极结构包括栅极电极以及沿着栅极电极的侧壁设置的一间隔物。栅极电极的顶部表面小于栅极电极的底部表面。上述间隔物包括顶部部分及底部部分，且上述间隔物的顶部部分的顶部表面大于上述间隔物的顶部部分的底部表面。
在一些实施例中，上述半导体装置还包括源极/漏极接点，源极/漏极接点具有大于底部表面的顶部表面，且上述间隔物被设置在栅极电极与源极/漏极接点之间。
在一些实施例中，栅极结构还包括栅极介电层，栅极介电层包括底部部分以及侧壁部分，栅极介电层的底部部分被设置在栅极电极与隔离层之间，而侧壁部分被设置在栅极电极与上述间隔物之间。栅极介电层的侧壁部分的高度小于栅极结构的高度，且栅极介电层的侧壁部分的高度基本上等于上述间隔物的底部部分的高度。
一种范例性方法，包括在基板上形成至少两个栅极结构，其中每个上述至少两个栅极结构包括栅极电极以及沿着栅极电极的侧壁的一间隔物。上述方法亦包括在基板上以及上述至少两个栅极结构之间形成层间介电层；蚀刻每个上述至少两个栅极结构的上述间隔物的顶部部分，以在栅极电极与层间介电层之间形成一沟槽，其中上述沟槽包括低于层间介电层的顶部表面的底部表面，且上述沟槽包括一倾斜侧壁，使得上述沟槽的顶部表面大于上述沟槽的底部表面；以及填充上述沟槽以形成上述间隔物的再填充部分。
在一些实施例中，上述方法还包括蚀刻上述至少两个栅极结构的上述间隔物之间的层间介电层，以形成接点开口；以及在接点开口中形成源极/漏极接点。
在一些实施例中，用于形成上述间隔物的再填充部分的对上述沟槽的填充，包括以一材料填充上述沟槽，其中上述材料具有不同于层间介电层的材料的蚀刻选择性。
在一些实施例中，上述方法还包括蚀刻层间介电层以形成被掘入层间介电层，使得被掘入层间介电层的顶部表面低于上述至少两个栅极结构的顶部表面；在被掘入层间介电层上形成硬遮罩层；以及其中对每个上述间隔物的顶部部分的蚀刻，包括横向蚀刻硬遮罩层的一部分、被掘入层间介电层的一部分、以及栅极电极的一部分，以形成上述沟槽的上述倾斜侧壁，且上述沟槽的底部表面低于被掘入层间介电层的顶部表面。
在一些实施例中，用于形成被掘入层间介电层的对层间介电层的蚀刻，包括蚀刻层间介电层使得被掘入层间介电层具有上述至少两个栅极结构的约50％至约90％的高度。
在一些实施例中，对栅极电极的第五顶部表面的横向蚀刻的程度，是栅极电极的宽度的约10％至约20％。
在一些实施例中，用于形成上述间隔物的再填充部分的对上述沟槽的填充，包括以一材料填充上述沟槽以形成上述间隔物的再填充部分，其中上述材料与硬遮罩层的材料相同。
在一些实施例中，用于形成上述沟槽的对每个上述间隔物的顶部部分的蚀刻，包括以氩基气体轰击上述间隔物的顶部表面；以及干式蚀刻上述间隔物的顶部部分以形成上述沟槽。
在一些实施例中，对上述间隔物的顶部表面的轰击是以氩基气体在约10瓦至约300瓦的功率下执行，而上述干式蚀刻则是使用氟化氢(HF)或三氟化氮(NF3)，以约10瓦至约200瓦的电极功率，在约50帕至约200帕的气体压力以及室温至约摄氏200度的温度下执行。
在一些实施例中，用于形成上述沟槽的对每个上述间隔物的顶部部分的蚀刻，包括蚀刻上述间隔物的顶部部分，使得上述沟槽的底部表面比层间介电层的顶部表面低约3纳米至约10纳米。
前述内文概述多项实施例或范例的特征，如此可使于本技术领域中技术人员优选地了解本公开的实施方式。本技术领域中技术人员应当理解他们可轻易地以本公开为基础设计或修改其他工艺及结构，以完成相同的目的及/或达到与本文介绍的实施例或范例相同的优点。本技术领域中技术人员亦需理解，这些等效结构并未脱离本公开的构思及范围，且在不脱离本公开的构思及范围的情况下，可对本公开进行各种改变、置换以及变更。

Claims (1)

1.一种半导体装置，包括：
一基板；
至少两个栅极结构，设置在上述基板上的上述至少两个栅极结构的每一者包括一栅极电极以及沿着上述栅极电极的侧壁设置的一间隔物，其中上述间隔物包括一再填充部分以及一底部部分，上述间隔物的上述再填充部分具有一漏斗形状，使得上述间隔物的上述再填充部分的顶部表面大于上述间隔物的上述再填充部分的底部表面；以及
一源极/漏极接点，设置在上述基板上以及上述至少两个栅极结构的上述间隔物之间。
CN202010169087.0A 2019-06-17 2020-03-12 半导体装置 Pending CN112103289A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/442,986 2019-06-17
US16/442,986 US10867870B1 (en) 2019-06-17 2019-06-17 Semiconductor device with funnel shape spacer and methods of forming the same

Publications (1)

Publication Number Publication Date
CN112103289A true CN112103289A (zh) 2020-12-18

Family

ID=73745223

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010169087.0A Pending CN112103289A (zh) 2019-06-17 2020-03-12 半导体装置

Country Status (3)

Country Link
US (3) US10867870B1 (zh)
CN (1) CN112103289A (zh)
TW (1) TW202101765A (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110875237B (zh) * 2018-08-29 2021-12-14 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US11183580B2 (en) * 2019-05-30 2021-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with metal gate stack
KR20220144076A (ko) * 2021-04-19 2022-10-26 삼성전자주식회사 반도체 장치

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007141903A (ja) * 2005-11-15 2007-06-07 Renesas Technology Corp 半導体装置およびその製造方法
JP5159828B2 (ja) * 2010-05-21 2013-03-13 パナソニック株式会社 半導体装置

Also Published As

Publication number Publication date
US20230052380A1 (en) 2023-02-16
US10867870B1 (en) 2020-12-15
US20210143069A1 (en) 2021-05-13
US11488874B2 (en) 2022-11-01
US20200395465A1 (en) 2020-12-17
TW202101765A (zh) 2021-01-01

Similar Documents

Publication Publication Date Title
US11688631B2 (en) Semiconductor structure with air gap and method sealing the air gap
US11367663B2 (en) Interconnect structure for fin-like field effect transistor
US11728216B2 (en) Semiconductor device with reduced contact resistance and methods of forming the same
US11973027B2 (en) Semiconductor device and methods of forming the same
KR20190058329A (ko) 게이트 유전체 보존 게이트 컷 프로세스
CN110875189A (zh) 半导体装置的形成方法
US11488874B2 (en) Semiconductor device with funnel shape spacer and methods of forming the same
US20210090959A1 (en) Air Spacer Formation for Semiconductor Devices
CN111223859A (zh) 半导体装置及其制造方法
CN113284951B (zh) 晶体管及其形成方法
US11107735B2 (en) Methods of forming epitaxial structures in fin-like field effect transistors
US11764281B2 (en) Gate air spacer for fin-like field effect transistor
EP3944295A1 (en) Semiconductor device with l-shape conductive feature and methods of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20201218

WD01 Invention patent application deemed withdrawn after publication