CN112103195B - Packaging structure with box dam and manufacturing method thereof - Google Patents
Packaging structure with box dam and manufacturing method thereof Download PDFInfo
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- CN112103195B CN112103195B CN202011235681.1A CN202011235681A CN112103195B CN 112103195 B CN112103195 B CN 112103195B CN 202011235681 A CN202011235681 A CN 202011235681A CN 112103195 B CN112103195 B CN 112103195B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
Abstract
The invention discloses a manufacturing method of a packaging structure with a box dam, which comprises the following steps: preparing a temporary bearing plate, and preparing a dielectric layer on the temporary bearing plate, wherein a first wiring layer and a conduction column positioned on the upper surface of the first wiring layer are arranged in the dielectric layer; preparing a second wiring layer on the outer surface of the dielectric layer, wherein the second wiring layer is in conduction connection with the first wiring layer through a conduction column; removing the temporary bearing plate, and respectively forming a first solder mask layer and a second solder mask layer on the upper surface and the lower surface of the dielectric layer; manufacturing a box dam on the outer surface of the first solder mask layer; respectively carrying out metal surface treatment on the first solder mask layer and the second solder mask layer; and mounting the device on the outer surface of the first solder mask layer, wherein the terminal of the device is connected with the second wiring layer, and laminating the packaging material to form a packaging layer so as to cover the dam and the device. Also disclosed is a packaging structure with a dam, comprising the dam and a device arranged in a space enclosed by the dam.
Description
Technical Field
The invention relates to a packaging structure of an electronic device with a dam, in particular to a packaging structure with a dam and a manufacturing method thereof.
Background
Most of the existing device packaging and embedding technologies adopt packaging substrates to mount devices and then carry out plastic packaging when the devices are packaged. Generally, the package substrate is complex in process and long in process, the yield of the package substrate product is about 95%, relevant substrate manufacturers mark each unit of the substrate after the substrate is manufactured, bad units are marked badly, so that the manufacturers in the later process can conveniently identify the badness, the mounting of devices in bad areas is avoided, and unnecessary waste of materials is reduced.
However, for products with high air tightness and reliability such as filters, if the package substrate is selectively mounted according to bad marks, when a plastic package material is attached to the plastic package, the amount of glue filling changes according to the number of devices, and the plastic package material flows relatively to a device-free area, which may cause the cavity of the peripheral area of the device without mounting, and abnormal rejection of the peripheral connected area due to the lack of glue. Therefore, when the subsequent mounting plastic package of the product is carried out, in order to ensure the stability of the glue filling amount, the whole-plate mounting device without identifying the yield of the substrate is generally adopted, so that a certain proportion of devices are directly wasted, and the great resource waste and the cost waste are caused. The key elements for solving the above problems are to improve the yield, reduce the manufacturing cost, and improve the product competitiveness, which is particularly urgent.
Disclosure of Invention
Embodiments of the present invention are directed to providing a package structure having a dam and a method of manufacturing the same to solve the above technical problems. According to the invention, the dam is prepared outside the solder resist layer, and the device is attached in the space surrounded by the dam, so that each unit has relative independence, the bad position of the substrate can be effectively avoided, the risk of local influence caused by individual influence is reduced, the device loss is reduced, the production cost is reduced, and the product yield is improved; when the packaging material is laminated, the top of the dam can effectively bear pressure, so that the possibility of pressure damage and failure of a vulnerable device is reduced; the height of the whole surface of the packaging layer is consistent, so that the packaging quality is ensured, and the packaging abnormity caused by height drop fluctuation is reduced; and the heat dissipation efficiency of the packaging structure with the box dam can be enhanced by setting the metalized box dam, and a good frame foundation is provided for subsequent heat dissipation.
A first aspect of the present invention relates to a method for manufacturing a package structure having a dam, comprising the steps of:
(a) preparing a temporary bearing plate, and preparing a dielectric layer on the temporary bearing plate, wherein a first wiring layer and a conduction column positioned on the upper surface of the first wiring layer are arranged in the dielectric layer;
(b) preparing a second wiring layer outside the dielectric layer, wherein the second wiring layer is in conductive connection with the first wiring layer through the conductive columns;
(c) removing the temporary bearing plate, and respectively forming a first solder mask layer and a second solder mask layer on the upper surface and the lower surface of the dielectric layer;
(d) manufacturing a peripheral dam outside the first solder resist layer;
(e) respectively carrying out metal surface treatment on the first solder mask layer and the second solder mask layer;
(f) mounting a device outside the first solder resist layer, wherein a terminal of the device is connected with the second wiring layer, and laminating an encapsulation material to form an encapsulation layer to cover the dam and the device.
In some embodiments, step (a) comprises the sub-steps of:
(a1) preparing a temporary bearing plate;
(a2) applying a first photoresist layer on the temporary bearing plate, and patterning the first photoresist layer to form a first characteristic pattern;
(a3) electroplating the first characteristic pattern to form a first wiring layer;
(a4) laminating a second photoresist layer outside the first wiring layer, and patterning the second photoresist layer to form a second feature pattern;
(a4) electroplating the second characteristic pattern to form a conducting column;
(a5) and removing the first photoresist layer and the second photoresist layer, laminating a dielectric material to form a dielectric layer, and thinning the dielectric layer to expose the end part of the conduction column.
In some embodiments, step (a 5) includes integrally thinning the dielectric layer by way of lapping or plasma etching to expose ends of the conductive vias.
In some embodiments, step (a 5) includes locally thinning the dielectric layer by laser or drilling to expose ends of the conductive vias.
In some embodiments, step (a 5) includes locally thinning the dielectric layer by exposure development to expose ends of the conductive vias.
In some embodiments, the dielectric material comprises an organic dielectric material, an inorganic dielectric material, or a combination thereof.
In some embodiments, the dielectric material comprises polyimide, epoxy, bismaleimide triazine resin, ceramic fillers, glass fibers, or combinations thereof.
In some embodiments, step (b) comprises the sub-steps of:
(b1) preparing a first metal seed layer outside the dielectric layer;
(b2) applying a third photoresist layer outside the first metal seed layer, and patterning the third photoresist layer to form a third feature pattern;
(b3) and electroplating the third photoresist layer to form a second wiring layer.
(b4) And removing the third photoresist layer, and etching away the exposed first metal seed layer.
In some embodiments, step (b 1) includes preparing a first metal seed layer on the dielectric layer by electroless plating or sputtering.
In some embodiments, the first metal seed layer comprises titanium, copper, a titanium tungsten alloy, or a combination thereof.
Preferably, a first metal seed layer is prepared outside the dielectric layer of the dielectric layer by sputtering 0.1 μm titanium and 1 μm copper.
In some embodiments, step (d) comprises the sub-steps of:
(d1) laminating a photosensitive dielectric material on the first solder mask layer;
(d2) exposing and developing the photosensitive medium material to form a fourth characteristic pattern;
(d3) removing exposed photosensitive dielectric material through the fourth feature pattern to form a dam in some embodiments, step (d) includes the substeps of:
(d1) silk-printing a solder resist material on the first solder resist layer;
(d2) exposing and developing the silk-screen solder resist material to form a fourth characteristic pattern;
(d3) forming a dam by removing exposed solder resist material through the fourth feature pattern in some embodiments, step (d) comprises the sub-steps of:
(d1) applying a fourth photoresist layer on the second solder mask layer;
(d2) preparing a second metal seed layer on the first solder mask layer;
(d3) applying a fifth photoresist layer on the second metal seed layer, and patterning the fourth photoresist layer to form a fourth feature pattern;
(d4) electroplating the fourth characteristic pattern to form a dam;
(d5) and removing the fourth photoresist layer and the fifth photoresist layer, and etching the exposed second metal seed layer.
In some embodiments, step (e) comprises performing a metal surface treatment on the first solder mask layer and the second solder mask layer by sputtering ni-pd-au or attaching a mechanical soldermask.
In some embodiments, step (f) includes disposing the device in the space enclosed by the dam and connecting the terminal of the device to the second wiring layer.
In some embodiments, the encapsulation material is selected from at least one of an epoxy resin, a benzocyclobutene resin, and a polyimide resin.
A second aspect of the present invention provides a package structure with a dam, which is prepared using the method for manufacturing a package structure with a dam as described above.
In some embodiments, the packaging structure includes a dam and a device disposed within a space enclosed by the dam.
In some embodiments, the ends of the dam are flush with or higher than the device.
In some embodiments, the device has a proportion of 1/5 to 1/2 in the space enclosed by the dam.
In some embodiments, the material of the dam includes a photosensitive dielectric material, a solder resist material, and a metal.
In some embodiments, the number of weirs is at least one.
Drawings
For a better understanding of the invention and to show embodiments thereof, reference is made to the accompanying drawings, purely by way of example.
With specific reference to the drawings, it must be emphasized that the specific illustrations are exemplary and are merely intended to illustratively discuss a preferred embodiment of the invention, and are presented in order to provide what is believed to be the most useful and readily understood illustration of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention; those skilled in the art will recognize how the several forms of the present invention may be embodied in practice with reference to the description of the figures. In the drawings:
fig. 1 is a schematic cross-sectional view of a package structure with a dam according to an embodiment of the present invention;
fig. 2(a) to 2(l) are schematic cross-sectional views showing intermediate structures of respective steps of the method for manufacturing the package structure with the dam shown in fig. 1.
Detailed Description
Referring to fig. 1, a cross-sectional schematic view of a package structure 100 having a dam is shown. The package structure 100 with the dam includes a dielectric layer 103, a first wiring layer 101 embedded in the dielectric layer 103, and a via 102, and a second wiring layer 104 on an upper surface of the dielectric layer 103, the via 102 conductively connecting the first wiring layer 101 and the second wiring layer 104. A plurality of conducting columns 102 with different sizes can be embedded in the dielectric layer 103, and the conducting columns 102 can be solid copper columns or hollow columns with copper plated surfaces; the end of the conductive via 102 may be flush with the dielectric layer 103 or lower than the dielectric layer 103; the conductive via 102 conductively connects the first wiring layer 101 and the second wiring layer 104, thereby achieving diffusion of heat generated by the device to the outer layer wiring.
A second solder resist layer 106 is formed on the lower surface of the dielectric layer 103, a first solder resist layer 105 is formed on the second wiring layer 104, a dam 107 is formed on the upper surface of the first solder resist layer 105, a device 108 is provided in a space surrounded by the dam 107, and a terminal of the device 108 is connected to the upper surface of the second wiring layer 104 through a first metal layer 1051. The device may have terminals on one side or both sides.
The material of the box dam 107 comprises photosensitive medium material, solder resist material and metal; when the dam 107 is made of metal, the heat dissipation efficiency of the package structure can be enhanced, and a good frame foundation is provided for subsequent heat dissipation. The number of the dam 107 is at least one, and usually, a plurality of dams 107 are formed on the upper surface of the first solder resist layer 105, and the plurality of dams 107 may be the same or different in size.
The ends of the dam 107 may be flush with the devices 108 or may be higher than the devices 108; the devices 108 are arranged in the space defined by the box dam 107, each unit formed by the box dam 107 and the devices 108 in the box dam 107 has relative independence, the bad position of the substrate can be effectively avoided, the risk of local influence caused by individual influence is reduced, the device loss is reduced, the production cost is reduced, and the product yield is improved; when the packaging materials are laminated, the top of the dam 107 can effectively bear pressure, so that the possibility of pressure damage and failure of a vulnerable device is reduced; the height of the whole surface of the packaging layer is consistent, the packaging quality is guaranteed, and the packaging abnormity caused by height drop fluctuation is reduced.
The proportion of the devices 108 in the space surrounded by the box dam 107 is 1/5-1/2; the width of the dam 107 can be calculated according to the filling amount during the post-packaging process, so that the dam 107 occupies a larger space ratio, the ratio of the device 108 in the space surrounded by the dam 107 is increased, and the phenomenon that the plastic package material in the peripheral area flows to cause poor filling and scrapping of the peripheral unit due to the fact that the filling amount required by the poor unit is too large when the single device with poor substrate is not mounted is reduced.
As shown in fig. 1, the package structure 100 includes an encapsulation layer 109 encapsulating the device 108 and the dam 107; the end part of the dam 107 is flush with the packaging layer 109 or lower than the packaging layer 109, and the height of the whole packaging layer 109 is consistent, so that the packaging quality is ensured, and the packaging abnormity caused by height drop fluctuation is reduced.
In some embodiments, multiple devices 108 may be included within the space enclosed by the same dam 107, with the multiple devices 108 separated by the encapsulation material.
Referring to fig. 2(a) -2 (l), there are shown schematic cross-sectional views of intermediate structures of various steps of a method of manufacturing the packaging structure with a dam 100 of fig. 1.
The manufacturing method comprises the following steps: preparing a temporary carrier plate-step (a), as shown in FIG. 2 (a). The temporary bearing plate can be any metal plate or glass substrate with a separation layer applied on the surface, such as a copper plate, an aluminum plate, a stainless steel plate or an aluminum alloy plate, and can also be a sacrificial copper foil or a surface copper clad plate. Preferably, the temporary bearing plate in this embodiment is a double-layer copper-clad plate in which double-layer copper foils are respectively covered on both sides of the insulating layer, and the double-layer copper foils are physically pressed together, so that the temporary bearing plate is easy to separate and can be added with layers on both sides simultaneously. As shown in fig. 2(a), the temporary carrier includes an insulating layer 110, a first copper layer 111, a second copper layer 112 and a protection layer 113 sequentially disposed from the insulating layer 110 to the outside; the first copper layer 111 and the second copper layer 112 are physically pressed by copper foil, a board separating surface in a subsequent process is formed between the first copper layer 111 and the second copper layer 112, the protective layer 113 may be formed by electroplating metal, and a material of the protective layer 113 may be selected from at least one of copper, titanium, nickel, and tungsten, which is not particularly limited. The thicknesses of the first copper layer 111, the second copper layer 112, and the protective layer 113 are respectively adjustable, and preferably, the thickness of the first copper layer 111 is 18 μm, the thickness of the second copper layer 112 is 3 μm, and the thickness of the protective layer is 3 to 10 μm. It should be noted that, the temporary carrier plate has a symmetrical structure, and in actual manufacturing, layers can be added on the upper and lower sides of the insulating layer 110 at the same time, and 2 substrates can be obtained by later-stage plate separation, and the substrates can be a grid-shaped matrix array and include a plurality of cells. The subsequent figures only show the manufacturing process of one side of the temporary bearing plate, and the manufacturing process of the other side is the same.
Next, a first photoresist layer 114 is applied outside the protection layer 113, and the first photoresist layer 114 is patterned to form a first feature pattern, step (b), as shown in fig. 2 (b). Typically, after the first photoresist layer 114 is applied, the first photoresist layer 114 is exposed and developed to form a first feature pattern.
Then, the first feature pattern is electroplated to form the first wiring layer 101, the second photoresist layer 115 is applied outside the first wiring layer 101, and the second photoresist layer 115 is patterned to form the second feature pattern — step (c), as shown in fig. 2 (c). In general, the first wiring layer 101 may be formed by filling the first feature pattern with copper plating.
Next, the second feature pattern is electroplated to form the conductive via 102, and the first photoresist layer 114 and the second photoresist layer 115 are removed (step (d)), as shown in fig. 2 (d). The conductive via 102 may be formed by electroplating copper to fill the second feature pattern.
The dielectric material is then laminated and pre-cured to form the dielectric layer 103, step (e), as shown in fig. 2 (e). In general, in order to ensure the filling effect, the amount of the dielectric material is calculated according to the filling amount, and the surface of the dielectric layer 103 is preferably 5 to 20 μm higher than the end of the conductive via 102. The dielectric material may include an organic dielectric material, an inorganic dielectric material, or a combination thereof, and may include, for example, polyimide, epoxy, bismaleimide, triazine resin, ceramic filler, glass fiber, or a combination thereof; and the medium materials can be photosensitive medium materials and non-photosensitive medium materials according to functional division.
Next, the end of the conductive via 102 is exposed, step (f), as shown in fig. 2 (f). Typically, the end portions of the conductive vias 102 may be exposed by thinning the dielectric layer 103 entirely, e.g., the end portions of the conductive vias 102 may be exposed by thinning the dielectric layer 103 entirely by way of plate grinding or plasma etching; the end of the conductive via 102 may also be exposed by locally thinning the dielectric layer 103, for example, the end of the conductive via 102 may be exposed by locally thinning the dielectric material on the upper surface of the conductive via 102 by laser or drilling; or when the dielectric material is a photosensitive dielectric material, the dielectric material on the upper surface of the conductive via 102 may be locally thinned by exposure and development to expose the end of the conductive via 102.
Then, a second wiring layer 104 is fabricated outside the dielectric layer 103-step (g), as shown in fig. 2 (g). Generally, the following substeps are included:
manufacturing a first metal seed layer 116 outside the dielectric layer 103;
applying a third photoresist layer outside the first metal seed layer 116, and patterning the third photoresist layer to form a third feature pattern;
electroplating the third feature pattern to form a second wiring layer 104;
the third photoresist layer is removed and the exposed first metal seed layer 116 is etched.
Generally, the first metal seed layer 116 is fabricated on the outside of the dielectric layer 103, and the first metal seed layer 116 can be fabricated on the outside of the dielectric layer 103 by chemical plating or sputtering; the material of the first metal seed layer 116 may be selected from titanium, copper, titanium tungsten alloy or their combination, and is not limited in particular, for example, the first metal seed layer may be formed outside the dielectric layer 103 by sputtering 0.1 μm titanium and 1 μm copper.
Next, a sixth photoresist layer is applied outside the second wiring layer 104, the first copper layer 111 and the second copper layer 112 are separated and the second copper layer 112 and the protection layer 113 are etched, and the sixth photoresist layer is removed — step (h), as shown in fig. 2 (h). In general, a sixth photoresist layer is attached to the outside of the second wiring layer 104 as a protection layer, and a full-scale exposure is performed to protect the second wiring layer 104 in a subsequent process of etching the second copper layer 112 and the protection layer 113. After the first copper layer 111 and the second copper layer 112 are separated, the second copper layer 112 and the protection layer 113 may be etched by using an etching solution.
Then, a first solder resist layer 105 is formed outside the second wiring layer 104, and a second solder resist layer 106 is formed on the lower surface of the dielectric layer 103 — step (i), as shown in fig. 2 (i). Generally, a silk-screen method may be adopted to fabricate the first solder mask layer 105 and the second solder mask layer 106 outside the second wiring layer 104 and on the lower surface of the dielectric layer 103, respectively.
Next, a dam 107 is formed outside the first solder resist layer 105, step (j), as shown in fig. 2 (j). Generally, a plurality of dams 107 are provided on the upper surface of the first solder resist layer 105, and the plurality of dams 107 may be the same or different in size; the material of the dam 107 may be selected from a photosensitive dielectric material, a solder resist material, or a metal; when the material of the dam 107 is metal, the heat dissipation efficiency of the package body can be enhanced, and a good frame foundation is provided for subsequent heat dissipation.
When the dam 107 is made of a photosensitive dielectric material, the dam 107 can be made outside the first solder resist layer 105 by the following sub-steps:
laminating a photosensitive dielectric material on the first solder resist layer 105;
exposing and developing the photosensitive medium material to form a fourth feature pattern;
when the dam 107 is made of solder resist material by removing exposed photosensitive dielectric material through the fourth feature pattern, the dam 107 may be made outside the first solder resist layer 105 by the following sub-steps:
screen printing solder resist material outside the first solder resist layer 105;
exposing and developing the silk-screen solder resist material to form a fourth characteristic pattern;
when the dam is made of metal by removing the exposed solder resist material by the fourth feature pattern to form the dam 107, the dam 107 may be made outside the first solder resist layer 105 by the following sub-steps:
applying a fifth photoresist layer over the second solder mask layer 106;
preparing a second metal seed layer outside the first solder resist layer 105;
applying a fourth photoresist layer outside the second metal seed layer, and patterning the fourth photoresist layer to form a fourth feature pattern;
electroplating metal in the fourth feature pattern to form a dam 107;
and removing the fourth photoresist layer and the fifth photoresist layer, and removing the exposed second metal seed layer.
Generally, the width and height of the box dam 107 are set according to actual requirements: the height of the dam 107 is larger than or equal to that of the device 108, and when packaging materials are laminated subsequently, the dam 107 can prevent the device 108 from being directly subjected to lamination acting force, so that the possibility of damage of the device is reduced; and the height of the dam 107 is larger than or equal to that of the device 108, so that the filling rate in the unit is ensured when the packaging material is laminated subsequently, and the poor filling in the unit caused by the loss of the packaging material of the peripheral unit is avoided. The width of the dam 107 can be calculated according to the filling amount of the packaging material during subsequent packaging, so that the dam 107 occupies a larger space, and the probability that the peripheral unit is discarded due to poor filling caused by the flowing of the packaging material in the peripheral area due to too large filling amount required by the poor unit when no device is mounted in the poor unit of the substrate is reduced.
Then, the first solder resist layer 105 and the second solder resist layer 106 are respectively subjected to metal surface treatment — step (k), as shown in fig. 2 (k). Generally, the first metal layer 1051 and the second metal layer 1061 may be formed by performing metal surface treatment on the first solder resist layer 105 and the second solder resist layer 106 by sputtering nickel-palladium-gold or Organic Soldermask (OSP), respectively.
Next, the device 108 is mounted outside the first solder resist layer 105, in which the terminals of the device 108 are connected to the second wiring layer 104, and an encapsulation material is laminated to form an encapsulation layer 109 to cover the dam 107, the device 108, step (l), as shown in fig. 2 (l). In general, the device 108 is disposed in a space surrounded by the dam 107 and the terminal of the device 108 is connected to the second wiring layer 104; the terminals of the device 108 are soldered to the second wiring layer 104 through the first metal layer 1051. The packaging material may be at least one selected from epoxy resin, benzocyclobutene resin, and polyimide resin; for example, a combination of an epoxy resin and a polyimide resin.
In general, layers may be added or removed as needed, and for example, when layers are added as needed, the layers may be added by exposing the end of the conductive via 102 and then repeating the wiring layer and the conductive via formation, or the layers may be added after the first copper layer 111 and the second copper layer 112 are separated and the second copper layer 112 and the protective layer 113 are etched.
Those skilled in the art will recognize that the present invention is not limited to what has been particularly shown and described hereinabove and hereinbelow. Rather, the scope of the present invention is defined by the appended claims, including both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description.
In the claims, the terms "comprise" and variations such as "comprises," "comprising," and the like, mean that the recited elements are included, but generally not the exclusion of other elements.
Claims (16)
1. A method of manufacturing a package structure having a dam, comprising the steps of:
(a) preparing a temporary bearing plate, and preparing a dielectric layer on the temporary bearing plate, wherein a first wiring layer and a conduction column positioned on the upper surface of the first wiring layer are arranged in the dielectric layer;
(b) preparing a second wiring layer outside the dielectric layer, wherein the second wiring layer is in conductive connection with the first wiring layer through the conductive columns;
(c) removing the temporary bearing plate, and respectively forming a first solder mask layer and a second solder mask layer on the upper surface and the lower surface of the dielectric layer;
(d) manufacturing a peripheral dam outside the first solder resist layer;
(e) respectively carrying out metal surface treatment on the first solder mask layer and the second solder mask layer;
(f) marking areas surrounded by the enclosing dams as good units and bad units respectively through detection, wherein devices are pasted outside the first solder resisting layer in the good units, terminals of the devices are connected with the second wiring layer, the devices are not pasted in the bad units, and packaging materials are laminated to form packaging layers for coating the good units and the bad units;
and the ratio of the devices in the good product units in the space surrounded by the dams is 1/5-1/2.
2. The method for manufacturing a package structure with a dam of claim 1, wherein the step (a) comprises the substeps of:
(a1) preparing a temporary bearing plate;
(a2) applying a first photoresist layer on the temporary bearing plate, and patterning the first photoresist layer to form a first characteristic pattern;
(a3) electroplating the first characteristic pattern to form a first wiring layer;
(a4) laminating a second photoresist layer outside the first wiring layer, and patterning the second photoresist layer to form a second feature pattern;
(a4) electroplating the second characteristic pattern to form a conducting column;
(a5) and removing the first photoresist layer and the second photoresist layer, laminating a dielectric material to form a dielectric layer, and thinning the dielectric layer to expose the end part of the conduction column.
3. The method of manufacturing a package structure with a dam according to claim 2, wherein the step (a 5) includes integrally thinning the dielectric layer by way of a grinding plate or plasma etching to expose an end portion of the conductive via.
4. The method of manufacturing a package structure with a dam of claim 2, wherein step (a 5) includes locally thinning the dielectric layer by means of laser or mechanical drilling to expose an end of the conductive via.
5. The method for manufacturing a package structure with a dam according to claim 2, wherein the step (a 5) comprises locally thinning the dielectric layer by exposure and development to expose an end portion of the conductive via.
6. The method of manufacturing a packaging structure with a dam of claim 2, wherein the dielectric material comprises an organic dielectric material, an inorganic dielectric material, or a combination thereof.
7. The method of manufacturing a packaging structure with a dam of claim 2, wherein the dielectric material comprises polyimide, epoxy, bismaleimide triazine resin, ceramic filler, glass fiber, or a combination thereof.
8. The method for manufacturing a package structure with a dam of claim 1, wherein the step (b) comprises the substeps of:
(b1) preparing a first metal seed layer outside the dielectric layer;
(b2) applying a third photoresist layer outside the first metal seed layer, and patterning the third photoresist layer to form a third feature pattern;
(b3) electroplating the third photoresist layer to form a second wiring layer;
(b4) and removing the third photoresist layer and etching the exposed first metal seed layer.
9. The method for manufacturing a package structure with a dam of claim 8, wherein step (b 1) comprises preparing a first metal seed layer on the dielectric layer by electroless plating or sputtering.
10. The method of claim 8, wherein the first metal seed layer comprises titanium, copper, titanium tungsten alloy, or a combination thereof.
11. The method for manufacturing a package structure with a dam of claim 1, wherein the step (d) comprises the substeps of:
(d1) laminating a photosensitive medium material on the first solder mask layer;
(d2) exposing and developing the photosensitive medium material to form a fourth characteristic pattern;
(d3) and removing the exposed photosensitive dielectric material through the fourth characteristic pattern to form a dam.
12. The method for manufacturing a package structure with a dam of claim 1, wherein the step (d) comprises the substeps of:
(d1) silk-printing a solder resist material outside the first solder resist layer;
(d2) exposing and developing the silk-screen solder resist material to form a fourth characteristic pattern;
(d3) removing the exposed solder resist material through the fourth feature pattern to form a dam.
13. The method for manufacturing a package structure with a dam of claim 1, wherein the step (d) comprises the substeps of:
(d1) applying a fourth photoresist layer outside the second solder resist layer;
(d2) preparing a second metal seed layer outside the first solder resist layer;
(d3) applying a fifth photoresist layer outside the second metal seed layer, and patterning the fourth photoresist layer to form a fourth feature pattern;
(d4) electroplating the fourth characteristic pattern to form a dam;
(d5) and removing the fourth photoresist layer and the fifth photoresist layer, and etching the exposed second metal seed layer.
14. The method for manufacturing a package structure with a dam according to claim 1, wherein the step (e) comprises performing metal surface treatment on the first solder resist layer and the second solder resist layer respectively by sputtering ni-pd-au or attaching a mechanical solder mask.
15. The manufacturing method of a package structure having a dam according to claim 1, wherein the step (f) comprises disposing a device in a space surrounded by the dam and connecting a terminal of the device to the second wiring layer.
16. The method of manufacturing a packaging structure with a dam according to claim 1, wherein the packaging material is selected from at least one of epoxy resin, benzocyclobutene resin, polyimide resin.
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| TWI840213B (en) | 2022-08-08 | 2024-04-21 | 大陸商珠海越亞半導體股份有限公司 | Embedded device packaging substrate and manufacturing method thereof |
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| CN113130420A (en) * | 2021-03-19 | 2021-07-16 | 南通越亚半导体有限公司 | Embedded packaging structure and manufacturing method thereof |
| CN114914222A (en) | 2022-03-01 | 2022-08-16 | 珠海越亚半导体股份有限公司 | Bearing plate for preparing packaging substrate, packaging substrate structure and manufacturing method thereof |
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