CN112103192A - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN112103192A CN112103192A CN202010788908.9A CN202010788908A CN112103192A CN 112103192 A CN112103192 A CN 112103192A CN 202010788908 A CN202010788908 A CN 202010788908A CN 112103192 A CN112103192 A CN 112103192A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
Abstract
The application discloses a chip packaging structure and a manufacturing method thereof, wherein the method comprises the following steps: providing an organic frame comprising metal posts and a core-embedded cavity; attaching a chip with the front side arranged upwards in the core embedding cavity; laminating a dielectric layer to cover the upper surface of the organic frame and the front surface and the peripheral surface of the chip; the dielectric layer is subjected to graphical processing to form a plurality of chip front side heat dissipation windows, chip terminal windows and metal column windows, lower surface adhesive tapes are removed, graphical processing is carried out on the upper surface and the lower surface, deposited metal forms a circuit layer and a heat dissipation layer, the circuit layer is arranged on the lower surface of the metal column and the positions of the chip terminal windows and the metal column windows, and the heat dissipation layer is arranged on the back side of the chip and the positions of the chip front side heat dissipation windows. The packaging structure is compatible with heat dissipation and circuit design, can conduct double-sided conduction, facilitates integration application of double-sided conduction of a back manufacturing procedure or surface-mounted other devices, guarantees a heat dissipation effect, and reduces process difficulty and production cost.
Description
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a chip package structure and a method for manufacturing the same.
Technical Field
With the continuous development of microelectronic technology, the requirement for high-density packaging technology is higher and higher for realizing the integration and miniaturization of products, and the products are required to have smaller area and better heat dissipation while realizing the integration and miniaturization of products, so that higher requirements are provided for the circuit layout in the packaging body.
In the current circuit layout, heat dissipation and circuit communication are separately designed, heat dissipation is implemented by applying a large metal block on the back surface of a chip, or by superposing a heat dissipation block or a heat dissipation mechanism on the surface of a package in a post-processing procedure, and the light, thin and small products are realized by re-wiring a circuit on the front surface of the chip through layer increasing design, so that the overall process is complex and the cost is high.
Content of application
The present application is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the present application provides a chip package structure and a method for manufacturing the same, which are compatible with heat dissipation and circuit design, reduce process difficulty and production cost while ensuring heat dissipation effect, and achieve integration and miniaturization. This summary is not intended to limit the scope of the claims. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a method for manufacturing a chip package structure, including the following steps:
providing an organic frame, wherein the organic frame comprises metal columns and a core-embedded cavity;
attaching an adhesive tape to the lower surface of the organic frame to seal the bottom of the embedded core cavity, attaching a chip in the embedded core cavity to enable the front of the chip to be upward, and arranging a terminal for leading wires on the front of the chip;
laminating a dielectric layer to enable the dielectric layer to cover the upper surface of the organic frame and be filled in the embedded core cavity to cover the front surface and the peripheral surface of the chip;
the dielectric layer is subjected to graphical processing to form a plurality of chips with front heat dissipation windows, chip terminal windows and metal column windows, lower surface adhesive tapes are removed, graphical processing is carried out on the upper surface and the lower surface, deposited metal forms a circuit layer and a heat dissipation layer, the circuit layer is arranged on the lower surface of the metal column and the chip terminal windows and the metal column windows, and the heat dissipation layer is arranged on the back of the chip and the front heat dissipation windows of the chip.
According to the manufacturing method of the chip packaging structure of the embodiment of the first aspect of the application, at least the following beneficial effects are achieved: on the first hand, the application provides a double-sided conductive chip packaging structure with circuit layers on both sides, which can be used as an intermediate, and is convenient for integrated application of double-sided conduction of post-processing or surface-mounting of other devices and the like; in a second aspect, the chip packaging structure of the present application has heat dissipation layers on both sides, and the heat dissipation layers are combined with the circuit layer, so that the heat dissipation area of the chip can be greatly increased; in a third aspect, the heat dissipation layer and the circuit layer of the chip packaging structure can be manufactured by a synchronous process, so that the process steps and the production cost are reduced.
Optionally, in an embodiment of this application, the circuit layer includes circuit layer and circuit layer down, it sets up to go up the circuit layer the chip terminal windowing with the metal post department of windowing, with the positive terminal of chip with surface connection on the metal post, the circuit layer sets up down the metal post lower surface, through the circuit layer with the metal post can with the electrical characteristics of the positive terminal of chip leads to chip back one side.
Optionally, in an embodiment of the present application, the heat dissipation layer includes an upper heat dissipation layer and a lower heat dissipation layer, and the lower heat dissipation layer covers the back surface of the chip and is used for heat dissipation of the back surface of the chip; the upper heat dissipation layer is arranged at the front side heat dissipation windowing position of the chip and used for front side heat dissipation of the chip.
Optionally, in an embodiment of the present application, a metal seed layer is further formed, where the metal seed layer is disposed on the lower surfaces of the circuit layer and the heat dissipation layer.
Optionally, in an embodiment of the present application, the method further includes depositing a solder resist layer on upper and lower surfaces, and forming an electrode window of the circuit layer and the heat dissipation layer by photolithography on the solder resist layer.
Optionally, in an embodiment of the present application, the method further includes performing an anti-oxidation treatment on the surface of the electrode window to form a protective layer.
Optionally, in an embodiment of the present application, the protective layer material includes ni-pd-au, ni-au, sn, ag, an organic solderability preservative film.
Optionally, in an embodiment of the present application, the first dielectric layer is a photosensitive resin material and has fluidity.
In a second aspect, an embodiment of the present application provides a chip package structure, including:
an organic frame comprising metal pillars and a core-buried cavity;
the front surface of the chip is upwards arranged in the embedded core cavity, and the front surface of the chip is provided with a terminal;
the circuit layers are arranged on the upper surface and the lower surface of the metal column and at the front terminal of the chip and used for conducting electricity and dissipating heat;
and the heat dissipation layer is arranged at the back of the chip and the front non-terminal position of the chip and used for dissipating heat.
According to the chip packaging structure of the embodiment of the second aspect of the present application, at least the following advantages are provided: on the first hand, the application provides a double-sided circuit layer which can be used as a double-sided conductive chip packaging structure of an intermediate body, and is convenient for double-sided conduction of a post-processing procedure or surface-mounting of other devices and the like; in a second aspect, the chip packaging structure of the present application has heat dissipation layers on both sides, and the heat dissipation layers are combined with the circuit layer, so that the heat dissipation area of the chip can be greatly increased; in a third aspect, the heat dissipation layer and the circuit layer of the chip packaging structure can be manufactured by a synchronous process, so that the process steps and the production cost are reduced.
Optionally, in an embodiment of the present application, the heat dissipation device further includes a solder resist layer disposed between the circuit layer and the heat dissipation layer for insulating the circuit layer and the heat dissipation layer.
Optionally, in an embodiment of the present application, the heat dissipation layer further includes a protection layer disposed on the upper surfaces of the circuit layer and the heat dissipation layer to prevent the surfaces of the circuit layer and the heat dissipation layer from being oxidized.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the claimed subject matter and are incorporated in and constitute a part of this specification, illustrate embodiments of the subject matter and together with the description serve to explain the principles of the subject matter and not to limit the subject matter.
Fig. 1 is a flowchart illustrating steps of a method for fabricating a chip package structure according to an embodiment of the present disclosure;
fig. 2 to 8 are cross-sectional views of an intermediate state of a method for manufacturing a chip package structure according to another embodiment of the present application;
fig. 9 is a cross-sectional view of a chip package structure provided in another embodiment of the present application;
fig. 10 is a cross-sectional view of a chip package structure according to another embodiment of the present application.
Reference numerals:
the organic frame 100, the metal pillar 110, the embedded core cavity 120, the adhesive tape 600, the chip 200, the terminal 210, the dielectric layer 300, the chip front side heat dissipation window 310, the metal pillar window 320, the chip terminal window 330, the upper circuit layer 511, the lower circuit layer 512, the upper heat dissipation layer 521, the lower heat dissipation layer 522, the metal seed layer 700, the solder mask layer 800, the electrode window 810, the protective layer 900 and the photosensitive barrier layer 1000.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the embodiments described herein are merely illustrative and not restrictive, and therefore do not represent any changes in the technical spirit, structure, proportion, or size which may occur or which may not affect the performance or objectives achieved thereby, and are intended to be covered by the teachings herein.
Reference will now be made in detail to the present embodiments of the present application, preferred embodiments of which are illustrated in the accompanying drawings, which are for the purpose of visually supplementing the description with figures and detailed description, so as to enable a person skilled in the art to visually and visually understand each and every feature and technical solution of the present application, but not to limit the scope of the present application.
In the description of the present application, the meaning of a plurality is one or more, the meaning of a plurality is two or more, and larger, smaller, larger, etc. are understood as excluding the present number, and larger, smaller, inner, etc. are understood as including the present number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
Referring to fig. 1 to 8, a method for manufacturing a chip package structure according to an embodiment of the present disclosure includes the following steps:
step S100, providing an organic frame 100, wherein the organic frame 100 comprises a metal column 110 and a core embedding cavity 120; specifically, as shown in fig. 2, an embedded frame composed of an organic medium and a metal is provided, the frame has an upper surface and a lower surface opposite to the upper surface, at least one conductive metal pillar 110, specifically a conductive copper pillar, and embedded core cavities 120 arranged in an array according to the size of an embedded chip 200 or a device, the number of the embedded core cavities 120 may be designed to be at least one according to actual requirements, it should be noted that the distribution of the embedded core cavities 120 may be regular array distribution or irregular distribution, in this embodiment, the description is given by taking the array distribution of two embedded core cavities 120 as an example. The thickness of the organic frame 100 is generally within 100-500um, and the specific thickness is set according to the thickness of the embedded chip 200 or device, and the thickness is generally set to be greater than the maximum thickness of the chip 200 or device 10-60 um.
Step S200, attaching an adhesive tape 600 to the lower surface of the organic frame 100 to seal the bottom of the embedded core cavity 120, attaching the chip 200 in the embedded core cavity 120 to enable the front surface of the chip 200 to be arranged upwards, and arranging a terminal 210 for leading on the front surface of the chip 200; specifically, as shown in fig. 3, first, a tape 600 is laminated on the lower surface or the upper surface of the organic frame 100 to seal one side of the organic frame 100; attaching the chip 200 or device to the sealing side of the organic frame 100, so that the front side of the chip 200 or device faces upward, and the back side contacts the adhesive tape 600, it should be noted that the chip 200 or device is divided into front and back sides according to whether there is a lead terminal, that is, the terminal surface is the front side of the chip 200 or device, the upward or downward placement of the chip 200 or device can be adjusted according to the actual situation, the chip 200 or device at least includes one active component, which may be an active component, or a combination of an active component and a passive component, and the attaching pressure of attaching the chip 200 or device is generally 0.5-5N.
Step S300, laminating a dielectric layer 300, so that the dielectric layer 300 covers the upper surface of the organic frame 100 and is filled in the core-embedded cavity 120 to cover the front surface and the peripheral surface of the chip 200; specifically, as shown in fig. 4, a dielectric layer 300, specifically an organic dielectric material, is laminated from the upper surface of the organic frame 100 to the lower surface, and is pre-cured, in order to ensure the filling effect, the organic dielectric material is at least 5um higher than the organic frame 100, it should be noted that the dielectric layer 300 material includes epoxy resin (ABF), polypropylene (PP), and photosensitive dielectric material (PID), wherein the photosensitive dielectric material (PID) has fluidity before being uncured, and can better cover the exposed portions of the machine frame 100 and the embedded cavity 120, and therefore in some embodiments of the present application, it is preferable to use the photosensitive dielectric material (PID) as the first dielectric layer 300.
Step S400, carrying out graphical processing on the dielectric layer 300 to form a plurality of chip front side heat dissipation windows 310, chip terminal windows 330 and metal column windows 320, removing the adhesive tape 600 on the lower surface, carrying out graphical processing on the upper surface and the lower surface, and electroplating metal to form a circuit layer and a heat dissipation layer, wherein the circuit layer is arranged on the lower surface of the metal column 110, the chip terminal windows (330) and the metal column windows 320, and the heat dissipation layer is arranged on the back side of the chip 200 and the chip front side heat dissipation windows 310; specifically, as shown in fig. 5, a photolithography process is performed on the dielectric layer 300, specifically, a photosensitive dielectric material (PID) is exposed and developed to expose a chip front side heat dissipation window 310, a chip terminal window 330, and a metal column window 320, where one metal column 110 corresponds to one metal column window 320, one terminal on the front side of the chip corresponds to one chip terminal window 330, and a plurality of chip front side heat dissipation windows 310 are correspondingly formed at a front side non-terminal position of one chip 200, and the plurality of chip front side heat dissipation windows 310 may perform subsequent layout and wiring according to an actual area of the chip front side non-terminal position, so as to achieve heat dissipation. Thermally curing the dielectric layer 300 after each window is formed; as shown in fig. 6, the adhesive tape 600 at the bottom of the organic frame 100 is removed to expose the lower surface of the metal pillar 110, and a metal seed layer 700 is formed on the surface of the dielectric layer 300 and the lower surface of the organic frame 100 by chemical plating or physical sputtering, wherein the metal seed layer 700 is formed by covering the entire surface of the dielectric layer 300 and the lower surface of the organic frame 100, and the common metal seed layer 700 material includes metal titanium, metal copper, titanium-tungsten alloy, and the like, but is not limited to the above materials, and the thickness of the metal seed layer 700 is generally 0.8-5 um. In some embodiments of the present application, it is preferable to deposit two layers of 0.1um thick titanium and 1um thick copper as the metal seed layer 700 by physical sputtering; as shown in fig. 7, attaching a photosensitive barrier layer 1000, specifically a photoresist, to the metal seed layer 700 on the upper surface and the lower surface, performing a graphic imaging process on the photosensitive barrier layer 1000, and developing to expose the corresponding graphics of the circuit layer and the heat dissipation layer, where it is noted that the corresponding graphics of the circuit layer and the heat dissipation layer on the upper surface of the organic frame are consistent with the positions of the heat dissipation window 310 on the front surface of the chip, the chip terminal window 330 and the metal pillar window 320, and the corresponding graphics of the circuit layer and the heat dissipation layer on the lower surface of the organic frame are consistent with the positions of the back surface of the chip 200 and the metal pillar 110, so as to deposit metal at each window position and form subsequent metal communication between the upper surface and the lower surface; as shown in fig. 8, depositing metal, specifically, electroplating metal copper, to form a circuit layer and a heat dissipation layer, where the circuit layer includes an upper circuit layer 511 and a lower circuit layer 512, where the upper circuit layer 511 is disposed at the chip terminal windowing 330 and the metal pillar windowing 320, and is connected to the terminal 210 on the front side of the chip and the upper surface of the metal pillar 110, and the lower circuit layer 512 is disposed on the lower surface of the metal pillar 110, and the electrical characteristics of the terminal 210 on the front side of the chip 200 can be introduced to the lower circuit layer on the back side of the chip 200 through the upper circuit layer 511, the lower circuit layer 512 and the metal pillar 110, so as to implement double-sided conduction, facilitate double-sided conduction in a post-process or surface-mount other devices, and improve the usage rate; the heat dissipation layer comprises an upper heat dissipation layer 521 and a lower heat dissipation layer 522, the lower heat dissipation layer 522 covers the back of the chip 200 and is used for heat dissipation of the back of the chip 200, the upper heat dissipation layer 521 is arranged at the position of the heat dissipation window 310 on the front of the chip and is used for heat dissipation of the front of the chip 200, no additional process step is added by arranging the heat dissipation layer at the position of a non-terminal on the front of the chip 200, the packaging space is fully utilized, and the overall heat dissipation efficiency of the chip 200 is improved; as shown in fig. 9, the film stripping process removes the photosensitive barrier layer 1000, specifically, removes the photoresist, and etches the metal seed layer 700, so that the metal seed layer 700 is consistent with the circuit layer and the heat dissipation layer, and the adhesion and the electrical conduction characteristic of the connection between the metal on the upper side and the metal on the lower side of the metal seed layer 700 can be enhanced by the metal seed layer 700.
In some embodiments of the present application, the method further includes depositing a solder mask layer 800 on the upper and lower surfaces, and lithographically forming electrode windows 810 of the circuit layer and the heat dissipation layer on the solder mask layer 800, specifically, as shown in fig. 10, depositing the solder mask layer 800 on both the upper and lower surfaces, and patterning the solder mask layer 800 to expose the circuit layer and the heat dissipation layer, where the solder mask layer 800 serves as an insulation layer for electrically isolating the circuit layer and the heat dissipation layer, and thus, electrical independence between the chips 200 or devices is achieved.
In some embodiments of the present application, the method further comprises performing an oxidation resistant treatment on the surface of the electrode window 810 to form a protective layer 900. The protective layer 900 may prevent oxidation of the metal of the electrode window 810 by covering the protective layer 900, thereby enhancing reliability, and the protective layer 900 may perform surface treatment by depositing chemically stable metals such as ni-pd-au, ni-au, sn, and ag, and further include covering the electrode window with an organic solder mask.
Based on the above chip package structure manufacturing method, various embodiments of the chip package structure of the present application are provided.
Referring to fig. 9, another embodiment of the present application further provides a chip package structure, including an organic frame 100, the organic frame 100 including a metal pillar 110 and a core-buried cavity 120; a chip 200 disposed inside the core-embedded cavity 120 with its front surface facing upward, the front surface of the chip being provided with a terminal 210; circuit layers disposed on the upper and lower surfaces of the metal posts 110 and the front terminals 210 of the chip 200 for conducting and dissipating heat; and the heat dissipation layer is arranged at the back surface of the chip 200 and the front surface of the chip 200, which are not terminals, and is used for dissipating heat.
In an embodiment, the chip 200 or the device is mounted in the embedded cavity 120 preset in the organic frame 100, the chip 200 is disposed with the front side facing upward and the back side facing downward, the front side of the chip 200 includes the terminal 210 for a lead, the terminal 210 is connected to the circuit layer on the upper surface of the organic frame 100 and is connected to the circuit layer on the lower surface through the metal pillar 110, so as to lead the electrical circuit of the chip 200 from the front side to the back side, thereby realizing the double-sided electrical characteristic, and in the subsequent connection or packaging, the double-sided connection can be realized as an intermediate, thereby increasing the practicability, and in addition, heat dissipation layers are respectively disposed at the back side of the chip 200 and the front side non-terminal of the chip 200, wherein the heat dissipation layer at the back side of the chip 200 covers the back side of the chip 200 to perform the back side heat dissipation function, and the heat dissipation layer is disposed at the.
It should be noted that the heat dissipation layer on the front side of the chip may be a continuous metal layer, or may be a plurality of discontinuous smaller-area partition metal layers, where the continuous metal layer may increase the heat dissipation area to provide better heat dissipation, and the discontinuous plurality of smaller-area partition metal layers may better release the stress of the chip 200, reduce the stress caused by the difference in thermal expansion coefficients between the organic frame 100 and the chip 200, and improve the reliability of the product, and the heat dissipation layer may be formed by a synchronous process with the circuit layer, without additionally increasing the process for forming the heat dissipation layer, which may reduce the process complexity and the production cost; the heat dissipation layer and the circuit layer on the front surface of the chip 200 are limited to the position corresponding to the front surface size of the chip 200, extra circuits are not added, the density of packaged circuits is crowded, the heat dissipation layer and the circuit layer can be flexibly arranged according to the terminal position and the chip area of the chip 200, external connection and wiring are facilitated, and the integrated circuit is more integrated.
Referring to fig. 10, in one embodiment provided by the present application, a solder mask layer 800 is further included and disposed between the circuit layer and the heat dissipation layer for insulating the circuit layer and the heat dissipation layer, and in one embodiment, the solder mask layer 800 is disposed on both the upper surface and the lower surface, and the solder mask layer 800 serves as an insulation for electrically isolating the circuit layer and the heat dissipation layer, so as to realize electrical independence between the chips 200 or devices.
Referring to fig. 10, in one embodiment provided by the present application, a protection layer 900 is further included and is disposed on the upper surfaces of the circuit layer and the heat dissipation layer to prevent the surfaces of the circuit layer and the heat dissipation layer from being oxidized. In one embodiment, the passivation layer 900 can prevent oxidation of metal exposed outside or the heat dissipation layer, so as to enhance the reliability of the product, and the passivation layer 900 can be formed by depositing chemically stable metals such as ni-pd-au, ni-au, sn, and ag, and further includes a surface treatment covered with an organic solder mask.
The structure in the embodiment of the present application is only a product example, the product in the embodiment of the present application is not limited to a single layer, and a multilayer build-up design can be performed according to the requirement of an actual design, all of which belong to the protection scope of the present application.
While the preferred embodiments of the present invention have been described, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and such equivalent modifications or substitutions are included in the scope of the present invention defined by the claims.
Claims (11)
1. A chip packaging structure manufacturing method is characterized by comprising the following steps:
providing an organic frame, wherein the organic frame comprises metal columns and a core-embedded cavity;
attaching an adhesive tape to the lower surface of the organic frame to seal the bottom of the embedded core cavity, attaching a chip in the embedded core cavity to enable the front of the chip to be upward, and arranging a terminal for leading wires on the front of the chip;
laminating a dielectric layer to enable the dielectric layer to cover the upper surface of the organic frame and be filled in the embedded core cavity to cover the front surface and the peripheral surface of the chip;
the dielectric layer is subjected to graphical processing to form a plurality of chips with front heat dissipation windows, chip terminal windows and metal column windows, lower surface adhesive tapes are removed, graphical processing is carried out on the upper surface and the lower surface, deposited metal forms a circuit layer and a heat dissipation layer, the circuit layer is arranged on the lower surface of the metal column and the chip terminal windows and the metal column windows, and the heat dissipation layer is arranged on the back of the chip and the front heat dissipation windows of the chip.
2. The method for manufacturing a chip package structure according to claim 1, wherein: the circuit layer includes last circuit layer and circuit layer down, it sets up to go up the circuit layer the chip terminal windowing with the metal post department of windowing, with the positive terminal of chip with surface connection on the metal post, the circuit layer sets up down the metal post lower surface, through the circuit layer with the metal post can with the electric characteristic of the positive terminal of chip leads to chip back one side.
3. The method for manufacturing a chip package structure according to claim 1, wherein: the heat dissipation layer comprises an upper heat dissipation layer and a lower heat dissipation layer, and the lower heat dissipation layer covers the back of the chip and is used for dissipating heat from the back of the chip; the upper heat dissipation layer is arranged at the front side heat dissipation windowing position of the chip and used for front side heat dissipation of the chip.
4. The method for manufacturing a chip package structure according to claim 1, wherein: the method further comprises the step of forming a metal seed layer, wherein the metal seed layer is arranged on the lower surfaces of the circuit layer and the heat dissipation layer.
5. The method for manufacturing a chip package structure according to claim 1, wherein: and depositing a solder mask on the upper surface and the lower surface, and photoetching the solder mask to form the electrode windows of the circuit layer and the heat dissipation layer.
6. The method for manufacturing a chip package structure according to claim 5, wherein: and performing anti-oxidation treatment on the surface of the electrode window to form a protective layer.
7. The method for manufacturing a chip package structure according to claim 6, wherein: the protective layer material comprises nickel-palladium-gold, nickel-gold, tin, silver and an organic solderability preservative film.
8. The method for manufacturing a chip package structure according to claim 1, wherein: the medium layer is made of photosensitive resin material and has fluidity.
9. A chip package structure, comprising:
an organic frame comprising metal pillars and a core-buried cavity;
the front surface of the chip is upwards arranged in the embedded core cavity, and the front surface of the chip is provided with a terminal;
the circuit layers comprise an upper circuit layer and a lower circuit layer, are arranged on the upper surface and the lower surface of the metal column and at the front terminal of the chip and are used for conducting electricity and dissipating heat;
and the heat dissipation layer comprises an upper heat dissipation layer and a lower heat dissipation layer, is arranged on the back surface of the chip and on the front surface of the chip, which is not provided with a terminal and is used for dissipating heat.
10. The chip package structure according to claim 9, further comprising a solder resist layer disposed between the wiring layer and the heat dissipation layer for insulating the wiring layer and the heat dissipation layer.
11. The chip package structure according to claim 9, further comprising a protection layer disposed on the upper surfaces of the circuit layer and the heat dissipation layer for preventing the surfaces of the circuit layer and the heat dissipation layer from being oxidized.
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| US20080211079A1 (en) * | 2006-12-27 | 2008-09-04 | Masanori Onodera | Heat dissipation methods and structures for semiconductor device |
| CN102456636A (en) * | 2010-10-19 | 2012-05-16 | 矽品精密工业股份有限公司 | Package of embedded chip and manufacturing method thereof |
| CN103035591A (en) * | 2012-12-28 | 2013-04-10 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation piece and manufacturing method thereof |
| CN111463178A (en) * | 2020-06-22 | 2020-07-28 | 珠海越亚半导体股份有限公司 | Heat dissipation embedding packaging method |
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2020
- 2020-08-07 CN CN202010788908.9A patent/CN112103192B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080211079A1 (en) * | 2006-12-27 | 2008-09-04 | Masanori Onodera | Heat dissipation methods and structures for semiconductor device |
| CN102456636A (en) * | 2010-10-19 | 2012-05-16 | 矽品精密工业股份有限公司 | Package of embedded chip and manufacturing method thereof |
| CN103035591A (en) * | 2012-12-28 | 2013-04-10 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation piece and manufacturing method thereof |
| CN111463178A (en) * | 2020-06-22 | 2020-07-28 | 珠海越亚半导体股份有限公司 | Heat dissipation embedding packaging method |
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