CN112100014A - Passive wireless communication chip verification platform, construction method and chip verification method - Google Patents
Passive wireless communication chip verification platform, construction method and chip verification method Download PDFInfo
- Publication number
- CN112100014A CN112100014A CN202011290063.7A CN202011290063A CN112100014A CN 112100014 A CN112100014 A CN 112100014A CN 202011290063 A CN202011290063 A CN 202011290063A CN 112100014 A CN112100014 A CN 112100014A
- Authority
- CN
- China
- Prior art keywords
- verification
- wireless communication
- sequence
- communication chip
- passive wireless
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3457—Performance evaluation by simulation
Abstract
The invention provides a passive wireless communication chip verification platform, a construction method and a chip verification method. The passive wireless communication chip verification platform comprises: the system comprises a sequence unit, a verification unit and a verification unit, wherein the sequence unit is used for providing a three-layer verification sequence for the verification of a passive wireless communication chip; the verification top-layer unit is used for establishing signal connection between the test interface and the tested passive wireless communication chip and starting simulation verification; the environment layer unit is used for sending a target verification sequence to the passive wireless communication chip to be tested after the simulation verification is started, and comparing and scoring a response result to obtain a verification result; and the test interface is used for connecting the tested passive wireless communication chip. The verification platform is simple in structure and high in operation efficiency, the verification quality and the verification efficiency of the passive wireless communication chip can be effectively improved, the three-layer verification sequence provided by the sequence unit can be combined and called according to different verified chips and different environments, the part is not required to be written repeatedly, and the writing efficiency of the verification sequence is improved.
Description
Technical Field
The invention relates to the field of chip verification testing, in particular to a passive wireless communication chip verification platform based on UVM, a passive wireless communication chip verification platform construction method based on UVM and a passive wireless communication chip verification platform chip verification method based on UVM.
Background
With the progress of society and the development of chip technology, passive wireless communication chips are more and more widely applied in the fields of industrial internet, article tracking, information acquisition and the like. The passive wireless communication chip generally has the characteristics of multiple commands, multiple states and large memory capacity, and the characteristics lead the chip to have diversified scenes during verification, thereby increasing the complexity of verification. Simulation verification plays an important role in the whole chip front-end process, can improve and guarantee the product quality, but can indirectly influence the overall product appearance time, and how to improve the verification efficiency to shorten the verification time is a key concern of the verification of the passive wireless communication chip.
A traditional simulation verification platform is built by using a Verilog language, only a direct excitation mode can be adopted, a large number of test cases need to be constructed, and the problem of incompleteness of verification scenes is easy to occur. UVM (Universal Verification Methodology) is a Universal Verification platform development framework mainly based on a SystemVerilog class library, which is introduced by the account standards organization and is fully supported by three major main stream EDA (Electronic design automation) suppliers. The UVM platform architecture is mainly composed of universal verification components UVC, each UVC is a verification environment component which is complete in function, configurable, packaged and reusable, and therefore a foundation is provided for building an efficient, automatic and reusable verification platform.
At present, some technical schemes are based on communication chips or communication module verification platforms of standard UVM architectures, and compared with verification platforms built by Verilog language, the verification platform has the attributes of automation, portability, random constraint and the like, and can improve verification efficiency and platform reusability to a certain extent. However, a verification platform based on UVM is not established aiming at the characteristics of multiple commands, multiple states and large memory capacity of the passive wireless communication chip, and further improvement of verification efficiency of the passive wireless communication chip is limited.
The existing verification platform based on UVM has the following problems when a passive wireless communication chip is verified:
1. the passive wireless communication chip generally has various instructions, various states and various scene combinations, thereby bringing difficulty to the generation of sequences. When it is necessary to verify whether the processing of each instruction in several different states is correct, the conventional verification platform needs to enter the state first and then send the instruction each time. And the user re-enters the next state to send the command again, so that the work of entering a part of the repeated writing state is caused, and the efficiency of excitation writing is reduced.
2. In the standard UVM architecture, the sending and receiving components are two base classes of UVM _ driver and UVM _ monitor, which are inherited respectively. With this structure, it is necessary to add a process of establishing association between transmission and reception of data packets in the verification environment, that is, the transmission driver needs to determine whether it is necessary to receive returned data according to different commands. Such processing can increase the complexity of the environment.
Disclosure of Invention
The verification platform is simple in structure, high in operation efficiency and reusability, verification quality and verification efficiency of the passive wireless communication chip can be effectively improved, a three-layer verification sequence provided by a sequence unit can be combined and called according to different verified chips and different environments, a part is not required to be written repeatedly, and writing efficiency of the verification sequence is improved. The verification platform construction method disclosed by the invention can effectively improve the compiling efficiency of the verification sequence, and the drive-receiver adopting a feedback mechanism can realize the task of sending a card reader command to the tested passive wireless communication chip and receiving a response frame without adding an additional receiver. The chip verification method is simple and high in verification sequence compiling efficiency.
In order to achieve the above object, a first aspect of the present invention provides a passive wireless communication chip verification platform based on UVM, including:
the system comprises a sequence unit, a verification unit and a verification unit, wherein the sequence unit is used for providing a three-layer verification sequence for the verification of a passive wireless communication chip;
the verification top-layer unit is used for establishing signal connection between the test interface and the tested passive wireless communication chip and starting simulation verification;
the environment layer unit is used for sending a target verification sequence to the tested passive wireless communication chip after starting the simulation verification, and performing response result comparison and scoring to obtain a verification result; and
and the test interface is used for connecting the passive wireless communication chip to be tested. A passive wireless communication chip verification platform comprising the units is built according to a standard UVM library, the platform is simple and flexible, and various requirements of the passive wireless communication chip can be met.
Optionally, the three-layer verification sequence includes:
defining a first-layer basic sequence of common attributes and methods of all verification sequences;
randomly constraining the second layer command sequence, the second layer state sequence and the second layer specific parameter sequence of different scenes based on the first layer basic sequence expansion; and
and a third layer function point sequence which realizes different functions under different scenes and is obtained based on the second layer command sequence, the second layer state sequence or the second layer specific parameter sequence expansion. According to the requirements of a passive wireless communication chip, different three-layer sequences are divided by adopting a layering idea, and the sequences are mutually combined and called to meet the verification requirements of complex scenes.
Optionally, the environment layer unit includes:
the reader agent module is used for sending a target verification sequence to the passive wireless communication chip to be tested after the simulation verification is started, receiving a response frame returned by the passive wireless communication chip to be tested, generating a feedback variable packet and transmitting the feedback variable packet to the score board module; and
and the score board module is used for analyzing the feedback variable packet to obtain an actual response result, and comparing and scoring the actual response result and an expected response result to obtain the verification result.
Further, the reader agent module includes:
the sequence generator is used for generating a reader-writer command according to the target verification sequence and issuing the reader-writer command to the drive-receiver;
the drive-receiver is used for sending the reader-writer command to the tested passive wireless communication chip and receiving a response frame returned by the tested passive wireless communication chip to generate a feedback variable packet;
the monitor is used for detecting whether the response parameters of the passive wireless communication chip to be detected are correct or not; and
and the functional coverage rate counting component is used for counting the functional coverage rate of the reader-writer command on the tested passive wireless communication chip according to the response parameters. The drive-receiver adopting the feedback mechanism can realize the task of sending the card reader command to the tested passive wireless communication chip and receiving the response frame without adding an additional receiver, thereby avoiding the increase of the processing of establishing the association of sending and receiving data packets in the verification environment and reducing the complexity of the verification environment.
Optionally, the reader agent module further includes:
and the configuration component is used for configuring the parameters of the reader-writer command.
Further, the scoreboard module includes:
the feedback variable packet analysis module is used for analyzing the feedback variable packet to obtain an actual response result;
the conversion function module is used for converting the target verification sequence into an expected response result;
and the comparison function module is used for comparing and scoring the actual response result and the expected response result to obtain the verification result. The score counting board comprises a conversion function module, can realize the conversion of a target verification sequence, does not need to write the expected response result of each verification case in the verification case, reduces the complexity of writing the verification case, and is easy to realize the transplantation and reuse of the verification case in a new project.
Optionally, the score board module further includes:
the first analysis port is used for accessing the target verification sequence and transmitting the target verification sequence to the reader agent module and the transfer function module;
and the second analysis port is used for transmitting the feedback variable packet to the feedback variable packet analysis module.
The invention provides a method for constructing a passive wireless communication chip verification platform based on UVM, which comprises the following steps:
defining a transaction-level data structure;
constructing a three-layer verification sequence according to a defined transaction-level data structure and the attribute of the verification sequence;
a reader agent module is constructed by adopting a driving-receiving device of a feedback mechanism, and the reader agent module is used for sending a target verification sequence to a tested passive wireless communication chip after starting simulation verification, receiving a response frame returned by the tested passive wireless communication chip, generating a feedback variable packet and transmitting the feedback variable packet to a score board module;
constructing an automatic comparison scoring board module, wherein the scoring board module is used for analyzing the feedback variable packet to obtain an actual response result, and comparing and scoring the actual response result and an expected response result to obtain a verification result;
and constructing a functional coverage rate counting component, wherein the functional coverage rate counting component is used for counting the functional coverage rate of the reader-writer command on the tested passive wireless communication chip. The verification sequence is compiled according to the transaction-level data structure and the attribute of the verification sequence, the compiling efficiency of the verification sequence can be effectively improved, the drive-receiver adopting a feedback mechanism can realize the task of sending a card reader command to the tested passive wireless communication chip and receiving a response frame, and an additional receiver is not required to be added.
Further, the defining a transaction-level data structure includes:
parameters in the environment are defined in the form of aggregation parameters, and meanwhile, a sending frame and a response frame are defined as a transaction;
defining a general data domain and a private data domain of each transaction according to the characteristics of the transactions;
defining the randomization performance of each data field;
a reservation switch defining each data field;
the function of the data field is defined to conform to the field _ automation mechanism. Parameters in the environment are defined in an aggregation parameter mode, so that the verification environment is simpler and clearer.
Further, the constructing a three-tier authentication sequence according to the defined transaction-level data structure and the attributes of the authentication sequence includes:
setting a first layer basic sequence for defining common attributes and methods of all verification sequences;
according to the first layer basic sequence expansion, a second layer command sequence, a second layer state sequence and a second layer specific parameter sequence which are randomly constrained into different scenes are obtained;
and expanding the second layer command sequence, the second layer state sequence or the second layer specific parameter sequence to obtain a third layer function point sequence for realizing different functions under different scenes. According to the requirements of a passive wireless communication chip, different three-layer sequences are divided by adopting a layering idea, and the sequences are mutually combined and called to meet the verification requirements of complex scenes.
The third aspect of the present invention provides a method for verifying a chip by a passive wireless communication chip verification platform based on UVM, where the method includes:
establishing signal connection between a test interface and a tested passive wireless communication chip;
setting a target verification sequence according to the tested passive wireless communication chip;
sending the target verification sequence to the tested passive wireless communication chip, and receiving a response frame of the tested passive wireless communication chip to generate a feedback variable packet;
and comparing the actual response result with the expected response result in the feedback variable packet to obtain a verification result. The verification method is simple and the verification sequence compiling efficiency is high. The method does not need to repeatedly write the state into the part, and improves the efficiency of verifying the sequence writing.
Further, the sending the target verification sequence to the passive wireless communication chip under test and receiving a response frame of the passive wireless communication chip under test includes:
1) the driver-receiver requests a reader command packet from the sequencer, the reader command packet being generated by the sequencer invoking a target verification sequence from a sequence unit;
2) the driver-receiver judges a communication protocol according to a first command received by a test interface, and sends the reader-writer command packet to a passive wireless communication chip to be tested through the test interface according to a format specified by the communication protocol;
3) the driving-receiving unit receives response frame data returned by the tested passive wireless communication chip, and copies the ID information of the request variable in the response frame data to a feedback variable to generate a feedback variable packet;
4) the reader-writer commands the execution to end, and returns the ID information of the request variable to the sequencer. The drive-receiver adopting the feedback mechanism can realize the task of sending the card reader command to the tested passive wireless communication chip and receiving the response frame without adding an additional receiver, thereby avoiding the increase of the processing of establishing the association of sending and receiving data packets in the verification environment and reducing the complexity of the verification environment.
Further, the comparing the actual response result in the feedback variable packet with the expected response result to obtain a verification result includes:
converting, by a conversion function module, the target verification sequence into an expected response result;
analyzing the feedback variable by a feedback variable packet analysis module to obtain an actual response result;
and comparing and scoring the actual response result and the expected response result by a comparison function module to obtain the verification result. The conversion of the target verification sequence is realized through the conversion function module, the expected response result of each verification case does not need to be written in the verification case, the complexity of writing the verification case is reduced, and the transplantation and reuse of the verification case in a new project are easy to realize.
Optionally, the method further includes:
detecting whether the response parameters of the passive wireless communication chip to be detected are correct or not by a monitor; and
and counting the functional coverage rate of the reader-writer command on the tested passive wireless communication chip by a functional coverage rate counting component according to the response parameter.
Further, the functional coverage includes a functional coverage of the timing parameter attribute and a functional coverage of the command information. The function coverage rate statistics is the key for completing closed-loop verification, and the verification quality can be ensured only by a complete coverage rate statistical model.
Through the technical scheme, the verification platform for the passive wireless communication chip is simple in structure, high in operation efficiency and high in reusability, the verification quality and the verification efficiency of the passive wireless communication chip can be effectively improved, the three-layer verification sequence provided by the sequence unit can be combined and called according to different verified chips and different environments, the state entering part does not need to be written repeatedly, and the verification sequence writing efficiency is improved.
The verification platform construction method disclosed by the invention can effectively improve the compiling efficiency of the verification sequence, and the drive-receiver adopting a feedback mechanism can realize the task of sending a card reader command to the tested passive wireless communication chip and receiving a response frame without adding an additional receiver.
The chip verification method is simple and high in verification sequence compiling efficiency.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a block diagram of a passive wireless communication chip verification platform based on UVM according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a three-layer verification sequence structure provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram of the working principle of the scoreboard according to an embodiment of the present invention;
fig. 4 is a flowchart of a UVM-based passive wireless communication chip verification platform construction method according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for verifying a chip by a UVM-based passive wireless communication chip verification platform according to an embodiment of the present invention;
fig. 6 is a schematic diagram of the operation of the driving-receiving unit according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a block diagram of a passive wireless communication chip verification platform based on UVM according to an embodiment of the present invention. As shown in fig. 1, the verification platform includes:
a sequence unit (sequence) for providing a three-layer authentication sequence for passive wireless communication chip authentication;
the verification top-layer unit is used for establishing signal connection between a test interface (interface) and a tested passive wireless communication chip (DUT) and calling a run _ test function to start simulation verification;
the environment layer unit is used for sending a target verification sequence to the tested passive wireless communication chip after starting the simulation verification, and performing response result comparison and scoring to obtain a verification result; and
and the test interface is used for connecting the passive wireless communication chip to be tested. A passive wireless communication chip verification platform comprising the units is built according to a standard UVM library, the platform is simple and flexible, and various requirements of the passive wireless communication chip can be met.
Optionally, the three-layer verification sequence includes:
defining a first-layer basic sequence of common attributes and methods of all verification sequences;
randomly constraining the second layer command sequence, the second layer state sequence and the second layer specific parameter sequence of different scenes based on the first layer basic sequence expansion; and
and a third layer function point sequence which realizes different functions under different scenes and is obtained based on the second layer command sequence, the second layer state sequence or the second layer specific parameter sequence expansion. The sequence structure is shown in FIG. 2. According to the requirements of a passive wireless communication chip, different three-layer sequences are divided by adopting a layering idea, and the sequences are mutually combined and called to meet the verification requirements of complex scenes.
Optionally, the environment layer unit includes:
a Reader agent (Reader _ agent) module, configured to send a target verification sequence to the passive wireless communication chip to be tested after the simulation verification is started, and receive a response frame returned by the passive wireless communication chip to generate a feedback variable packet, which is transmitted to the score board module to simulate a behavior of a passive wireless communication chip Reader; and
and the score board (scoreboard) module is used for analyzing the response frame to obtain an actual response result, and comparing and scoring the actual response result and an expected response result to obtain the verification result.
Further, the reader agent module includes:
a sequence generator (sequencer) for generating a reader/writer command according to the target verification sequence and issuing the reader/writer command to the driver/receiver;
the drive-receiver (Dev _ Rcv) is used for sending the reader-writer command to the tested passive wireless communication chip and receiving a response frame returned by the tested passive wireless communication chip to generate a feedback variable packet;
a monitor (monitor) for detecting whether the response parameters of the passive wireless communication chip under test are correct, such as the response time, the BLF error and other parameters; and
and a functional coverage rate counting (Func _ cov) component for counting the functional coverage rate of the reader command on the passive wireless communication chip to be tested according to the response parameter. The function coverage rate mainly comprises a function coverage rate of the time sequence parameter attribute and a function coverage rate of the command information. The checking of the timing parameter attribute mainly comprises the coverage rate statistics of each timing parameter specified by the communication protocol. The functional coverage statistics of the command information mainly comprises statistics of data such as command codes, states, error codes, cyclic redundancy check and the like. The function coverage rate statistics is the key for completing closed-loop verification, and the verification quality can be ensured only by a complete coverage rate statistical model.
The drive-receiver adopting the feedback mechanism can realize the task of sending the card reader command to the tested passive wireless communication chip and receiving the response frame without adding an additional receiver, thereby avoiding the increase of the processing of establishing the association of sending and receiving data packets in the verification environment and reducing the complexity of the verification environment.
Optionally, the reader agent module further includes:
a configuration component (config) for configuring parameters of the reader command.
Further, the scoreboard module includes:
the feedback variable packet analysis module is used for analyzing the feedback variable packet to obtain an actual response result;
the conversion function module is used for converting the target verification sequence into an expected response result;
and the comparison function module is used for comparing and scoring the actual response result and the expected response result to obtain a verification result. The score counting board comprises a conversion function module, can realize the conversion of a target verification sequence, does not need to write the expected response result of each verification case in the verification case, reduces the complexity of writing the verification case, and is easy to realize the transplantation and reuse of the verification case in a new project.
Optionally, the score board module further includes:
the first analysis port is used for accessing a target verification sequence and transmitting the target verification sequence to the reader agent module and the transfer function module;
and the second analysis port is used for transmitting the feedback variable packet to the feedback variable packet analysis module.
As shown in fig. 3, which is a schematic diagram of the scoreboard operation, in the operation process of the scoreboard module, the first analysis port accesses the target verification sequence and transmits the target verification sequence to the conversion function module in the driver-receiver and the scoreboard module, the driver-receiver transmits the target verification sequence to the passive wireless communication chip to be tested, the passive wireless communication chip to be tested returns a response frame to the driver-receiver and the monitor, the driver-receiver returns a feedback variable packet to the feedback variable packet analysis module in the scoreboard module through the second analysis port, the feedback variable packet analysis module analyzes the feedback variable packet to obtain an actual response result, the conversion function module includes a reference model of the response command of the passive wireless communication chip to be tested, and the model simulates the behavior and state of the passive wireless communication chip to be tested under the action of the target verification sequence to obtain an expected response result, and the comparison function module compares and scores the actual response result and the expected response result, if the response results are inconsistent, the verification platform automatically reports an error, and the verification of the tested passive wireless communication chip fails.
Fig. 4 is a flowchart of a method for constructing a passive wireless communication chip verification platform based on UVM according to an embodiment of the present invention. As shown in fig. 4, the method includes:
defining a transaction-level data structure;
constructing a three-layer verification sequence according to a defined transaction-level data structure and the attribute of the verification sequence;
a reader agent module is constructed by adopting a driving-receiving device of a feedback mechanism, and the reader agent module is used for sending a target verification sequence to a tested passive wireless communication chip after starting simulation verification, receiving a response frame returned by the tested passive wireless communication chip, generating a feedback variable packet and transmitting the feedback variable packet to a score board module;
constructing an automatic comparison scoring board module, wherein the scoring board module is used for analyzing the feedback variable packet to obtain an actual response result, and comparing and scoring the actual response result and an expected response result to obtain a verification result;
and constructing a functional coverage rate counting component, wherein the functional coverage rate counting component is used for counting the functional coverage rate of the reader-writer command on the tested passive wireless communication chip. The verification sequence is compiled according to the transaction-level data structure and the attribute of the verification sequence, the compiling efficiency of the verification sequence can be effectively improved, the drive-receiver adopting a feedback mechanism can realize the task of sending a card reader command to the tested passive wireless communication chip and receiving a response frame, and an additional receiver is not required to be added.
The compiling of the verification sequence is important work in the verification process, accounts for 50% of the whole verification workload, has a very large proportion in the whole simulation verification process, and if the efficiency of the work can be improved, the simulation verification period can be effectively shortened. Whether the writing is normal or not directly influences the correctness of the verification result. The verification of the chip is carried out by adopting a mode of combining direct excitation and random excitation, and the result is output in an automatic comparison mode.
Further, the defining a transaction-level data structure includes:
1. parameters in the environment are defined in the form of aggregation parameters, and a transmission frame and a response frame are defined as one transaction. The main verification component of the UVM platform is UVM _ sequence _ item, which is used to define the structure of the verification sequence, such as command format, address range, read length, flag bit, status bit, Cyclic Redundancy Check (CRC), etc.
In practical applications, the transmission frame and the response frame may be defined as two uvm _ sequence _ items respectively, or may be defined as one uvm _ sequence _ item. If two transactions (item) are defined, then 2 parameters need to be passed in at the time of driver, sequencer and sequence definition, which increases the complexity of environment setup. Finally, the invention chooses to define the send and response frames as one transaction, while defining the parameters needed in the environment as aggregated parameters. The design makes the verification environment more concise and clearer.
2. And defining a general data domain and a private data domain of each transaction according to the characteristics of the transactions. For example, the generic data field cmd _ type, the private data field select _ target.
3. Defining the randomization performance of each data field, e.g., constraint c _ select _ target, to ensure that each field of the instruction can be randomized;
a reservation switch for each data field is defined, for example, a switch for reserving correct and wrong crc is convenient for environment expansion;
the function of defining data field is in accordance with field _ automation mechanism, and field _ automation mechanism provided by UVM is fully utilized to realize the functions of printing (print), copying (copy), comparing (compare), packaging (pack) and the like of data. Parameters in the environment are defined in an aggregation parameter mode, so that the verification environment is simpler and clearer.
The rationality of the sequence planning directly determines the efficiency of the verification. The passive wireless communication chip has various instructions, various states and various scene combinations, thereby bringing difficulty to the generation of the sequence, and needing to reasonably plan the level of the sequence.
Further, the constructing a three-tier authentication sequence according to the defined transaction-level data structure and the attributes of the authentication sequence includes:
setting a first layer base sequence for defining common attributes and methods of all verification sequences, such as the raid _ object and the drop _ object;
according to the first layer basic sequence expansion, a second layer command sequence, a second layer state sequence and a second layer specific parameter sequence which are randomly constrained into different scenes are obtained;
and expanding the second layer command sequence, the second layer state sequence or the second layer specific parameter sequence to obtain a third layer function point sequence for realizing different functions under different scenes. The function point sequence needs to further modify the random constraint on the basis of the three sequences of the second layer or the function point sequence is used for completing the verification of each function point. According to the requirements of a passive wireless communication chip, different three-layer sequences are divided by adopting a layering idea, and the sequences are mutually combined and called to meet the verification requirements of complex scenes.
Fig. 5 is a flowchart of a method for verifying a chip by a UVM-based passive wireless communication chip verification platform according to an embodiment of the present invention. As shown in fig. 5, the method includes:
establishing signal connection between a test interface and a tested passive wireless communication chip;
setting a target verification sequence according to the tested passive wireless communication chip;
sending the target verification sequence to the tested passive wireless communication chip, and receiving a response frame of the tested passive wireless communication chip to generate a feedback variable packet;
and comparing the actual response result with the expected response result in the feedback variable packet to obtain a verification result. The verification method is simple and the verification sequence compiling efficiency is high. The method does not need to repeatedly write the state into the part, and improves the efficiency of verifying the sequence writing.
Wherein, the sending of the target verification sequence to the passive wireless communication chip to be tested and the receiving of the response frame of the passive wireless communication chip to be tested are mainly implemented by a driver-receiver, and a feedback mechanism provided by UVM is adopted in the application: sequence- > sequence generator- > driver- > sequence, the driver can return the feedback (response) of one driver to the sequence without adding an extra receiver. Fig. 6 shows a working schematic diagram of a driving-receiving device, which includes the following specific steps:
1) the driver-receiver requests a reader command packet from the sequencer, the reader command packet being generated by the sequencer invoking a target verification sequence from a sequence unit;
2) the driver-receiver judges a communication protocol according to a first command received by a test interface (port), determines whether a leading head needs to be sent or a frame needs to be sent for synchronization, and sends the reader-writer command packet to a passive wireless communication chip to be tested through the test interface according to a format specified by the communication protocol;
3) the driving-receiving unit receives response frame data returned by the tested passive wireless communication chip, and copies the ID information of a request variable (req) in the response frame data to a feedback variable (rsp) to generate a feedback variable packet;
4) and the reader-writer command finishes executing, and returns the ID information of the request variable to the sequencer after triggering the item _ done signal. The drive-receiver adopting the feedback mechanism can realize the task of sending the card reader command to the tested passive wireless communication chip and receiving the response frame without adding an additional receiver, thereby avoiding the increase of the processing of establishing the association of sending and receiving data packets in the verification environment and reducing the complexity of the verification environment.
It should be noted that in the passive wireless communication chip verification, some verification sequences do not need the passive wireless communication chip to respond, so that the reader/writer commands composed of these verification sequences do not have returned response frame data.
Further, the comparing the actual response result with the expected response result in the feedback variable packet to obtain a verification result includes:
converting, by a conversion function module, the target verification sequence into an expected response result;
analyzing the feedback variable by a feedback variable packet analysis module to obtain an actual response result;
and comparing and scoring the actual response result and the expected response result by the comparison function module to obtain a verification result. The conversion of the target verification sequence is realized through the conversion function module, the expected response result of each verification case does not need to be written in the verification case, the complexity of writing the verification case is reduced, and the transplantation and reuse of the verification case in a new project are easy to realize. The function of automatically comparing the running of the verification sequence is realized.
The score board module is responsible for comparing the data returned by the tested passive wireless communication chip, and the component is connected with other components through a first analysis port and a second analysis port. The data comparison mainly includes data comparison of memory areas, state comparison, card flag bit comparison, response time parameter check, etc.
Optionally, the method further includes:
detecting whether the response parameters of the passive wireless communication chip to be detected are correct or not by a monitor; and
and counting the functional coverage rate of the reader-writer command on the tested passive wireless communication chip by a functional coverage rate counting component according to the response parameter.
Further, the functional coverage includes a functional coverage of the timing parameter attribute and a functional coverage of the command information. The checking of the timing parameter attribute mainly comprises the coverage rate statistics of each timing parameter specified by the communication protocol. The functional coverage statistics of the command information mainly comprises statistics of data such as command codes, states, error codes, cyclic redundancy check and the like. The function coverage rate statistics is the key for completing closed-loop verification, and the verification quality can be ensured only by a complete coverage rate statistical model.
Those skilled in the art will appreciate that all or part of the steps in the method for implementing the above embodiments may be implemented by a program, which is stored in a storage medium and includes several instructions to enable a single chip, a chip, or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
While the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications are within the scope of the embodiments of the present invention. It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as disclosed in the embodiments of the present invention as long as it does not depart from the spirit of the embodiments of the present invention.
Claims (15)
1. A passive wireless communication chip verification platform based on UVM, characterized in that, said verification platform includes:
the system comprises a sequence unit, a verification unit and a verification unit, wherein the sequence unit is used for providing a three-layer verification sequence for the verification of a passive wireless communication chip;
the verification top-layer unit is used for establishing signal connection between the test interface and the tested passive wireless communication chip and starting simulation verification;
the environment layer unit is used for sending a target verification sequence to the tested passive wireless communication chip after starting the simulation verification, and performing response result comparison and scoring to obtain a verification result; and
and the test interface is used for connecting the passive wireless communication chip to be tested.
2. The UVM-based passive wireless communication chip verification platform of claim 1, wherein the three-tier verification sequence comprises:
defining a first-layer basic sequence of common attributes and methods of all verification sequences;
randomly constraining the second layer command sequence, the second layer state sequence and the second layer specific parameter sequence of different scenes based on the first layer basic sequence expansion; and
and a third layer function point sequence which realizes different functions under different scenes and is obtained based on the second layer command sequence, the second layer state sequence or the second layer specific parameter sequence expansion.
3. The UVM-based passive wireless communication chip verification platform of claim 1, wherein the environmental layer unit includes:
the reader agent module is used for sending a target verification sequence to the passive wireless communication chip to be tested after the simulation verification is started, receiving a response frame returned by the passive wireless communication chip to be tested, generating a feedback variable packet and transmitting the feedback variable packet to the score board module; and
and the score board module is used for analyzing the feedback variable packet to obtain an actual response result, and comparing and scoring the actual response result and an expected response result to obtain the verification result.
4. The UVM based passive wireless communication chip authentication platform of claim 3, wherein said reader agent module comprises:
the sequence generator is used for generating a reader-writer command according to the target verification sequence and issuing the reader-writer command to the drive-receiver;
the drive-receiver is used for sending the reader-writer command to the tested passive wireless communication chip and receiving a response frame returned by the tested passive wireless communication chip to generate a feedback variable packet;
the monitor is used for detecting whether the response parameters of the passive wireless communication chip to be detected are correct or not; and
and the functional coverage rate counting component is used for counting the functional coverage rate of the reader-writer command on the tested passive wireless communication chip according to the response parameters.
5. The UVM based passive wireless communication chip authentication platform of claim 4, wherein said reader agent module further comprises:
and the configuration component is used for configuring the parameters of the reader-writer command.
6. The UVM based passive wireless communication chip verification platform of claim 3, wherein said scoreboard module includes:
the feedback variable packet analysis module is used for analyzing the feedback variable packet to obtain an actual response result;
the conversion function module is used for converting the target verification sequence into an expected response result;
and the comparison function module is used for comparing and scoring the actual response result and the expected response result to obtain the verification result.
7. The UVM-based passive wireless communication chip verification platform of claim 6, wherein the scoreboard module further comprises:
the first analysis port is used for accessing the target verification sequence and transmitting the target verification sequence to the reader agent module and the transfer function module;
and the second analysis port is used for transmitting the feedback variable packet to the feedback variable packet analysis module.
8. A passive wireless communication chip verification platform construction method based on UVM is characterized by comprising the following steps:
defining a transaction-level data structure;
constructing a three-layer verification sequence according to a defined transaction-level data structure and the attribute of the verification sequence;
a reader agent module is constructed by adopting a driving-receiving device of a feedback mechanism, and the reader agent module is used for sending a target verification sequence to a tested passive wireless communication chip after starting simulation verification, receiving a response frame returned by the tested passive wireless communication chip, generating a feedback variable packet and transmitting the feedback variable packet to a score board module;
constructing an automatic comparison scoring board module, wherein the scoring board module is used for analyzing the feedback variable packet to obtain an actual response result, and comparing and scoring the actual response result and an expected response result to obtain a verification result;
and constructing a functional coverage rate counting component, wherein the functional coverage rate counting component is used for counting the functional coverage rate of the reader-writer command on the tested passive wireless communication chip.
9. The UVM-based passive wireless communication chip verification platform construction method according to claim 8, wherein the defining a transaction-level data structure includes:
parameters in the environment are defined in the form of aggregation parameters, and meanwhile, a sending frame and a response frame are defined as a transaction;
defining a general data domain and a private data domain of each transaction according to the characteristics of the transactions;
defining the randomization performance of each data field;
a reservation switch defining each data field;
the function of the data field is defined to conform to the field _ automation mechanism.
10. The UVM-based passive wireless communication chip verification platform construction method according to claim 8, wherein the construction of a three-layer verification sequence according to a defined transaction-level data structure and attributes of the verification sequence includes:
setting a first layer basic sequence for defining common attributes and methods of all verification sequences;
according to the first layer basic sequence expansion, a second layer command sequence, a second layer state sequence and a second layer specific parameter sequence which are randomly constrained into different scenes are obtained;
and expanding the second layer command sequence, the second layer state sequence or the second layer specific parameter sequence to obtain a third layer function point sequence for realizing different functions under different scenes.
11. A method for verifying a chip by a passive wireless communication chip verification platform based on UVM is characterized by comprising the following steps:
establishing signal connection between a test interface and a tested passive wireless communication chip;
setting a target verification sequence according to the tested passive wireless communication chip;
sending the target verification sequence to the tested passive wireless communication chip, and receiving a response frame of the tested passive wireless communication chip to generate a feedback variable packet;
and comparing the actual response result in the feedback variable packet with the expected response result to obtain a verification result.
12. The UVM-based passive wireless communication chip verification platform chip verification method of claim 11, wherein the sending the target verification sequence to the passive wireless communication chip under test and receiving a response frame of the passive wireless communication chip under test comprises:
1) the driver-receiver requests a reader command packet from the sequencer, the reader command packet being generated by the sequencer invoking a target verification sequence from a sequence unit;
2) the driver-receiver judges a communication protocol according to a first command received by a test interface, and sends the reader-writer command packet to a passive wireless communication chip to be tested through the test interface according to a format specified by the communication protocol;
3) the driving-receiving unit receives response frame data returned by the tested passive wireless communication chip, and copies the ID information of the request variable in the response frame data to a feedback variable to generate a feedback variable packet;
4) the reader-writer commands the execution to end, and returns the ID information of the request variable to the sequencer.
13. The method for verifying the chip by the UVM-based passive wireless communication chip verification platform of claim 11, wherein the comparing the actual response result with the expected response result in the feedback variable packet to obtain the verification result comprises:
converting, by a conversion function module, the target verification sequence into an expected response result;
analyzing the feedback variable by a feedback variable packet analysis module to obtain an actual response result;
and comparing and scoring the actual response result and the expected response result by a comparison function module to obtain the verification result.
14. The UVM-based passive wireless communication chip verification platform verification chip method of claim 12, further comprising:
detecting whether the response parameters of the passive wireless communication chip to be detected are correct or not by a monitor; and
and counting the functional coverage rate of the reader-writer command on the tested passive wireless communication chip by a functional coverage rate counting component according to the response parameter.
15. The UVM-based passive wireless communication chip verification platform chip verification method of claim 14, wherein the functional coverage includes a functional coverage of timing parameter attributes and a functional coverage of command information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011290063.7A CN112100014B (en) | 2020-11-18 | 2020-11-18 | Passive wireless communication chip verification platform, construction method and chip verification method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011290063.7A CN112100014B (en) | 2020-11-18 | 2020-11-18 | Passive wireless communication chip verification platform, construction method and chip verification method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112100014A true CN112100014A (en) | 2020-12-18 |
| CN112100014B CN112100014B (en) | 2021-02-09 |
Family
ID=73784659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011290063.7A Active CN112100014B (en) | 2020-11-18 | 2020-11-18 | Passive wireless communication chip verification platform, construction method and chip verification method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112100014B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113342583A (en) * | 2021-06-08 | 2021-09-03 | 海光信息技术股份有限公司 | Chip verification system, method, device, equipment and storage medium |
| CN114218026A (en) * | 2021-11-29 | 2022-03-22 | 北京百度网讯科技有限公司 | Score board generation method and device, electronic equipment and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935936A (en) * | 2015-06-15 | 2015-09-23 | 东南大学 | Entropy decoder authentication method based on UVM and device |
| CN105446844A (en) * | 2014-09-01 | 2016-03-30 | 上海华虹集成电路有限责任公司 | Read-only register verification test platform and verification method based on UVM (Universal Verification Methodology Manual) |
| CN106294895A (en) * | 2015-05-19 | 2017-01-04 | 上海华虹集成电路有限责任公司 | HDCP transponder controller module level function verification method and verification environment platform |
| CN108196976A (en) * | 2017-12-28 | 2018-06-22 | 湖南国科微电子股份有限公司 | A kind of LDPC simulation and verification platforms, verification method |
| US20180300431A1 (en) * | 2017-04-18 | 2018-10-18 | Raytheon Company | Universal verification methodology (uvm) register abstraction layer (ral) traffic predictor |
| CN109684681A (en) * | 2018-12-06 | 2019-04-26 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Using the high layering verification method of UVM verification platform |
-
2020
- 2020-11-18 CN CN202011290063.7A patent/CN112100014B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105446844A (en) * | 2014-09-01 | 2016-03-30 | 上海华虹集成电路有限责任公司 | Read-only register verification test platform and verification method based on UVM (Universal Verification Methodology Manual) |
| CN106294895A (en) * | 2015-05-19 | 2017-01-04 | 上海华虹集成电路有限责任公司 | HDCP transponder controller module level function verification method and verification environment platform |
| CN104935936A (en) * | 2015-06-15 | 2015-09-23 | 东南大学 | Entropy decoder authentication method based on UVM and device |
| US20180300431A1 (en) * | 2017-04-18 | 2018-10-18 | Raytheon Company | Universal verification methodology (uvm) register abstraction layer (ral) traffic predictor |
| CN108196976A (en) * | 2017-12-28 | 2018-06-22 | 湖南国科微电子股份有限公司 | A kind of LDPC simulation and verification platforms, verification method |
| CN109684681A (en) * | 2018-12-06 | 2019-04-26 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Using the high layering verification method of UVM verification platform |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113342583A (en) * | 2021-06-08 | 2021-09-03 | 海光信息技术股份有限公司 | Chip verification system, method, device, equipment and storage medium |
| CN113342583B (en) * | 2021-06-08 | 2022-11-29 | 海光信息技术股份有限公司 | Chip verification system, method, device, equipment and storage medium |
| CN114218026A (en) * | 2021-11-29 | 2022-03-22 | 北京百度网讯科技有限公司 | Score board generation method and device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112100014B (en) | 2021-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106940428B (en) | Chip verification method, device and system | |
| CN112100014B (en) | Passive wireless communication chip verification platform, construction method and chip verification method | |
| CN108038294B (en) | UVM environment building method and system | |
| CN115841089A (en) | System-on-chip verification platform and verification method based on UVM | |
| CN112286746B (en) | Universal verification platform and method for AXI slave device interface | |
| CN113076227A (en) | MCU verification method, system and terminal equipment | |
| CN113486625B (en) | Chip verification method and verification system | |
| US11507718B1 (en) | Chip verification system and verification method therefor | |
| CN109597653A (en) | Method, BIOS and the BMC of BIOS and BMC command interaction | |
| CN115146568A (en) | Chip verification system and verification method based on UVM | |
| CN102737727B (en) | The method and system of Double Data Rate synchronous DRAM stability test | |
| US6487699B1 (en) | Method of controlling external models in system-on-chip verification | |
| CN115496018A (en) | Multi-version verification method, device and equipment for SoC (System on chip) | |
| CN112363877A (en) | Chip verification method and platform | |
| US8250545B2 (en) | Associated apparatus and method for supporting development of semiconductor device | |
| CN109901664A (en) | Method, apparatus, system, equipment and the readable storage medium storing program for executing of clock signal are provided | |
| CN115685785B (en) | Universal bus model and simulation test method | |
| CN115659885B (en) | System and method for simulation test | |
| CN116894411A (en) | SPI module verification platform and method with DMA interface | |
| CN113177388B (en) | Device, system and method for testing and verifying IP (Internet protocol) core | |
| CN114513436B (en) | SDIO device transmission rate detection method, system and storage medium | |
| CN114444423B (en) | Data processing method and system based on verification platform and electronic equipment | |
| CN115684897B (en) | Method and device for testing chip | |
| CN116842902B (en) | System-level simulation modeling method for black box model | |
| CN109669872A (en) | A kind of verification method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |