CN112086516B - Semiconductor-on-insulator structure and total dose radiation resisting reinforcement method thereof - Google Patents
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract
The invention relates to a semiconductor-on-insulator structure and a method for reinforcing the same against total dose irradiation. A semiconductor-on-insulator structure comprising, from bottom to top: the semiconductor device comprises a semiconductor substrate, a first insulating layer, an electron trapping layer and a second insulating layer, wherein the electron trapping layer is made of different materials from the first insulating layer and the second insulating layer, and the semiconductor layer comprises a source region, a drain region and a channel region arranged between the source region and the drain region; and a third insulating layer, a gate electrode. The invention solves the problems that the existing reinforcement scheme has application limitation and can not flexibly and non-volatile solve the accumulation and irreversibility of the total dose irradiation effect due to the reasons of complex process, channel parasitic effect, inflexible application and the like.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor-on-insulator structure and a method for reinforcing the same against total dose irradiation.
Background
Compared with a bulk silicon metal-oxide-semiconductor field effect transistor (MOSFET), the Fully Depleted Silicon On Insulator (FDSOI) device has the advantages of small parasitic capacitance, good capability of regulating and controlling short channel effects such as drain to barrier reduction (DIBL), good subthreshold characteristic, no need of isolation process of a bulk silicon circuit in a special structure, good single event resistance effect and the like, is widely applied to the fields of space, military and the like, and has wide application prospect in the aspects of high-performance ultra-large-scale integrated circuits, high-speed storage equipment, low-power-consumption circuits, military anti-irradiation and the like.
Although the N-type FDSOI device has excellent resistance to the single event effect, the total dose irradiance effect of the device is exacerbated by the presence of its buried oxide layer. The existing total dose effect reinforcement schemes are various, such as omega-shaped gate structures, partially Depleted SOI (PDSOI), BUSFET, back gate voltage regulation and control and the like. However, the manufacturing process of the omega-shaped gate structure is complex, the PDSOI enables the back drain to be far away from the source drain region, but the parasitic effect still exists, the BUSFET source drain is not interchangeable, so that the application is inflexible, and the back gate voltage regulation and control can inhibit the back gate leakage but is inconvenient to operate. Moreover, although the reinforcement scheme except the back gate voltage regulation has a certain inhibition effect on the total dose effect, the regulation on the total dose effect cannot be realized, and the problems of accumulation and irreversibility of the irradiation effect cannot be solved. The back gate voltage regulation can regulate the back channel electron inversion caused by the total dose effect, but needs to keep the back gate voltage drop continuously, and does not have non-volatility. These solutions have limitations when designing complex, large scale integrated circuits.
Disclosure of Invention
It is a primary object of the present invention to provide a semiconductor-on-insulator structure that has superior total dose radiation (TID) resistance compared to the same type of device.
Another object of the present invention is to provide the method for reinforcing a semiconductor-on-insulator structure against total dose radiation, which solves the problems of application limitation and incapability of flexibly and non-volatile solving the accumulation and irreversibility of the total dose radiation effect due to complex process, channel parasitic effect, inflexible application and the like of the existing reinforcing scheme.
In order to achieve the above object, the present invention provides the following technical solutions:
a semiconductor-on-insulator structure comprising, from bottom to top:
a semiconductor substrate having a semiconductor layer formed thereon,
a first insulating layer is provided over the first insulating layer,
an electron-trapping layer is provided between the first and second electron-trapping layers,
a second insulating layer is provided over the first insulating layer,
the semiconductor layer is formed of a semiconductor layer,
a third insulating layer is provided on the first insulating layer,
a gate;
the semiconductor layer comprises a source region, a drain region and a channel region arranged between the source region and the drain region; the electron capturing layer is made of a material different from that of the first insulating layer and the second insulating layer.
The above-described semiconductor-on-insulator structure, which is added with a second insulating layer and an electron trapping layer as compared with a conventional N-type semiconductor-on-insulator device, can be used to offset positive charges accumulated by multiple particle incidence in a radiation environment, and thus, the structure itself naturally has excellent total dose radiation (TID) resistance. If electrons FN (Fowler-Nordheim) in the channel region are tunneled into the electron trapping layer under a pressing operation, the total dose effect resistance is better.
The corresponding method for reinforcing the semiconductor-on-insulator structure by resisting total dose irradiation comprises the following steps: the semiconductor-on-insulator structure is subjected to the following pressing operation:
the source region, the drain region and the grid electrode are grounded, a positive bias voltage is applied to the semiconductor substrate, and the positive bias voltage is maintained until the semiconductor-on-insulator structure achieves preset electrical performance; wherein the forward bias voltage can enable electrons in the channel region to generate FN tunneling, and the FN tunneling is preferably 7V-18V.
As described above, the method applies a specific voltage strength to enable electrons in the channel region to generate FN tunneling and be captured by the electron capturing layer, so that positive charges accumulated by multiple particle incidence in a radiation environment can be counteracted, and electrical property damage or other harm caused by radiation is avoided.
In addition, in order to more intuitively and quantitatively compare the change of the electrical property of the device before and after irradiation and the change of the electrical property after irradiation reinforcement, the electrical property of the device before irradiation and the performance after working in a simulated irradiation environment are tested before irradiation reinforcement by the method, and then the electrical property of the device after reinforcement is tested after irradiation reinforcement is completed. The invention is not limited to test conditions and simulated irradiation environments, and can be determined according to the specific application and use environment of the device.
Wherein, the electrical performance of the device before irradiation before reinforcement can be tested by the following method:
the source region and the substrate are grounded, the drain region is applied with a fixed positive bias, and the grid electrode is applied with a positive bias scan gradually increasing from 0 volt to observe the current change.
The simulated irradiation environment may be:
the source region, the substrate and the grid electrode are grounded, a positive bias voltage is applied to the drain region, the device to be tested is exposed to an irradiation source, the irradiation source is Co-60, and current change is observed through scanning.
The method for testing the electrical performance of the device after irradiation reinforcement refers to the method for testing the electrical performance before irradiation, namely:
the source region and the substrate are grounded, the drain region is applied with a fixed positive bias, and the grid electrode is applied with a positive bias scan gradually increasing from 0 volt to observe the current change.
In addition, the irradiation strengthening method is particularly suitable for restoring the electrical property of the device after irradiation, and the restoring is nonvolatile.
In conclusion, compared with the prior art, the invention achieves the following technical effects:
(1) The novel semiconductor device on the insulating layer is provided, and the device has good total dose radiation resistance naturally;
(2) The structure added by the novel semiconductor device on the insulating layer can be prepared by using traditional materials and processes, is compatible with the traditional CMOS process, has no complex process and has the advantage of cost; namely, the invention improves the total dose irradiation resistance of the device with lower cost;
(3) The method overcomes the defects that the traditional total dose reinforcement scheme cannot improve the total dose effect accumulation, is irreversible or needs to continuously maintain the regulation voltage, can realize the irradiation reinforcement and the electrical property recovery of the device through programming, and is nonvolatile.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
Fig. 1 is a schematic diagram of a novel semiconductor-on-insulator device according to an embodiment of the present invention;
FIG. 2 is a schematic illustration of a radiation-induced consolidation process for a novel semiconductor-on-insulator device according to an embodiment of the present invention;
FIG. 3 is a voltage schematic for a novel semiconductor-on-insulator device of the present invention in a radiation operation;
FIG. 4 is a schematic view of electron tunneling through the channel region during irradiation strengthening operation of the novel semiconductor-on-insulator device of the present invention;
FIG. 5 is a schematic diagram of transfer characteristics of a novel semiconductor-on-insulator device of the present invention before irradiation, after irradiation, and after irradiation consolidation;
reference numerals:
11-a semiconductor substrate; 12-a first insulating layer; 13-an electron capture layer;
14-a second insulating layer; 15-a third insulating layer; a 16-gate;
111-source region; 112-drain region; 113-channel region.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
In order to solve the problems that the irradiation reinforcement process in the prior art cannot flexibly and non-volatile, and the like, the invention provides the following novel semiconductor-on-insulator device structure and an irradiation reinforcement method based on the structure.
A semiconductor-on-insulator structure, as shown in fig. 1, comprising, from bottom to top:
the semiconductor substrate 11 is provided with a semiconductor layer,
the first insulating layer 12 is provided with a first insulating layer,
the electron-trapping layer 13 is provided with a light-emitting layer,
the second insulating layer 14 is provided with a layer of insulating material,
a semiconductor layer, wherein the semiconductor layer includes a source region 111, a drain region 112, and a channel region 113 disposed between the source region 111 and the drain region 112;
a third insulating layer 15 is provided which,
a gate electrode 16;
wherein the electron trapping layer 13 is made of a material different from that of the first insulating layer 12 and the second insulating layer 14.
The above-described semiconductor-on-insulator structure, which is added with a second insulating layer and an electron trapping layer as compared with a conventional N-type semiconductor-on-insulator device, can be used to offset positive charges accumulated by multiple particle incidence in a radiation environment, and thus, the structure itself naturally has excellent total dose radiation (TID) resistance. If electrons FN (Fowler-Nordheim) in the channel region are tunneled into the electron trapping layer under a pressing operation, the total dose effect resistance is better.
In some embodiments, the first insulating layer has a thickness of 5nm to 30nm.
In some embodiments, the electron capture layer has a thickness of 8nm to 15nm to ensure adequate ability to capture electrons.
In some embodiments, the second insulating layer is thinner than the first insulating layer to ensure that electrons can tunnel through the second insulating layer to the electron trapping layer without readily leaking from the second insulating layer; in a more preferred embodiment, the thickness of the second insulating layer is 4nm to 9nm.
In some embodiments, the gate structure is any gate structure that is not limited to a planar gate structure or a vertical gate structure.
In some embodiments, the insulating layer preparation material is SiO 2 Or one of the silicon oxide silicon nitride composite dielectric layers.
In some embodiments, the electron-trapping layer is Si 3 N 4 One of a floating metal gate or polysilicon.
In some embodiments, the gate is one of polysilicon or a metal gate.
In some embodiments, the semiconductor substrate is a silicon substrate or a sapphire substrate, or the like.
Any of the above semiconductor-on-insulator structures is suitable for the following irradiation strengthening method. In order to improve the testing and reinforcing efficiency and simultaneously minimize the influence of factors outside irradiation/reinforcement on the result, a complete testing and irradiation reinforcing process is provided below, namely, testing the electrical properties of the device before irradiation and the device after irradiation before irradiation reinforcement, and the specific process is shown in fig. 2.
Step S21: performing a first pressing operation, and testing the electrical performance of the device before irradiation, wherein the first pressing operation comprises: the source region and the substrate are grounded, the drain region is applied with a fixed positive bias, and the grid electrode is applied with a positive bias scan which gradually increases from 0 volt.
Step S22: and (3) canceling the first pressurizing operation, performing a first irradiation operation, and performing an irradiation experiment on the device according to the embodiment, wherein the first irradiation operation comprises: the source region, the substrate, and the gate electrode are grounded, and the drain region is biased positively to expose the device of this embodiment to a radiation source, as shown in fig. 3. Typically the irradiation source is Co-60.
Step S23: and the first irradiation operation is canceled, and the first pressurizing operation is performed to test the electrical performance of the device after irradiation in the embodiment.
Step S24: and the first pressing operation is canceled, a second pressing operation is carried out, a high electric field is formed in the channel region, and the second pressing operation comprises the following steps: the source region, the drain region, and the gate electrode are grounded, and a positive bias voltage is applied to the substrate, for example, the positive bias voltage used in some embodiments is 7V to 18V.
Step S25: maintaining the second pressing operation to perform irradiation reinforcement on the device according to the embodiment. After a period of time, electrons in the channel region tunnel to the electron trapping layer through FN tunneling, as shown in fig. 4, the electron tunneling direction is perpendicular to the length direction of the second insulating layer.
Wherein, the second pressing operation is maintained in two ways, the first maintaining way is to maintain the second pressing operation for a longer time, and the first maintaining way is a Direct Current (DC) programming way; the second maintaining mode is to intermittently maintain the second pressing operation, and is an Alternating Current (AC) programming mode.
Step S26: and the second pressing operation is canceled, and the first pressing operation is performed to test the electrical performance of the device after irradiation reinforcement in the embodiment.
In the above method, step S24 and step S25 are key steps for completing irradiation reinforcement, and the positive bias value and the duration of the pressing may be determined according to the device type, the material and thickness of each functional layer, and other factors. If the reinforcement and repair of the two steps are insufficient, so that the device still cannot meet the preset requirements, the step S24 and the step S25 can be repeated until the required electrical performance is met after the test of the step S26.
The invention also provides the following examples, and the electrical properties of the devices before irradiation, after irradiation and after irradiation reinforcement are tested.
The semiconductor structure of this embodiment is shown in fig. 1, and specifically includes: semiconductor linerThe bottom 11 is a silicon substrate, the thicknesses of the first insulating layer 12, the electron capturing layer 13 and the second insulating layer 14 are respectively 5nm to 30nm,8nm to 15nm, and all insulating layer materials of 4nm to 9nm are SiO 2 Or silicon oxide silicon nitride composite material, the material of the electron trapping layer 13 is Si 3 N 4 A floating metal gate or polysilicon, and gate 16 is a polysilicon or metal gate.
The device of this example was consolidated by irradiation in the same manner as shown in fig. 2. Wherein, the positive bias voltage of the second pressing operation in the step S24 is 7V-18V, and the maintaining time is 1 mu S-10 ms.
Through testing, the electrical properties of the device before irradiation, after irradiation and after irradiation reinforcement are shown in fig. 5, and the data show that: since electrons trapped in the electron trapping layer cancel to some extent the effect of positive charges generated in the insulating layer due to the total dose irradiation, the electric leakage level thereof can be restored to the level before irradiation to some extent.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (9)
1. A method of total dose irradiation resistance reinforcement of a semiconductor-on-insulator structure, the semiconductor-on-insulator structure comprising, from bottom to top:
a semiconductor substrate having a semiconductor layer formed thereon,
a first insulating layer is provided over the first insulating layer,
an electron-trapping layer is provided between the first and second electron-trapping layers,
a second insulating layer is provided over the first insulating layer,
the semiconductor layer is formed of a semiconductor layer,
a third insulating layer is provided on the first insulating layer,
a gate;
the electron capturing layer is made of a material different from that of the first insulating layer and the second insulating layer, and the semiconductor layer comprises a source region, a drain region and a channel region arranged between the source region and the drain region;
the method includes applying a compressive force to the semiconductor-on-insulator structure as follows:
the source region, the drain region, and the gate electrode are grounded, a positive bias is applied to the semiconductor substrate, and the positive bias is maintained until the semiconductor-on-insulator structure achieves a desired electrical performance; wherein the forward bias voltage can enable electrons in the channel region to generate FN tunneling, and the FN tunneling is 7V-18V; the maintenance method comprises the following steps: maintaining by applying direct current or alternating current; the duration of the maintenance is 1 mus to 10ms.
2. The method of total dose radiation resistant reinforcement according to claim 1, wherein the thickness of the second insulating layer is less than the thickness of the first insulating layer.
3. The method of total dose radiation resistant reinforcement according to claim 1 or 2, wherein the thickness of the first insulating layer is 5nm to 30nm; the thickness of the second insulating layer is 4 nm-9 nm.
4. The method of claim 1, wherein the electron trapping layer has a thickness of 8nm to 15nm.
5. The method of total dose radiation resistant consolidation of claim 1 wherein each of said first, second and third insulating layers is independently SiO 2 Or a silicon oxide silicon nitride composite.
6. The method of claim 1, wherein the electron trapping layer is Si 3 N 4 A floating metal gate or polysilicon.
7. The method of claim 1, wherein the gate is a polysilicon or metal gate.
8. The method of claim 1, wherein the grid is a planar grid or a vertical grid.
9. The method of total dose radiation resistant reinforcement as defined in claim 1, wherein said semiconductor substrate is a silicon substrate.
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| CN1467851A (en) * | 2002-07-05 | 2004-01-14 | ������������ʽ���� | Nonvolatile semiconductor memory device |
| CN101707210A (en) * | 2009-11-27 | 2010-05-12 | 北京大学 | Anti-radiation field effect transistor, CMOS integrated circuit and preparation thereof |
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| CN1467851A (en) * | 2002-07-05 | 2004-01-14 | ������������ʽ���� | Nonvolatile semiconductor memory device |
| CN101707210A (en) * | 2009-11-27 | 2010-05-12 | 北京大学 | Anti-radiation field effect transistor, CMOS integrated circuit and preparation thereof |
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