CN112086117A - Phase change memory, memory control method and memory chip - Google Patents
Phase change memory, memory control method and memory chip Download PDFInfo
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- CN112086117A CN112086117A CN202010969755.8A CN202010969755A CN112086117A CN 112086117 A CN112086117 A CN 112086117A CN 202010969755 A CN202010969755 A CN 202010969755A CN 112086117 A CN112086117 A CN 112086117A
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/008—Write by generating heat in the surroundings of the memory material, e.g. thermowrite
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/50—Resistive cell structure aspects
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/50—Resistive cell structure aspects
- G11C2213/52—Structure characterized by the electrode material, shape, etc.
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
Abstract
The invention relates to a phase change memory, a memory control method and a memory chip, wherein the phase change memory comprises a first electrode, a second electrode, a phase change memory layer, a plurality of heaters and a control unit; the phase change memory layer is positioned between the first electrode and the second electrode and is respectively and electrically connected with the first electrode and the second electrode; the control unit is electrically connected with the heaters respectively and is used for providing driving signals for the heaters; the heaters are respectively adjacent to different phase change areas of the phase change memory layer, and each heater is configured to heat the adjacent phase change area under the driving of a driving signal, so that the multi-value storage of a single memory cell can be realized, and the storage density of the phase change memory is improved.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductor devices, in particular to a phase change memory, a memory control method and a memory chip.
[ background of the invention ]
The phase change memory has the advantages of high-speed reading, high erasable times, nonvolatility, small element size, low power consumption, strong shock resistance, radiation resistance and the like, and is considered by the international association of semiconductor industry as a device which is most likely to replace the current flash memory and becomes the mainstream product of the future memory and a device which is the commercial product at first.
However, the storage density of the phase change memory is still to be improved.
[ summary of the invention ]
The invention aims to provide a phase change memory, a memory control method and a memory chip, so as to improve the storage density of the phase change memory.
In order to solve the above problems, the present invention provides a phase change memory including a first electrode, a second electrode, a phase change memory layer, a plurality of heaters, and a control unit; the phase change memory layer is positioned between the first electrode and the second electrode and is respectively and electrically connected with the first electrode and the second electrode; the control unit is electrically connected with the heaters respectively and is used for providing driving signals for the heaters; and a plurality of heaters respectively adjacent to different phase change regions of the phase change memory layer, wherein each heater is configured to heat the adjacent phase change region under the driving of a driving signal.
Wherein, the phase change area adjacent to each of the heaters comprises at least two target phase change areas with different volume sizes.
Wherein the heating areas of the at least two target phase change regions by the adjacent heaters are different, so that the volumes of the at least two target phase change regions are different.
The heaters are columnar or cuboid, and the areas of at least two target phase change areas opposite to the adjacent heaters are different.
Wherein the heating time lengths of the at least two target phase change regions by the adjacent heaters are different, so that the volumes of the at least two target phase change regions are different.
Wherein the powers of the driving signals of the heaters of the at least two target phase change regions which are adjacent are different, so that the volumes of the at least two target phase change regions are different.
The phase change memory layer is provided with an upper surface, a lower surface and a side surface positioned between the upper surface and the lower surface, wherein the phase change memory layer is electrically connected with the first electrode through the upper surface and electrically connected with the second electrode through the lower surface; and a plurality of heaters adjoining the phase change region through the side surface.
The phase change memory further comprises an isolation layer, the isolation layer is arranged on the side surface, the heater is at least partially embedded in the isolation layer, and the isolation layer electrically isolates the heater from the first electrode and the second electrode.
The control unit comprises a power supply electronic unit and a plurality of heating control switches, wherein each heater is electrically connected with the power supply electronic unit through one heating control switch; the power supply electronic unit is configured to supply a driving signal to the corresponding heater through the heating control switch when the heating control switch is turned on.
Any two phase change areas in the phase change storage layer are not overlapped.
The phase change memory also comprises a reading control switch electrically connected to the second electrode.
In order to solve the above problem, the present invention also provides a memory control method applied to the phase change memory of any one of the above, the memory control method including: receiving, by a control unit, a first instruction to write data; in response to the first instruction, a drive signal is output to each heater by the control unit.
The memory control method further comprises the following steps: receiving, by the peripheral logic circuit, a second instruction to read data; in response to a second instruction, a voltage is output to the first electrode and the second electrode through the peripheral logic circuit.
In order to solve the above problems, the present invention further provides a memory chip, which includes a memory array, where the memory array includes an array of any one of the phase change memories described above.
The invention has the beneficial effects that: different from the prior art, the phase change memory provided by the invention comprises a first electrode, a second electrode, a phase change storage layer, a plurality of heaters and a control unit, wherein the phase change storage layer is positioned between the first electrode and the second electrode and is respectively and electrically connected with the first electrode and the second electrode, the control unit is respectively and electrically connected with the plurality of heaters and is used for providing driving signals for the heaters, the plurality of heaters are respectively adjacent to different phase change areas of the phase change storage layer, and each heater is configured to heat the adjacent phase change areas under the driving of the driving signals, so that the multi-value storage of a single storage unit can be realized, and the storage density of the phase change memory is further improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a vertical cross-sectional structure of a phase change memory according to an embodiment of the invention;
FIG. 2 is a cross-sectional structure diagram of a phase change memory according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another cross-sectional structure of a phase change memory according to an embodiment of the invention;
FIG. 4 is a schematic diagram of another vertical cross-sectional structure of a phase change memory according to an embodiment of the invention;
FIG. 5 is a schematic diagram of another vertical cross-sectional structure of a phase change memory according to an embodiment of the invention;
FIG. 6 is a schematic diagram of another vertical cross-sectional structure of a phase change memory according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another vertical cross-sectional structure of a phase change memory according to an embodiment of the invention;
FIG. 8 is a flowchart illustrating a memory control method according to an embodiment of the invention.
[ detailed description ] embodiments
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.
In addition, directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], and the like, refer to directions of the attached drawings only. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic diagram of a vertical cross-sectional structure of a phase change memory according to an embodiment of the invention, and fig. 2 is a schematic diagram of a cross-sectional structure of the phase change memory according to the embodiment of the invention. As shown in fig. 1 and 2, the phase change memory 10 includes a first electrode 11, a second electrode 12, a phase change memory layer 13, a plurality of heaters 141/142/143/144, and a control unit 15. Wherein the phase change memory layer 13 is located between the first electrode 11 and the second electrode 12, and is electrically connected to the first electrode 11 and the second electrode 12, respectively. The control unit 15 is electrically connected to the plurality of heaters 141/142/143/144, respectively, for supplying driving signals to the respective heaters 141/142/143/144. The plurality of heaters 141/142/143/144 respectively adjoin different phase change regions 131/132/133/134 of the phase change memory layer 13, and each heater 141/142/143/144 is configured to heat the adjoining phase change region 131/132/133/134 under driving of a driving signal.
For example, as shown in fig. 1 and 2, the heater 141 is adjacent to the phase change region 131 and configured to heat the phase change region 131 under the driving of the driving signal; the heater 142 is adjacent to the phase change region 132 and configured to heat the phase change region 132 under the driving of the driving signal; the heater 143 is adjacent to the phase change region 133 and configured to heat the phase change region 133 under the driving of the driving signal; and a heater 144 is adjacent to the phase change region 134 and configured to heat the phase change region 134 upon actuation of the drive signal.
Phase-change memory layer 13 may include, among other things, a phase-change material, such as a germanium-antimony-tellurium (Ge-Sb-Te, abbreviated GST) -based material (e.g., Ge2Sb2Te5) One or more of (a). The phase change materialThe material may be switched between different phases (e.g., crystalline and amorphous) when heated. And the resistivity of the same material is greatly different between a crystalline phase and an amorphous phase. In particular, the resistivity of a phase change material in the amorphous phase may be hundreds to thousands of times higher than the resistivity in the crystalline phase. The heater 141/142/143/144 can be cylindrical or rectangular in shape, and the heater 141/142/143/144 can be made of a resistive material with a suitable resistivity, such as a metallic material, a ceramic material, or a composite material. In some embodiments, the heater 141/142/143/144 may be made of a nickel-chromium alloy comprising 80% nickel and 20% chromium. Also, depending on the material forming the heater, the heater 141/142/143/144 may include a metallic heating material, a ceramic heating material, or a composite heating material.
Specifically, the above-described heater 141/142/143/144 abutting the phase change region 131/132/133/134 may include two cases. One such case is where heater 141/142/143/144 is not in contact with, but is close to, phase change region 131/132/133/134. Another case is where heater 141/142/143/144 contacts phase change region 131/132/133/134. In some embodiments, when the distance between heater 141/142/143/144 and phase change region 131/132/133/134 is greater than a preset threshold (e.g., 1mm), heater 141/142/143/144 may be considered to be not in contact with but close to phase change region 131/132/133/134.
It is understood that the heater 141/142/143/144 in the embodiment of the present invention refers to any one or more of the heater 141, the heater 142, the heater 143, and the heater 144. The material, shape and distance between the phase change regions of different heaters may be the same or different, and the embodiment of the invention is not limited thereto.
In the present embodiment, the heater 141/142/143/144 is used to heat at least a portion of the phase-change memory layer 13 to change the phase state of at least a portion of the phase-change memory layer 13. The heaters 141/142/143/144 may correspond one-to-one to the phase change regions 131/132/133/134, and the phase change regions 131/132/133/134 may be understood to correspond to at least a portion of the phase change memory layer 13 heated by the heaters 141/142/143/144. The shape of phase change region 131/132/133/134 may be determined by a number of factors, among others. The plurality of factors include, for example, any of the configuration of the phase-change storage layer 13 (e.g., surface shape, length, width, height, etc.), properties (e.g., thermophysical properties such as phase-change temperature, phase-change enthalpy, thermal conductivity, etc.), and the shape and/or arrangement of the heater 141/142/143/144. Here, the heater 141/142/143/144 may be disposed between the first electrode 11 and the second electrode 12, between the first electrode 11 and the phase-change memory layer 13, or between the second electrode 12 and the phase-change memory layer 13. In some embodiments, the phase change region 131/132/133/134 may have a dome or another shape.
It is understood that when the heater 141/142/143/144 is not in contact with but close to the phase change region 131/132/133/134, joule heat generated by the heater 141/142/143/144 may be indirectly conducted to the phase change region 131/132/133/13 through the region between the heater 141/142/143/144 and the phase change region 131/132/133/134; when the heater 141/142/143/144 contacts the phase change region 131/132/133/134, joule heat generated by the heater 141/142/143/144 may be directly conducted into its corresponding phase change region 131/132/133/134.
Specifically, as shown in fig. 1 and 2, the phase change memory layer 13 has an upper surface 13A, a lower surface 13B, and a side surface 13C between the upper surface 13A and the lower surface 13B. The phase change memory layer 13 may be electrically connected to the first electrode 11 through the upper surface 13A, and electrically connected to the second electrode 12 through the lower surface 13B. The plurality of heaters 141/142/143/144 may adjoin phase change region 131/132/133/134 through side surface 13C.
In particular, the shape of the surface of the heater 141/142/143/144 directly opposite to the side surface 13C of the phase change memory layer 13 may match the shape of the side surface 13C of the phase change memory layer 13. For example, when the side surface 13C of the phase change memory layer 13 is a plane, the surface of the heater 141/142/143/144 directly opposite to the side surface 13C of the phase change memory layer 13 may also correspond to a plane (e.g., the bottom surface of a columnar heater); when the side surface 13C of the phase change memory layer 13 is a curved surface (e.g., a side surface of a cylindrical phase change memory layer), a surface of the heater 141/142/143/144 directly opposite to the side surface 13C of the phase change memory layer 13 may also correspond to a curved surface. In this manner, joule heat generated by heater 141/142/143/144 can be ensured to be uniformly and efficiently conducted to corresponding phase change region 131/132/133/134 through side surface 13C.
It is to be understood that fig. 1 and 2 are described by way of example in which the heater 141/142/143/144 abuts the side surface 13C of the phase-change memory layer 13. However, the embodiment of the present invention does not limit the specific location where the heater 141/142/143/144 abuts the phase-change memory layer 13. For example, the upper surface 13A and the lower surface 13B of the phase change memory layer 13 may also reserve positions for the heaters 141/142/143/144. The heater 141/142/143/144 may also be adjacent to the upper surface 13A and the lower surface 13B of the phase-change memory layer 13.
In this embodiment, the size of the phase change region 131/132/133/134 is controllable. Specifically, when the adjacent phase change region 131/132/133/134 is heated by the heater 141/142/143/144, the volume size of the corresponding phase change region 131/132/133/134 may be controlled by the control unit 15 controlling the heating parameters (e.g., heating time period, heating current or heating voltage, etc.) of the heater 141/142/143/144. Wherein, the heating current and the heating voltage may be equal to the output current and the output voltage of the driving signal provided by the control unit 15 to the heater 141/142/143/144, and the heating time period may be equal to the duration of the driving signal applied by the control unit 15 to the heater 141/142/143/144. In particular, the heating current may be used to characterize the current flowing through heater 141/142/143/144 as heater 141/142/143/144 heats adjacent phase change region 131/132/133/134. The heating voltage may be used to characterize the voltage difference between the input and output of heater 141/142/143/144 when heater 141/142/143/144 heats the adjacent phase change region 131/132/133/134.
In one embodiment, the phase change regions 131/132/133/134 adjacent to each of the plurality of heaters 141/142/143/144 may have the same volume size. Accordingly, the effect of the transition of the plurality of phase change regions 131/132/133/134 corresponding to the plurality of heaters 141/142/143/144 from the first phase state (e.g., crystalline phase) to the second phase state (e.g., amorphous phase) on the resistance value of the phase change memory layer 13 may be the same, that is, the resistance value of the phase change memory layer 13 may be related to only the number of phase change regions 131/132/133/134 in which the phase change occurs. For example, when the number of the phase change regions 131/132/133/134 is n, where n is 2 or more, the phase change memory layer 13 may have (n +1) states with different resistance values, thereby enabling the storage of multi-bit binary numbers. Taking n equal to 3 as an example, one phase change memory layer 13 may implement the storage of 2-bit binary numbers.
In other embodiments, in order to further increase the storage density of the phase change memory 10, the plurality of phase change regions 131/132/133/134 corresponding to the plurality of heaters 141/142/143/144 may have different volume sizes. Accordingly, the plurality of phase change regions 131/132/133/134 corresponding to the plurality of heaters 141/142/143/144 have different influences on the resistance value of the phase change memory layer 13 when the phase change regions are changed from a first phase state (e.g., a crystal phase) to a second phase state (e.g., an amorphous phase). That is, the resistance value of the phase change memory layer 13 is related to not only the number of the phase change regions 131/132/133/134 where the phase change occurs but also the volume size of the phase change region 131/132/133/134 where the phase change occurs. For example, when the number of the phase change regions 131/132/133/134 is m, where m is 2 or more, the phase change memory layer 13 corresponding to the above may have 2mDifferent resistance values, thereby enabling the storage of multi-bit binary numbers (i.e., m-bit binary numbers). Taking m equal to 4 as an example, one phase change memory layer 13 may enable the storage of a 4-bit binary number.
In other embodiments, the phase change regions 131/132/133/134 adjacent to each of the heaters 141/142/143/144 may include at least two target phase change regions 131/132/133/134 with different volume sizes. For example, with continued reference to fig. 2, four target phase change regions 131/132/133/134 having different volume sizes may be included, or target phase change regions 131 and 133 having different volume sizes and phase change regions 132 and 134 having the same volume size as target phase change region 131 may be included.
In some embodiments, the heating area of the at least two target phase change regions 131/132/133/134 by the adjacent heaters 141/142/143/144 may be different such that the volume of the at least two target phase change regions 131/132/133/134 are different in size. Specifically, when the heater 141/142/143/144 is in contact with the corresponding phase change region 131/132/133/134, the heating area of the heater 141/142/143/144 may be understood as the contact area of the heater 141/142/143/144 with the phase change memory layer 13. When the heater 141/142/143/144 is not in contact with but close to the corresponding phase change region 131/132/133/134, the heating area of the heater 14 can be understood as the area directly facing between the phase change memory layer 13 and the heater 141/142/143/144. In one embodiment, the plurality of heaters 141/142/143/144 may have the same shape and different sizes and abut corresponding phase change regions 131/132/133/134 such that the facing areas of at least two target phase change regions 131/132/133/134 and the abutted heaters 141/142/143/144 are different.
In other embodiments, at least two target phase change regions 131/132/133/134 may be heated by adjacent heaters 141/142/143/144 for different durations such that the volumes of the at least two target phase change regions 131/132/133/134 are different in size. In this way, when the heating areas of the heaters 141/142/143/144 adjacent to the at least two target phase change regions 131/132/133/134 are the same, the volume sizes of the at least two target phase change regions 131/132/133/134 may be made different by controlling the heating time periods of the heaters 141/142/143/144 adjacent to the at least two target phase change regions 131/132/133/134 by the control unit 15.
In other embodiments, the power of the drive signals to the heaters 141/142/143/144 to which at least two target phase change regions 131/132/133/134 are adjoined may be different such that the volumes of the at least two target phase change regions 131/132/133/134 are different in size. In this way, when the heating areas of the heaters 141/142/143/144 adjacent to the at least two target phase change regions 131/132/133/134 are the same and the heating time lengths of the at least two target phase change regions 131/132/133/134 by the adjacent heaters 141/142/143/144 are the same, the power of the driving signal of the heater 141/142/143/144 adjacent to the at least two target phase change regions 131/132/133/134 can be controlled by the control unit 15, so that the volumes of the at least two target phase change regions 131/132/133/134 are different. In practical implementation, the control unit 15 may adjust the magnitude of the driving signal (e.g., a pulse current or a pulse voltage) applied to the heater 141/142/143/144, so that the powers of the driving signals of the heaters 141/142/143/144 adjacent to the at least two target phase change regions 131/132/133/134 may be different.
It is understood that, in order to make the volumes of the at least two target phase change regions 131/132/133/134 different, the sizes of the joule heat generated by the heaters 141/142/143/144 corresponding to the at least two target phase change regions 131/132/133/134 when heating the respective adjacent target phase change regions 131/132/133/134 are different, and are not limited to only different heating areas, only different heating time periods, or only different powers of the driving signals. In some embodiments, each heater 141/142/143/144 corresponding to at least two target phase change regions 131/132/133/134 may differ in at least two of heating area, heating duration, and power of the driving signal.
In one embodiment, as shown in fig. 3, the control unit 15 may include an electronic unit 151 and a plurality of heating control switches 152 (structures within a dotted frame in the figure). Wherein each heater 141/142/143/144 is electrically connected to the power supply unit 151 through one heating control switch 152, and the power supply unit 152 is configured to provide a driving signal to the corresponding heater 141/142/143/144 through the heating control switch 152 when the heating control switch 152 is turned on, so that the heater 141/142/143/144 heats the corresponding phase change region 131/132/133/134. The heating control switch 152 may be a field effect transistor, for example, a MOS transistor, and the gate of the field effect transistor 152 may be electrically connected to the electronic unit 152. When receiving a turn-on signal (e.g., voltage) input by the power supply unit 152 through the gate, the fet 152 is turned on, otherwise, it is turned off.
In some embodiments, as shown in fig. 4, the first electrode 11 and the second electrode 12 may be electrically connected to a first terminal 16 and a second terminal 17, respectively, and the first terminal 16 and the second terminal 17The terminal 17 may form a first current path L1 through the phase-change memory layer 13. In one operation mode, the resistance of the phase change memory layer 13 may be detected through the first current path L1 described above to perform a reading process of data. Taking the example that the number of the phase change regions 131/132/133/134 is 4 and the volume sizes of the 4 phase change regions 131/132/133/134 are all different, as shown in table 1 below, the 4 phase change regions 131/132/133/134 may be numbered 1, 2, 3 and 4 in sequence, and correspondingly, the phase change memory layer 13 may have 24That is, 16 different resistance states R, which may be sequentially numbered R1-R16. Among them, the high resistance value phase state of the phase change region 131/132/133/134 may represent data "0" and the low resistance value phase state may represent data "1", thereby enabling the storage of a 4-bit binary number as shown in table 1 below by the phase change memory layer 13.
The phase change regions with different volumes have different resistance values in a high resistance value phase state, and the phase change regions with different volumes have different resistance values in a low resistance value phase state.
TABLE 1
Specifically, as shown in fig. 5, the first electrode 11 may be electrically connected to a bit line BL of a peripheral logic circuit via the first terminal 16. The phase change memory 10 may further include a read control switch 18 (a structure within a dashed line frame in the figure) electrically connected to the second electrode 12, and the peripheral logic circuit may be configured to apply a voltage to the phase change memory layer 13 through a first current path L1 when the read control switch 18 is turned on, so as to read data stored in the phase change memory layer 13, wherein the first current path L1 passes through the first electrode 11 and the second electrode 12, and does not pass through the heater 141/142/143/144. In addition, in the implementation, with reference to fig. 5, the read control switch 18 may be a field effect transistor 181, such as a MOS transistor, and a gate of the field effect transistor 181 may be electrically connected to a word line WL of the peripheral logic circuit. One of a source and a drain of the field effect transistor 181 may be electrically connected to the second electrode 12, and the other may be grounded. When the fet 181 receives a turn-on signal (e.g., a voltage) input from the peripheral logic circuit through the gate thereof, the fet 181 is turned on, and otherwise, is turned off.
In some embodiments, with continued reference to fig. 5, when the heater 141/142/143/144 is located on the side surface 13C of the phase change memory layer 13 and contacts the corresponding phase change region 131/132/133/134, the heater 14 may be electrically connected to the control unit 15 through a second current path L2. Wherein the second current path L2 passes through the phase change memory layer 13. In a specific implementation, the second current path L2 may sequentially pass through the control unit 15, the heater 14, the phase change memory layer 13, and the second electrode 12. Also, in an operation mode, the control unit 15 may provide a corresponding driving signal to the heater 141/142/143/144 through the second current path L2 to drive the heater 141/142/143/144 to heat the corresponding phase change region 131/132/133/134, thereby writing data into the phase change memory layer 13. For example, the control unit 15 may provide a large or medium pulse current to the heater 141/142/143/144 via the second current path L2 to drive the heater 141/142/143/144 to heat the corresponding phase change region 131/132/133/134, thereby switching the phase state of the phase change region 131/132/133/134 between the amorphous phase and the crystalline phase.
In some alternative embodiments, as shown in fig. 6, when the heater 141/142/143/144 is located on the side surface 13C of the phase change memory layer 13 and is not in contact with but close to the corresponding phase change region 131/132/133/134, the heater 141/142/143/144 may be electrically connected to the control unit 15 through a third circuit path L3. The third circuit path L3 does not pass through the phase change memory layer 13. Specifically, the above-described third current path L3 may sequentially pass through the control unit 15, the input terminal (e.g., heating anode) of the heater 141/142/143/144, and the output terminal (e.g., heating anode) of the heater 141/142/143/144, and the output terminal of the heater 141/142/143/144 may be grounded. Also, in an operation mode, the control unit 15 may provide a corresponding driving signal to the heater 141/142/143/144 through the third current path L3 to drive the heater 141/142/143/144 to heat the corresponding phase change region 131/132/133/134, thereby writing data into the phase change memory layer 13. For example, the control unit 15 may provide a large or medium pulse current to the heater 141/142/143/144 via the third current path L3 to drive the heater 141/142/143/144 to heat the corresponding phase change region 131/132/133/134, thereby switching the phase state of the phase change region 131/132/133/134 between the amorphous phase and the crystalline phase.
In this way, the data writing process and the data reading process of the phase change memory 10 are respectively performed through the two independently controlled current paths, so that the problem that the data writing process and the data reading process cannot be performed and the problem that the data reading cannot be performed simultaneously when the current paths are open due to the fact that the data writing process and the data reading process are performed through the same current path in the prior art can be avoided.
In one embodiment, as shown in fig. 7, the phase change memory 10 may further include an isolation layer 19, and the isolation layer 19 may be disposed between the first electrode 11 and the second electrode 12 and may be located on the side surface 13C of the phase change memory layer 13. The heater 141/142/143/144 may be at least partially embedded in the isolation layer 19. The isolation layer 19 may electrically isolate the heater 141/142/143/144 from the first electrode 11 and the heater 141/142/143/144 from the second electrode 12. The material of the isolation layer 19 may be an electrically insulating material such as silicon dioxide or silicon nitride.
In the above embodiments, the first electrode 11 and the second electrode 12 may have a sheet structure, and may include a low resistance material, for example, one or more of metal or semiconductor materials such as tungsten, cobalt, copper, aluminum, silicide, and the like. The plurality of phase change regions 131/132/133/134 in the phase change memory layer 13 may be electrically connected to the remaining portion in the phase change memory layer 13, and the resistance of the remaining portion may remain unchanged during data writing and data reading operations of the phase change memory 10, and thus, the change in resistance of the phase change memory layer 13 may be determined by the change in resistance of the phase change region 131/132/133/134, that is, the phase change of the phase change region 131/132/133/134. In addition, the phase change regions 131/132/133/134 in the phase change memory layer 13 may be arranged at intervals around the middle region of the phase change memory layer 13, and any two phase change regions 131/132/133/134 in the phase change memory layer 13 may not overlap, so as to ensure that the phase change regions 131/132/133/134 can be well thermally isolated, and further ensure that the phase change regions 131/132/133/134 do not affect the phase states of other phase change regions 131/132/133/134 when being heated to cause a phase change, thereby improving the security of data storage.
Different from the prior art, the phase change memory in this embodiment includes a first electrode, a second electrode, a phase change memory layer, a plurality of heaters, and a control unit, where the phase change memory layer is located between the first electrode and the second electrode and is electrically connected to the first electrode and the second electrode, the control unit is electrically connected to the plurality of heaters respectively for providing driving signals to the heaters, the plurality of heaters are adjacent to different phase change regions of the phase change memory layer respectively, and each heater is configured to heat the adjacent phase change region under the driving of the driving signals, so that multi-value storage of a single memory cell can be achieved, and storage density of the phase change memory is improved.
Referring to fig. 8, fig. 8 is a flowchart illustrating a memory control method according to an embodiment of the present disclosure. The memory control method is applied to the phase change memory of any one of the embodiments, wherein the phase change memory includes a first electrode, a second electrode, a phase change memory layer, a plurality of heaters, and a control unit. The phase change memory layer is located between the first electrode and the second electrode and is electrically connected with the first electrode and the second electrode respectively. The control unit is electrically connected with the heaters respectively and used for providing driving signals for the heaters. The plurality of heaters are respectively adjacent to different phase change areas of the phase change storage layer, and each heater is configured to heat the adjacent phase change area under the driving of a driving signal. The description of the phase change memory has been described in detail in the above embodiments, and is not repeated here.
As shown in fig. 8, the memory control method includes the steps of:
step S81: a first instruction to write data is received by a control unit.
Step S82: in response to the first instruction, a drive signal is output to each heater by the control unit.
In one embodiment, the memory control method may further include:
step S83: a second instruction to read data is received by the peripheral logic circuitry.
Step S84: in response to a second instruction, a voltage is output to the first electrode and the second electrode through the peripheral logic circuit.
Specifically, the driving signals provided by the control unit to the different heaters may be the same or different. And, the driving signal corresponding to each heater may be preset by the developer according to the actual storage requirement. In addition, during the implementation, in the using process of the phase change memory, research personnel can update the driving signals corresponding to the heaters when the actual storage requirements change, so as to meet diversified storage requirements.
It should be noted that, in the present embodiment, reference may be made to the description of the control unit, the heater, the driving signal, the peripheral logic circuit, the first electrode, and the second electrode in the phase change memory embodiment, and therefore details are not repeated herein.
Different from the prior art, in the memory control method in this embodiment, the control unit receives the first instruction for writing data, and outputs the driving signal to each heater through the control unit in response to the first instruction, so that multi-value storage of a single storage unit can be realized, and the storage density of the phase change memory can be further improved.
Accordingly, an embodiment of the present application further provides a memory chip, where the memory chip includes a memory array, and the memory array may include an array formed by the phase change memory according to any of the above embodiments.
Specifically, the phase change memory may include a first electrode, a second electrode, a phase change memory layer, a plurality of heaters, and a control unit. The phase change memory layer is located between the first electrode and the second electrode and is electrically connected with the first electrode and the second electrode respectively. The control unit is electrically connected with the heaters respectively and used for providing driving signals for the heaters. The plurality of heaters are respectively adjacent to different phase change areas of the phase change storage layer, and each heater is configured to heat the adjacent phase change area under the driving of a driving signal.
Different from the prior art, in the memory chip in the embodiment, the control unit is electrically connected to the plurality of heaters respectively for providing the driving signal to the heaters, the plurality of heaters are respectively adjacent to different phase change regions of the phase change memory layer, and each heater is configured to heat the adjacent phase change region under the driving of the driving signal, so that the multi-value storage of a single memory cell can be realized, and the storage density of the phase change memory can be further improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (13)
1. The phase change memory comprises a first electrode, a second electrode, a phase change memory layer, a plurality of heaters and a control unit; wherein the content of the first and second substances,
the phase change storage layer is positioned between the first electrode and the second electrode and is electrically connected with the first electrode and the second electrode respectively;
the control unit is electrically connected with the heaters respectively and is used for providing driving signals for the heaters;
a plurality of the heaters respectively adjoining different phase change regions of the phase change memory layer, each of the heaters being configured to heat the adjoining phase change region under the driving of the driving signal.
2. The phase change memory according to claim 1, wherein the phase change regions adjacent to each of the plurality of heaters include at least two target phase change regions having different volume sizes.
3. The phase change memory according to claim 2, wherein heating areas of the heaters to which at least two of the target phase change regions are adjoined are different such that volumes of the at least two of the target phase change regions are different in size.
4. The phase change memory according to claim 3, wherein the plurality of heaters have a columnar or rectangular parallelepiped shape, and at least two of the target phase change regions are different in area from the heater adjacent thereto.
5. The phase change memory according to claim 2, wherein at least two of the target phase change regions are heated by the heater in a different period of time so that the volumes of the at least two target phase change regions are different in size.
6. The phase change memory according to claim 2, wherein powers of driving signals of the heaters to which at least two of the target phase change regions are adjoined are different such that volumes of at least two of the target phase change regions are different in size.
7. The phase change memory according to claim 1, wherein the phase change memory layer has an upper surface, a lower surface, and a side surface between the upper surface and the lower surface,
the phase change storage layer is electrically connected with the first electrode through the upper surface and is electrically connected with the second electrode through the lower surface;
a plurality of the heaters adjoining the phase change region through the side surface.
8. The phase change memory according to claim 7, further comprising an isolation layer disposed on the side surface, the heater being at least partially embedded in the isolation layer, the isolation layer electrically isolating the heater from the first electrode and the heater from the second electrode.
9. The phase change memory according to claim 1, wherein the control unit includes a power supply unit and a plurality of heating control switches, wherein each of the heaters is electrically connected to the power supply unit through one of the heating control switches;
the power supply electronic unit is configured to provide the driving signal to the corresponding heater through the heating control switch when the heating control switch is turned on.
10. The phase change memory according to any one of claims 1 to 9, wherein no two of the phase change regions in the phase change memory layer overlap.
11. The phase change memory according to any one of claims 1 to 9, wherein the first electrode is electrically connected to a bit line, and the phase change memory further comprises a read control switch electrically connected to the second electrode.
12. A memory control method applied to the phase change memory according to any one of claims 1 to 11, the method comprising:
receiving, by the control unit, a first instruction to write data;
outputting, by the control unit, a drive signal to each of the heaters in response to the first instruction.
13. A memory chip comprising a memory array, wherein the memory array comprises an array of phase change memories according to any one of claims 1 to 11.
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