CN1120779A

CN1120779A - Image plane generating circuit

Info

Publication number: CN1120779A
Application number: CN 94118654
Authority: CN
Inventors: 樋口善男
Original assignee: Funai Electric Co Ltd
Current assignee: Funai Electric Co Ltd
Priority date: 1994-10-11
Filing date: 1994-10-11
Publication date: 1996-04-17

Abstract

The circuit can display gray background as picture on screen when there is not image signals if video recorder is used for replay or tuner is used to select TV station. It is composed of signal discriminator for judging whether there is complex signals, analog horizontal synchronous signal generator that takes its action if there is not complex signals, and signal processing circuit for generating gray background on screen according to said analog horizontal synchronous signal.

Description

Image plane generating circuit

The present invention relates to not produce when input composite signal (vision signal) not the Image plane generating circuit of ugly noise picture, this circuit is the circuit that is incorporated with the receiver of display frame in being suitable for or connects the equipment of those receivers.

During from the video tape video reproduction or when tuner receives channel selection, if there is not picture signal, the noise image that is difficult to see will appear with original video tape recorder in the display frame.

For this reason, be to produce the vision signal that display frame becomes blue look without picture signal when from the video tape video reproduction time or with tuner, receiving channel selection to output to display unit if a kind of device is arranged to replace ugly noise picture.

Fig. 6, Fig. 7 show the prior art example, and wherein 60 is tuners of received television signal; The 61st, from the outer input of the TV signal of video camera etc.; The 62nd, blue look background signal generator; The 63rd, the synchronizing signal separation detecting circuit; The 64th, diverter switch, when not having aforementioned signal in order to coming self-tuner 60 or switching to input from blue look background signal generator from the input of outer input; The 65th, videoblankingsync is separated into the split circuit of brightness signal Y and chrominance signal C; 66,67 is respectively the signal processing circuit of Y and C, the 68th, and the look demodulator circuit; The 69th, matrixer; The 70th, CRT.

Fig. 7 is more detailed to express blue look background signal generator 62, and wherein 80 is synchronous generators, and 80a, 80b, 80c and 80d export compound horizontal-drive signal, blanking pulse, burst gating pulse and subcarrier signal respectively.

The 81st, secondary colour synchronous gate and subcarrier, and the circuit of output burst signal 82; The 83rd, the 3.58MHz band pass filter.The 84th, the add circuit of above-mentioned burst signal 82 and compound horizontal-drive signal 80a addition; The 85th, amplitude adjusting circuit; The 86th, have the composite synchronizing signal of burst signal.

On the other hand, the 87th, the negative circuit of subcarrier 80d; The 88th, the 3.58MHz band pass filter; The 89th, amplitude adjuster; 90 for being equivalent to the colour signal of blue look.

The 91st, have the composite synchronizing signal 86 of burst signal and a switching circuit of blue chrominance signal 90 according to blanking pulse 80 is synthetic; The 92nd, the blue look background signal after synthesizing.

The course of work of Fig. 6 is as described below, come the TV signal of self-tuner or outer input to be input to y/c separation circuit 65 through diverter switch 64, again its television image is outputed to CRT70, if synchronizing signal separation detecting circuit 63 fails to detect synchronizing signal separation, just diverter switch 64 is transformed into blue look background signal generator 62 as no TV signal input.

The course of action (see figure 7) of this blue look background signal generator 62 is described below, at first burst gating pulse 80C and the subcarrier 80d that synchronous generator 80 is produced synthesizes, and more compound horizontal-drive signal is added in the composite synchronizing signal 86 that obtains having burst signal on the aforementioned signal.Then the phasing back of the subcarrier 80d of synchronous generator 80 generations is formed blue chrominance signals 90 for 180 °.For blue chrominance signal 90 is synthesized on composite synchronizing signal 86, use the blanking pulse 80b that produces by synchronous generator 80 to synthesize, the result exports blue look background signal 92.

The problem that above-mentioned video tape recorder exists is signal processing circuit complexity and a cost height of display frame being made the picture signal on blue look background for producing, thereby the price of video tape recorder is improved.

The present invention will eliminate above-mentioned problem, its objective is provides a kind of inexpensive Image plane generating circuit, if when sort circuit receives channel selection in the video tape video reproduction or with tuner because unwritten image and not video reproduction or do not receive picture signal, can make gray background to display frame, i.e. grey.

Image plane generating circuit involved in the present invention is had or not the signal identification device of composite signal, produces the dummy level synchronization signal generating apparatus of the horizontal-drive signal of simulating when aforementioned signal identification device does not detect aforementioned composite signal and according to the dummy level synchronizing signal generation that aforementioned dummy level synchronization signal generating apparatus produces the signal processing circuit of the composite signal of display frame grey is constituted by differentiation.

Use Image plane generating circuit of the present invention, if do not have picture signal to emit or do not receive signal when receiving channel selection when video replay band image or with tuner, display frame can not form ugly noise picture with regard to becoming to the gray background picture so.

Fig. 1 is the block diagram of the Image plane generating circuit of embodiments of the invention;

Fig. 2 is the oscillogram of dummy level synchronizing signal of output interface end output of the microcomputer of the embodiment of the invention;

Fig. 3 is the signal waveforms that the character input 2a of the y/c signal treatment circuit 2 of the embodiment of the invention is imported;

Fig. 4 is the gray background vision signal input-output characteristic figure to the character input 2a in the y/c signal treatment circuit of the present invention;

Fig. 5 is the structure chart of the synchronous detailed Image plane generating circuit of dummy level of the present invention;

Fig. 6 is original Image plane generating circuit figure

Fig. 7 is original Image plane generating circuit figure.

Embodiments of the invention are described with reference to the accompanying drawings.

Fig. 1 is the block diagram that the embodiment of Image plane generating circuit used in the video tape recorder constitutes.

Among Fig. 1, the 1st, control circuit; 1a is arranged in the control circuit 1 in order to judge whether to contain the signal supervisory instrument of composite signal; 1b is arranged on the dummy level synchronization signal generating apparatus in the control circuit 1, in order to the roughly the same dummy level synchronizing signal of generation and output and horizontal-drive signal when signal supervisory instrument 1a does not detect composite signal; 1C is arranged on control circuit 1 interior input in order to the composite signal of input after the A/D conversion, and 1d is the output of output by the dummy level synchronizing signal of dummy level synchronization signal generating apparatus 1b generation.

R1 and R2 are the resistance that level translation is used, and resistance R 1 is connected between 5V power line and the output 1d, and resistance R 2 is connected between output 1d and the ground.

2. be the y/c signal treatment circuit that carries out the recording playback signal processing of brightness signal Y and carrier chrominance signal C, it uses comparatively cheap IC.There is one to possess the input shown in Fig. 4 among this IC to the video output characteristic of character input voltage.

When the input control voltage of the character input of this y/c signal treatment circuit 2 is 5V, be output as sync level; During for 3.5V, be output as the blanking signal level; When adding the control voltage of 1.5-2V, what obtain is the luminance signal of the gray level in the middle of blanking signal level and white level roughly.

Below illustrated with regard to its action.

When the composite signal of process A/D conversion was input to control circuit 1, signal supervisory instrument 1a judgement had or not composite signal, does not have composite signal if be judged as, and control circuit 1 instruction simulation horizontal-drive signal generating means 1b produces the dummy level synchronizing signal.

And, this dummy level synchronizing signal is outputed to the output 1d of control circuit 1, carry out level translation by the dummy level synchronizing signal of output 1d output by the value of R1 and R2.

Deliver to the character input of y/c signal treatment circuit 2 through the dummy level synchronizing signal of conversion.In y/c signal treatment circuit 2 because and have as shown in Figure 4 input-output characteristic between the video output, so produce and the vision signal of the gray level of output shown in Fig. 4 right-hand member with respect to the signal of delivering to the character input.

As a result, when not having composite signal, the display frame of video tape recorder has just become grey screen, thereby can the display noise picture.

And, owing to can change the voltage ratio of the 5V supply voltage of R1 and R2 decision, so can adjust the brightness of gray level.

The generation circuit of the dummy level synchronizing signal in the foregoing description is described now in further detail.

Fig. 5 is the circuit diagram of above-mentioned dummy level synchronous signal generating circuit.

The part identical or suitable with Fig. 1 among Fig. 5 used prosign, and explanation is omitted

Among Fig. 5, the 3rd, microcomputer (CPU); 3a is a dummy level synchronous signal output end mouth; 3b is the output port that only just becomes the L level when gray background; 3C is the input port of input composite signal.

In addition, D3 is a diode, and R3, R4 are resistance, and Tr is the H of corresponding output port 3b, the ON/OFF transistor of L level.

In y/c signal treatment circuit 2,2a is character input (a literal insertion terminal), and it is the composite signal output of handling that the dummy level synchronizing signal is input to this input 2b, and it also is the gray background VT.2C is the composite signal input.

Below be illustrated with regard to its action.

Microcomputer 3 is input to input port 3C to signal from the composite signal output circuit, and detection has or not composite signal.

If judging does not have composite signal, microcomputer 3 just outputs to dummy level synchronizing signal shown in Figure 2 on its output port 3a.

Among Fig. 2, the cycle of synchronizing signal is 64 μ S, the H level (being about 5V) of 4 μ S width, the 4 μ S width that join with it is arranged as high impedance status in each cycle, and all the other times are L level (about 0V).

On the other hand, export the L level simultaneously on the output port 3b of microcomputer 3, transistor Tr is by (OFF).

Wherein, when output port 3a was the L level, 5V voltage was input to input 2a by the parallel resistance dividing potential drop of resistance R 1 and resistance R 2 and resistance R 3.

And when output port 3a was high impedance, 5V voltage was input to input 2a by resistance R 1 and resistance R 2 dividing potential drops.

When output port 3a was the H level, 5V voltage was input to input 2a.

If select the value of resistance R 1, R2, R3, can be input to dummy level synchronizing signal shown in Figure 3 character input 2a.

That is: the voltage waveform of 1 cycle, the 64 μ S of dummy level synchronizing signal can be the wide 5V of 4 μ S, then be the wide 3V of 4 μ S all the other for 2V.

If above dummy level synchronizing signal is input to the character input 2a of y/c signal treatment circuit 2, from the output 2b gray background vision signal of output voltage waveform as shown in Figure 4 just.

On the other hand, when microcomputer 3 detects composite signal, output port 3a output L level.Simultaneously, output port 3b output H level, transistor Tr conducting (ON).Thus, the terminal 1d of control circuit 1 is near OV.The character input 2a of y/c signal treatment circuit 2 is delivered in this output.As shown in Figure 4, because voltage at this moment is lower than 1.1V fully, so y/c signal treatment circuit 2 is handled the composite signal that input 2C receives from tuner, and outputs to output 2b.

Though be that circuit of the present invention has been described at the center with the interior example that is loaded on video tape recorder in an embodiment, certainly sort circuit also can in be loaded on image replaying machine different or television receiver etc. and have in the machine of display frame with video tape recorder etc., need not to explain again.

If adopt aforesaid the present invention, when receiving channel selection during with the video tape recorder video reproduction or with tuner, do not having under the situation of picture signal, can do to become gray background to display frame with low cost.

Claims

1. an Image plane generating circuit is characterized in that signal identification device, dummy level synchronization signal generating apparatus that produces the dummy level synchronizing signal when aforementioned signal identification device does not detect aforementioned composite signal that this circuit is had or not by the differentiation composite signal and the signal processing circuit of the composite signal of grey being made in display frame according to the aforementioned dummy level synchronizing signal generation that aforementioned dummy level synchronization signal generating apparatus produces constitute.