CN1416271A - Device for stabilizing composite video output signal - Google Patents
Device for stabilizing composite video output signal Download PDFInfo
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- CN1416271A CN1416271A CN 02144912 CN02144912A CN1416271A CN 1416271 A CN1416271 A CN 1416271A CN 02144912 CN02144912 CN 02144912 CN 02144912 A CN02144912 A CN 02144912A CN 1416271 A CN1416271 A CN 1416271A
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Abstract
Changing the frequency of the reference clock of the displaying frames and changing the output phase of the composite video frequency chrominance pulse train realize the stability of the output signal of the composite video frequency. The invention consists of following parts: The MPEG decoder decodes the MPEG video and collects the frame information. The multifunctional unit inserts the OSD to the frame information as well as converts the outputs signal to the formatted frame preset. The formatter for displaying framke outputs the signal of frames according to its component. The NTSC encoder converts the signal to the NTSC composite video signal.
Description
Technical field
The invention belongs to the digital circuit technique field, specifically mainly discussed the stabilizing arrangement relevant issues of composite video output signal in Digital Television.
Background technology
For meeting the arrival in digital and electronic epoch, various countries are developing many Digital Television series with set-top box.The Digital Television of North America is supported 18 kinds of pattern of the inputs in ATSC (digital television standard of the U.S.) standard, but display format limits four kinds of forms at most.
In high definition TV (HD level) output format, pixel count adopts interlace mode up to 1920 * 1080; Pixel count is that 1280 * 720 TVs adopt progressive scan mode.In the clear main TV of standard (SD level) pattern of the input, pixel count is 720 * 480, adopts progressive scan mode and interlace mode.The display unit of current main exploitation and Digital Television, its pixel count are 1920 * 1080 high definition TV (HD level), and scan mode mainly adopts interlacing scan.With the Digital Television set-top box series that various exterior display devices are supported, when exploitation, all support above-mentioned four kinds of pattern of the inputs.Present four kinds of forms mainly are used on the ultrahigh resolution Digital Television, and the composition output format is as interface.
Composition output is by synchronizing signal and comprise the luminance signal (y) of monochrome information and the color difference signal of chrominance information is formed, and output reference RGB supervision, is RGB, horizontal-drive signal and the vertical synchronizing signal of interface.
Up to the present, popularize maximum still simulated televisions as the map medium, the Digital Television of super definition, the quantity of popularizing is few now.In the current Digital Television series of products with set-top box that provide, basic still simulated television will make its digitlization, must will be provided with in simulated television and the outside interface that is connected, and could realize television digitization by interface.According to this needs and be the output of standard definition television (SD level) composite video signal, this TV is set up encoder in addition.
The current multiple Digital Television series of products that provide.Come designing image output if input information changes, when then exporting synchronous and chroma stability, follow input frame speed to change and the generation transitional period; On the contrary, when input information changes, independently form image output, then follow frame rate and flash, this situation to cause that repeatedly moving image frame becomes undesired.For reducing this undesired many frame memories that need to increase.
From last analysis as can be known, said method one is to set up encoder; The 2nd, increase memory.This defective is impelled the method for seeking the stable composite video output signal that has nothing to do with input video stream explanation degree and frame-rate conversion.
Summary of the invention
The objective of the invention is for digital television series product being provided the stabilizing arrangement of composite video output signal.For satisfying this demand, the present invention changes the display frame clock for determining output frame speed at output show image picture field blanking interval; In output show image frame blanking interval (VBI), follow the display frame reference clock to change and change and export composite video colourity pulse train phase place simultaneously, so just guaranteed the stable output composite video signal of interactive input stream.
This method makes Digital Television under the situation that the input stream frame-rate conversion has nothing to do, and not only stable generation output is synchronous, and guarantees stable realization output colourity reproduction.Also the people makes output signal transitional period and the colourity reproduction transitional period shortening of following the frame-rate conversion generation or minimizes simultaneously.
The present invention in output show image picture field blanking section, changes the pulse of show image picture reference clock for determining output frame speed; The transitional period instability that removing follows input stream frame-rate conversion and output signal frame-rate conversion to produce.According to the input stream frame rate, the colourity pulse train phase place of compensation output composite signal; Poor according to the input and output frame rate, eliminate colourity and reappear error.Change according to the output frame speed display frame reference clock of determining, in output display field blanking zone, change the colourity pulse train phase place of output composite signal, can not occur reappearing the wrong transitional period because of input information frame rate signal colour fidelity thereby reach.
This device is made up of following part:
The periodic mpeg decoder of gathering the frame rate information in the input stream; According to the frame information that mpeg decoder is extracted out, the show image picture processor of processing or output video image frame information; Above-mentioned video image frame information is converted to the formative display format device of display frame (Disply Formatter) by HD/SD level of having set and interlaced/progressive scan mode etc.; The output signal of display format device is pass on parallel operation by first analog/digital that composition is converted to analog video signal; Above-mentioned video image frame information is converted to the NISC encoder (NTSC ENCODE ER) of NTSC composite video signal; The output signal of NTSC encoder is converted to second digital/analog converter of analog video composite video signal; Frame rate information in the frame information of gathering above outputed to show that picture shows the clock switch loop of formatter and NTSC formatter etc.
The clock switch loop is made up of following part:
Produce the generator of system clock; The display frame reference clock switch synchronous with display frame; Be the compensation of colourity burst frequencies, with the clock converter of above-mentioned system clock by set point requirement conversion; Converted clock is selected the multi-function device of one in system clock and above-mentioned clock converter; The conversion initial point of display frame reference clock, and change according to the display frame clock and will in output picture field blanking district, form the colourity pulse train phse conversion of output composite signal, according in system clock and variation clock, selecting one, send the compositions such as display frame sync break service routine portion of control signal to Port Multiplier according to the frame rate of extracting out in the Video Decoder for this reason.
The design feature of this device: the one, correctly determined the zero-time that the display frame reference clock changes; The 2nd, in the ground vertical scanning section, choose reasonable output composite video colourity pulse train phase change; The 3rd, reasonably designed the video pictures processor of machining information on request and NTSC encoder etc.This device structure characteristics have well realized functions of the equipments.
Description of drawings
Below in conjunction with accompanying drawing the present invention is elaborated:
Fig. 1 is for implementing the block diagram of apparatus of the present invention;
Fig. 2 is the timing ratio signal flow graph of extracting out from mpeg decoder;
Fig. 3 is clock switch loop feature embodiment;
Fig. 4 is clock switch loop other parts enforcement figure;
Fig. 5 is an action sequence diagram
★ drawing major part symbol description:
The 110:MPEG decoder;
120: video display frame processor;
130: graphic process unit;
140: multi-function device;
150: the display frame formatter;
160.180: digital/analog converter;
The 170:NTSC encoder
Embodiment
Fig. 1 is the block diagram of device, and as seen from the figure, it is that following part is formed: the mpeg decoder (110) of the sex-limited frame rate information of extracting out from the state information of input stream of cycle when the MPEG video stream is decoded; The frame information of mpeg decoder (110) is processed into the video display frame processor (120) of image output frame information; For generating the graphic process unit (130) of OSD (screen display is used); Insert the multi-function device (140) of OSD for frame of video information; Convert multi-function device (140) output signal to display frame formatter (150) that the display frame form of setting is used; Display frame formatter (150) output signal is pass on parallel operation (160) by the digital-to-analog that heterogeneity is converted to vision signal; The output signal of multi-function device (140) is converted to the NTSC encoder (170) of NTSC composite video signal; NTSC encoder (170) output signal is converted to digital/analog converter (180) that analog composite video signal uses etc.
Action and effect thereof to this structure are described as follows:
Outputting video signal after mpeg decoder (110) is decoded video information (ES, PES), video display frame processor (120) forms the video image frame information.And export it to multi-function device (140).At this moment, if graphic process unit (130) generates OSD image video pictures, then multi-function device (140) inserts above-mentioned OSD video image picture to video pictures processor (120), and exports it to display frame formatter (150) or NTSC encoder (170).Meanwhile, display frame formatter (150) receives OSD display frame vision signal on the screen from multi-function device (140), and with its conversion or various display format.That is to say, display frame formatter (150) will be exported the explanation degree, scan mode and output chromaticity coordinates system etc. are converted to HD/SD level signal of video signal, the interlaced/progressive scan mode, (RGB/YPbPr) etc. output format is pressed composition image output video analog signal with switched signal of video signal by digital/analog converter (160).
The output format of regeneration adopts 1920 * 1080 interlacing scans usually in display frame formatter (150), and 1280 * 720 for lining by line scan, and 720 * 480 is interlacing or four kinds of explanation degree that scan and scan mode.Usually select to support the proportionately NYPPR output format of tap face of external equipment, the RGR supervision is the rgb video picture and the level of interface, the output format that vertical synchronization constitutes.
For popularizing now the more benchmark simulation Digital Television series of products that have, display frame formatter (150) is also supported to receive the composite video form and is exported.
NTSC encoder (170) color difference signal (Cbcr) is carried out the orthogonal multi-path conversion, and the relevant chrominance carrier of each pixel modifies tone for making the vision signal conversion or the NTSC composite video variable signal of screen display.
The chrominance signal reference phase subcarrier that modifies tone in NTSC encoder (170) is loaded in edge after the horizontal pulse, Here it is look pulse train, and its fixed frequency is 3.57954MHz, and has the stationary phases of-180 degree.If colourity pulse train phase place is askew, then the color and luster of counter modulation picture is distorted; If frequency changes, cause not only that then bad colour is normal, and colourity can not be recovered former state.
From now on, chrominance signal (C) that NTSC encoder (170) will modulate above and grey scale signal (Y) addition of representing monochrome information will produce composite video signal after loading synchronizing signal simultaneously.This signal is exported analog composite video signal by digital/analog converter (180).
But mpeg decoder (110) is analyzed video stream by the sequence mark, and reads the frame rate that is coded in the sequence mark frame information.Each is read the sequence mark cycle enter video information is upgraded frame information.
Then, mpeg decoder (100) is according to the frame rate of the input information of every sequence mark extraction in input information, and video display frame processor (120) is determined output display frame output frame speed.
Though, to the variation of input frame speed, can generate output display frame output frame information independently, according to the difference of frame rate produce periodic frame flash with repeatedly, this just might produce the mobile variation of picture or undesired.To move the picture that causes undesired in order to reduce the animation face, needs many frame memories.
Simultaneously, from face image frame quality, fixedly input and output frame rate, remove frame flash with repetitive operation be a principle matter
Fig. 3: (ES, frame-rate conversion PES) fix frame rate between input and output by the switchization of exporting display frame reference clock (27MHz), are provided with clock switch loop (300) as shown in the figure for this reason according to enter video information.
In above-mentioned clock switch loop (300), oscillator (310) produces the 27MHz system clock, and exports this clock to multi-function device (330).The clock converter decomposes the system clock frequency of above-mentioned 27MHz by 1001/1000 ratio, and exports the 27.027MHz clock to multi-function device (330).Control multi-function device (330) according to the frame rate of extracting out in the sequence mark.
If input frame speed belongs to 59.94Hz group video, then multi-function device (330) is selected the system clock of the 27MHz of oscillator (310) generation, and will export video display frame processor (120) and NTSC encoder (170) to.
In this case, the 27MHz incoming frequency forms vertically through a minute loop, horizontal timing, and at this moment, vertical frequency is 59.94Hz.
Then, if be input to the reference clock of the DTO that produces the NTSC chrominance subcarrier signal when being 27MHz, the chrominance subcarrier signal of NTSC encoder (170) output 3.579545Hz.
If input frame speed belongs to the video of (60Hz) group, multi-function device (330) is selected the output clock of clock converter (320) of the system clock of conversion 27MHz, and exports it to video display frame processor (120) and NTSC encoder (170).
That is to say,,, and export the clock of 27.02MHZ to multi-function device (330) so clock converter (320) carried out conversion with reference clock by 1000: 1001 because of 59.94Hz is 1000: 1001 to the ratio of 60Hz.Be input to the 27.027MHZ clock of multi-function device (330) above, inputed to display video processor (120) and NTSC encoder (170).
In this case, the incoming frequency of 27.027HZ forms the timing of vertical and horizontal direction through minute loop, and this moment, frequency was 60Hz.
But the DTO input reference clock that produces chrominance subcarrier signal is 27.027MHZ, if therefore there is not the subcarrier frequency compensation, then inevitably produces the chrominance demodulation mistake.
Particularly, the frame information of from sequence mark, extracting out, the initial point and the display frame that form converting frame rate are irrelevant synchronously.Therefore, the transitional period that conversion forms according to clock causes that display frame is unstable synchronously, occurs irregular picture simultaneously.
If comprise in image in the OSD picture, then the synchronous instability of display frame causes that the transition time limit has increased.
For addressing the above problem, the present invention is provided with clock switch loop (400) as shown in Figure 4 simultaneously.Wherein, for the show image picture has adopted the reference clock switch of synchronized show image picture, with encoder compensating clock frequency, it specifies as follows:
At first, mpeg decoder (110) from sequence mark, extract out the input in frame information the time, frame rate is stored in the register temporarily in this frame information.After, clock switch loop (400) assimilates in display frame frame information vertical blanking interval, the frame information that temporarily is stored in depositing is read by display frame assimilation break in service portion this moment (440), and exports the clock selecting control signal to multi-function device (330).
Then, if clock control signal is " 0 ", then multi-function device (430) is selected from the 27MHz system clock of generator (410) generation; If clock control signal is " 1 ", then selects from the 27.027MHz clock of clock converter (420) generation that produces, and export it to video display frame processor (120) and NTSC encoder (170).
Equally, the DTO coefficient that produces the clock subcarrier according to clock frequency assimilates in display frame frame information vertical blanking interval (VBI), and display frame sync break service routine portion (440) exports the colourity pulse signal to video display frame processor (120) and NTSC encoder (170) simultaneously.
Simultaneously, in carrying out said process, the incoming frame information conversion initial point that upgrades according to frame-rate conversion and to the clock pulse frequency conversion initial point of composite image signal assimilates in showing between vertical blanking district (VBI) and realizes comprising OSD in interior image stabilisation.
On the one hand, said process is consistent with as shown in Figure 5 sequence of movement, and it is simply described as follows: at first, mpeg decoder (110) is extracted incoming frame information out from sequence mark, and frame rate is stored in (S501) in the register temporarily in this information.
Then, clock switch loop (400) is shown the synchronization signal assimilation of frame information, display synchronization interrupt service routine portion (440) reads the frame information of storing in the temporary register and judges whether to be 60Hz, determines to export to the clock selecting control signal value (S502) of Port Multiplier (330) according to judged result.
At this moment, if the frame information value that is stored in the register is judged as 60Hz temporarily, and when the clock selecting control signal was " 1 ", then Port Multiplier (330) was selected the 27.027MHz clock and is exported video display frame processor (120) to and NTSC encoder (170) from clock converter (420); It is 60Hz (503) (504) that while audio video synchronization interrupt service routine portion (440) will export control colourity pulse signal.
Simultaneously, if being judged as, the frame information value of storing not 60Hz in register, and the clock selecting control signal is " 0 ", and then Port Multiplier (330) is selected the clock of 27.0MHz from generator (410), and exports display frame processor (120) and NTSC encoder (170) to; Simultaneously display frame sync break service routine portion (440) will export control the colourity pulse signal be 59Hz (S505) (S506).
(among the S503～S506), colourity is selected signal and colourity pulse signal, at each sequence mark readout interval, brings in constant renewal in according to frame information at said process.
Simultaneously, select signal value and colourity pulse signal value according to said process decision colourity.The incoming frame information conversion initial point that is updated according to frame-rate conversion and to the colourity pulse frequency conversion initial point of total image signal, in showing vertical blanking interval (VBI), assimilate (S507) (S508).
In sum, the present invention is shown the display frame reference clock switch of picture synchronizationization and with colourity pulse frequency compensation way, and the reference clock of video display processor (120) and NTSC encoder (170) is changed the problem that the colourity pulse frequency conversion initial point of initial point that face upgrades and the composite image signal that generates assimilates according to the input frame speed that is updated in the mpeg decoder (110) in the demonstration vertical blanking interval from NTSC encoder (170).
Simultaneously, display synchronization unsteadiness that conversion causes according to clock and transitional period and the colourity reproduction transitional period that impulse transfer causes according to colourity form in vertical blanking interval, and therefore, actual image can be expressed as latent fixed.
The invention effect: as above describing in detail, the present invention is exactly to synthetic image output, fixing input The output ratio; Prevent that frame from flashing and repeatedly. Show reference clock switch and encoder, colourity pulse frequency for this reason The rate compensation assimilates in vertical blanking interval, and the demonstration that conversion causes according to clock thus is synchronously unstable The property and transitional period and impulse transfer causes according to colourity colourity reproduce the transitional period at vertical blanking interval (VBI) form in, realize stable thereby stablize the output that comprises OSD.
Claims (2)
1, a kind of stabilizing arrangement with composite video output signal of clock switch, it is characterized in that: digital TV with set-top box, in the time of to the input decoding, the periodic Video Decoder of extracting input frame speed information out, generate the video display frame processor of image frame information according to the frame information of extracting out, with above-mentioned image frame information translation is the HD/SD level, interlaced/progressive scanning sides etc. are by the video image formatter of the display format of having set, the output signal of video image formatter is converted to the 1st digital/analog converter of analog image signal by heterogeneity, image frame signal HTSC is converted to the NTSC encoder of composite image signal, the output signal of encoder is converted to the 2nd digital/analog converter of analog composite signal of video signal, the colourity pulse train phse conversion of the output composite signal that shows the conversion initial point of reference clock and changes according to reference clock forms in exporting the demonstration vertical blanking interval, in the frame information of above-mentioned extraction, export clock to display format device and NTSC formatter according to frame rate for this reason.
2, the stabilizing arrangement of composite video output signal according to claim 1, it is characterized in that: the clock switch device is by the generator that produces clock, be shown the demonstration reference clock switch of assimilation, be the compensation of colourity burst frequencies, system clock is by the clock converter of the requirement conversion of limit value, select the multi-function device of one of them at system clock and clock converter, show reference clock conversion initial point and change the colourity pulse train phse conversion of exporting composite signal and in the vertical blanking interval that output shows, be split into according to its reference clock, for this reason will be according to the frame rate of Video Decoder output, export multi-function device to for selective system clock or conversion clock and with control signal, and have the display synchronization interrupt service routine.
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| CN 02144912 CN1416271A (en) | 2002-12-16 | 2002-12-16 | Device for stabilizing composite video output signal |
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| CN 02144912 CN1416271A (en) | 2002-12-16 | 2002-12-16 | Device for stabilizing composite video output signal |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1961580B (en) * | 2004-06-28 | 2010-04-21 | 英特尔公司 | Power management apparatus, systems, and methods |
| CN101083741B (en) * | 2006-05-29 | 2010-06-16 | 索尼株式会社 | Image display apparatus and method, signal processing apparatus |
| CN101356811B (en) * | 2006-01-05 | 2010-09-29 | 汤姆森特许公司 | Raw mode for vertical blanking internval (VBI) data |
| CN101867758A (en) * | 2009-04-20 | 2010-10-20 | 天津天极视讯科技发展有限公司 | Device and method for realizing conversion process of multiple standard signals |
| CN101316369B (en) * | 2007-05-29 | 2011-08-17 | 索尼株式会社 | Image processing device and method |
-
2002
- 2002-12-16 CN CN 02144912 patent/CN1416271A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1961580B (en) * | 2004-06-28 | 2010-04-21 | 英特尔公司 | Power management apparatus, systems, and methods |
| CN101356811B (en) * | 2006-01-05 | 2010-09-29 | 汤姆森特许公司 | Raw mode for vertical blanking internval (VBI) data |
| CN101083741B (en) * | 2006-05-29 | 2010-06-16 | 索尼株式会社 | Image display apparatus and method, signal processing apparatus |
| CN101316369B (en) * | 2007-05-29 | 2011-08-17 | 索尼株式会社 | Image processing device and method |
| CN101867758A (en) * | 2009-04-20 | 2010-10-20 | 天津天极视讯科技发展有限公司 | Device and method for realizing conversion process of multiple standard signals |
| CN101867758B (en) * | 2009-04-20 | 2014-09-17 | 天津天极视讯科技发展有限公司 | Device and method for realizing conversion process of multiple standard signals |
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