CN112073049A - FPGA-based RS485 interface signal burr eliminating method, receiving method and FPGA - Google Patents
FPGA-based RS485 interface signal burr eliminating method, receiving method and FPGA Download PDFInfo
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- CN112073049A CN112073049A CN202010921627.6A CN202010921627A CN112073049A CN 112073049 A CN112073049 A CN 112073049A CN 202010921627 A CN202010921627 A CN 202010921627A CN 112073049 A CN112073049 A CN 112073049A
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
The invention provides a FPGA-based RS485 interface signal burr eliminating method, which comprises the following steps: for the input signal rxd _ clk _ rx, jitter elimination needs to be performed on the low level of the start bit for a set time length; the debounce duration is represented by the number of cycles of the reference clock clk and is recorded as debounce _ max _ cnt; debounce _ max _ cnt is equal to the debounce time length divided by the reference clock clk clock period; in the period of the debounce _ max _ cnt reference clock clk, if the start bit is always kept at a low level, the start signal is considered to really arrive, and at this time, the indication signal stable _ flg in the FPGA is changed from 0 to 1; at the moment, the state machine enters an initial state from an idle state, otherwise, the state machine is considered to have burrs and is ignored, the indication signal stable _ flg is kept to be 0, and the state machine stays in the idle state. The invention also provides an RS485 interface signal receiving method based on the FPGA. The invention can effectively prevent the external interference on the receiving of the RS485 signal.
Description
Technical Field
The invention relates to a receiving method of an RS485 signal, in particular to a method for eliminating burrs of an RS485 interface signal based on an FPGA and a receiving method.
Background
In the commodity circulation parcel sorting process, need PLC to pass through the accurate transport cart car number that the parcel was located of RS485 interface to the camera, this is also one of the basic condition who ensures that the parcel can be accurate from corresponding feed opening letter sorting. However, the field environment of the sorting center is severe, and five, six or even more trolleys exist in one line of the large-scale sorting center, so that the length of an RS485 cable line can be more than 100 meters or even longer, and external electromagnetic interference RS485 signals are easy to cause, and the normal receiving of the trolley numbers is influenced.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides an RS485 interface signal burr eliminating method based on an FPGA, a receiving method and the FPGA, which can eliminate the influence of burrs on RS485 signal receiving to a certain extent, reasonably set the signal sampling process and ensure the accurate sampling of data bits of an RS485 signal.
In a first aspect, an embodiment of the present invention provides a method for removing glitches on an RS485 interface signal based on an FPGA, including:
for the input signal rxd _ clk _ rx, jitter elimination needs to be performed on the low level of the start bit for a set time length; the debounce duration is represented by the number of cycles of the reference clock clk and is recorded as debounce _ max _ cnt; debounce _ max _ cnt is equal to the debounce time length divided by the reference clock clk clock period; in the period of the debounce _ max _ cnt reference clock clk, if the start bit is always kept at a low level, the start signal is considered to really arrive, and at this time, the indication signal stable _ flg in the FPGA is changed from 0 to 1; at the moment, the state machine enters an initial state from an idle state, otherwise, the state machine is considered to have burrs and is ignored, the indication signal stable _ flg is kept to be 0, and the state machine stays in the idle state.
Further, when stable _ flg =1 or the state machine is in the start state, the glitch occurring in the start bit is not processed any more.
In a second aspect, an embodiment of the present invention provides an RS485 interface signal receiving method based on an FPGA, including:
setting a reference clock clk, wherein the frequency of the reference clock clk is 50 MHz-200 MHz;
setting a sampling signal baud _ x16_ en, wherein the frequency of the sampling signal baud _ x16_ en is 16 times of the baud rate of the RS485 signal, and the high level of one reference clock clk period is kept and only kept in each period of the sampling signal baud _ x16_ en;
when baud _ x16_ en is high, one sample position for each bit of the RS485 signal;
the input RS485 signal ser _ in is synchronously received twice by using a reference clock and then is recorded as an input signal rxd _ clk _ rx;
setting a sampling count signal over _ sample _ cnt, which counts down by 1 every time baud _ x16_ en =1 during one bit of the RS485 signal, and the initial value is 15;
setting an over _ sample _ cnt _ done signal whose value is 1, which indicates that the sampling number is full, in other words, if and only if over _ sample _ cnt =0, then over _ sample _ cnt _ done = 1;
using the method as described above to perform debouncing treatment; the state machine directly enters the data state on condition that over _ sample _ cnt =0, i.e., over _ sample _ cnt _ done =1 and baud _ x16_ en =1 are satisfied;
each data bit following the start bit is sampled once every baud _ x16_ en =1 when over _ sample _ cnt ≧ 2, and the counter bit _ value1_ cnt is incremented by 1 when the value of the sample is "1", the counter bit _ value0_ cnt is incremented by 1 when the value of the sample is "0", so that 14 consecutive samples are taken during one data bit; when over _ sample _ cnt =1 and baud _ x16_ en =1, the sizes of bit _ value1_ cnt and bit _ value0_ cnt are compared, when bit _ value0_ cnt is larger, the final value of the data bit is "0", and when bit _ value1_ cnt is larger, the final value of the data bit is "1".
Further, all data bits of one data frame are received completely, and the valid data bit reception end flag bit _ cnt _ done = 1;
when over _ sample _ cnt _ done =1 and bit _ cnt _ done =1 and baud _ x16_ en =1, the state machine enters the stop state from the data state.
Further, in the stop state, when over _ sample _ cnt =3 and baud _ x16_ en =1, the state machine enters the idle state from the stop state, and is ready to receive the next frame data frame.
In a third aspect, an embodiment of the present invention provides an FPGA, where an operation logic is solidified inside the FPGA, and when the operation logic is executed, the steps of the method described above are implemented.
The invention has the advantages that:
1) and (4) eliminating jitter for a set time length on the low level of the start bit, and preventing external electromagnetic interference RS485 signals from being received.
2) The process of receiving the RS485 signal is scientifically designed, and each data bit of the RS485 signal can be accurately obtained.
Drawings
Fig. 1 is a schematic diagram of a reference clock clk and a sampling signal baud _ x16_ en according to an embodiment of the present invention.
Fig. 2a is a schematic diagram of a front part of one bit of an RS485 signal in the embodiment of the present invention.
Fig. 2b is a rear part schematic diagram of one bit of an RS485 signal in the embodiment of the present invention.
Fig. 3 is a diagram illustrating a serial data frame format of an RS485 signal according to an embodiment of the invention.
Fig. 4 is a state transition diagram of a signal receiving side according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The embodiment of the invention provides an RS485 interface signal burr eliminating method based on an FPGA, which comprises the following steps:
setting a reference clock clk, wherein the frequency of the reference clock clk is recommended to be 50 MHz-200 MHz; in this example 50 MHz;
in this example, the baud rate of the RS485 signal is 19200;
setting a sampling signal baud _ x16_ en, wherein the frequency of the sampling signal baud _ x16_ en is 16 times of the baud rate of the RS485 signal, and the high level of one reference clock clk period is maintained and only maintained in each period of the sampling signal baud _ x16_ en, as shown in fig. 1;
as shown in fig. 2a and 2 b;
one sample position for each bit (bit) of the RS485 signal when baud _ x16_ en is high;
the input RS485 signal ser _ in is synchronously received twice by using a reference clock (commonly called as two beats) and then is recorded as an input signal rxd _ clk _ rx; to prevent meta-stability; as in FIG. 2a, the rxd _ clk _ rx signal is delayed relative to the ser _ in signal by two reference clock clk cycles;
setting a sampling count signal over _ sample _ cnt, which counts down by 1 every time baud _ x16_ en =1 during one bit of the RS485 signal, and the initial value is 15;
setting an over _ sample _ cnt _ done signal whose value is 1, which indicates that the sampling number is full, in other words, if and only if over _ sample _ cnt =0, then over _ sample _ cnt _ done = 1;
serial data frame format of RS485 signal see fig. 3; one data frame of the RS485 signal comprises 1 start bit, 8 data bits and 1 stop bit;
for the input signal rxd _ clk _ rx, jitter elimination needs to be performed on the low level of the start bit for a set time length; the debounce duration is represented by the number of cycles of the reference clock clk and is recorded as debounce _ max _ cnt; debounce _ max _ cnt is equal to the debounce time length divided by the reference clock clk clock period, e.g. debounce time length 0.5 μ s, if clk is 50MHz, 0.5 μ s is 25 clk clock periods, i.e. debounce duration debounce _ max _ cnt = 25; in the period of the debounce _ max _ cnt reference clock clk, if the start bit is always kept at a low level, the start signal is considered to really arrive, and at this time, the indication signal stable _ flg in the FPGA is changed from 0 to 1; at the moment, the state machine enters an initial state from an idle state, otherwise, the state machine considers that burrs exist and are ignored, the indicating signal stable _ flg is kept to be 0, and the state machine stays in the idle state; as shown in fig. 4;
after the indication signal stable _ flg =1, a glitch may occur again, so that the start bit level check of the input signal rxd _ clk _ rx is not performed after the start state is entered; that is to say, when stable _ flg =1 or the state machine is in the initial state, the glitch occurring at the initial bit is not processed any more; but rather the state machine goes directly to the data state on condition that over _ sample _ cnt =0 (i.e., over _ sample _ cnt _ done = 1) and baud _ x16_ en =1 are satisfied;
each data bit following the start bit is sampled once every baud _ x16_ en =1 when over _ sample _ cnt ≧ 2, and the counter bit _ value1_ cnt is incremented by 1 when the value of the sample is "1", the counter bit _ value0_ cnt is incremented by 1 when the value of the sample is "0", so that 14 consecutive samples are taken during one data bit; when over _ sample _ cnt =1 and baud _ x16_ en =1, the sizes of bit _ value1_ cnt and bit _ value0_ cnt are compared, when bit _ value0_ cnt is larger, the final value of the data bit is "0", and when bit _ value1_ cnt is larger, the final value of the data bit is "1";
all data bits (8 bits) of one data frame are received end, and the valid data bit reception end flag bit _ cnt _ done = 1;
when over _ sample _ cnt _ done =1, bit _ cnt _ done =1, and baud _ x16_ en =1, the state machine enters a stop state from the data state;
in the stop state, when over _ sample _ cnt =3 and baud _ x16_ en =1, the state machine enters the idle state from the stop state, and is ready to receive the next frame data frame in advance.
The method is realized based on the FPGA, the interior of the FPGA is solidified with operation logic, and when the operation logic is executed, the steps of the method are realized.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (6)
1. An RS485 interface signal burr eliminating method based on FPGA is characterized by comprising the following steps:
for the input signal rxd _ clk _ rx, jitter elimination needs to be performed on the low level of the start bit for a set time length; the debounce duration is represented by the number of cycles of the reference clock clk and is recorded as debounce _ max _ cnt; debounce _ max _ cnt is equal to the debounce time length divided by the reference clock clk clock period; in the period of the debounce _ max _ cnt reference clock clk, if the start bit is always kept at a low level, the start signal is considered to really arrive, and at this time, the indication signal stable _ flg in the FPGA is changed from 0 to 1; at the moment, the state machine enters an initial state from an idle state, otherwise, the state machine is considered to have burrs and is ignored, the indication signal stable _ flg is kept to be 0, and the state machine stays in the idle state.
2. The FPGA-based RS485 interface signal glitch removal method of claim 1,
when stable _ flg =1 or the state machine is in the initial state, the glitch occurring in the initial bit is not processed any more.
3. An RS485 interface signal receiving method based on FPGA is characterized by comprising the following steps:
setting a reference clock clk, wherein the frequency of the reference clock clk is 50 MHz-200 MHz;
setting a sampling signal baud _ x16_ en, wherein the frequency of the sampling signal baud _ x16_ en is 16 times of the baud rate of the RS485 signal, and the high level of one reference clock clk period is kept and only kept in each period of the sampling signal baud _ x16_ en;
when baud _ x16_ en is high, one sample position for each bit of the RS485 signal;
the input RS485 signal ser _ in is synchronously received twice by using a reference clock and then is recorded as an input signal rxd _ clk _ rx;
setting a sampling count signal over _ sample _ cnt, which counts down by 1 every time baud _ x16_ en =1 during one bit of the RS485 signal, and the initial value is 15;
setting an over _ sample _ cnt _ done signal whose value is 1, which indicates that the sampling number is full, in other words, if and only if over _ sample _ cnt =0, then over _ sample _ cnt _ done = 1;
using the method of claim 2 for debouncing; the state machine directly enters the data state on condition that over _ sample _ cnt =0, i.e., over _ sample _ cnt _ done =1 and baud _ x16_ en =1 are satisfied;
each data bit following the start bit is sampled once every baud _ x16_ en =1 when over _ sample _ cnt ≧ 2, and the counter bit _ value1_ cnt is incremented by 1 when the value of the sample is "1", the counter bit _ value0_ cnt is incremented by 1 when the value of the sample is "0", so that 14 consecutive samples are taken during one data bit; when over _ sample _ cnt =1 and baud _ x16_ en =1, the sizes of bit _ value1_ cnt and bit _ value0_ cnt are compared, when bit _ value0_ cnt is larger, the final value of the data bit is "0", and when bit _ value1_ cnt is larger, the final value of the data bit is "1".
4. The FPGA-based RS485 interface signal receiving method of claim 3,
all data bits of one data frame are received, and the effective data bit receiving end flag bit _ cnt _ done = 1;
when over _ sample _ cnt _ done =1 and bit _ cnt _ done =1 and baud _ x16_ en =1, the state machine enters the stop state from the data state.
5. The FPGA-based RS485 interface signal receiving method of claim 4,
in the stop state, when over _ sample _ cnt =3 and baud _ x16_ en =1, the state machine enters the idle state from the stop state, and is ready to receive the next frame data frame.
6. An FPGA is characterized in that a plurality of FPGA chips are arranged in a matrix,
the FPGA is internally solidified with arithmetic logic, and when the arithmetic logic is executed, the steps of the method according to any one of claims 3-5 are realized.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113836075A (en) * | 2021-09-22 | 2021-12-24 | 珠海华网科技有限责任公司 | FPGA platform-based method for eliminating burrs of SPI interface signals |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100635873B1 (en) * | 2005-04-22 | 2006-10-18 | 매그나칩 반도체 유한회사 | Embedded system for eliminating a glich |
| US20160087615A1 (en) * | 2014-09-24 | 2016-03-24 | Dialog Semiconductor (UK) Ltd. | Debounce Circuit with Dynamic Time Base Adjustment for a Digital System |
| CN206003410U (en) * | 2016-05-16 | 2017-03-08 | 重庆电子工程职业学院 | A kind of disappearing for button trembles the circuit module of experimental demonstration teaching |
| CN112487739A (en) * | 2020-12-15 | 2021-03-12 | 安徽皖通邮电股份有限公司 | Signal jitter elimination method and system based on EPLD |
-
2020
- 2020-09-04 CN CN202010921627.6A patent/CN112073049B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100635873B1 (en) * | 2005-04-22 | 2006-10-18 | 매그나칩 반도체 유한회사 | Embedded system for eliminating a glich |
| US20160087615A1 (en) * | 2014-09-24 | 2016-03-24 | Dialog Semiconductor (UK) Ltd. | Debounce Circuit with Dynamic Time Base Adjustment for a Digital System |
| CN206003410U (en) * | 2016-05-16 | 2017-03-08 | 重庆电子工程职业学院 | A kind of disappearing for button trembles the circuit module of experimental demonstration teaching |
| CN112487739A (en) * | 2020-12-15 | 2021-03-12 | 安徽皖通邮电股份有限公司 | Signal jitter elimination method and system based on EPLD |
Non-Patent Citations (1)
| Title |
|---|
| 王红宇，孟立凡，黄广炎，刘春美，王威舒，降帅: "集成光波导陀螺高可靠性数据传输设计", 《仪表技术与传感器》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113836075A (en) * | 2021-09-22 | 2021-12-24 | 珠海华网科技有限责任公司 | FPGA platform-based method for eliminating burrs of SPI interface signals |
| CN113836075B (en) * | 2021-09-22 | 2024-03-19 | 珠海华网科技有限责任公司 | SPI interface signal burr eliminating method based on FPGA platform |
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Address after: No. 979, Antai Third Road, Xishan District, Wuxi City, Jiangsu Province, 214000 Patentee after: Zhongke Weizhi Technology Co.,Ltd. Address before: No. 299, Dacheng Road, Xishan District, Wuxi City, Jiangsu Province Patentee before: Zhongke Weizhi intelligent manufacturing technology Jiangsu Co.,Ltd. |