CN113765834B - Chip, signal recovery device, signal adjustment method and signal recovery method - Google Patents
Chip, signal recovery device, signal adjustment method and signal recovery method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
- H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling
- H04L25/03872—Parallel scrambling or descrambling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
- H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
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Abstract
The embodiment of the application provides a chip, a signal recovery device, a signal adjustment method and a signal recovery method, a first state signal with a first bit width generated by a functional module is adjusted to a second state signal with a second bit width by a gearbox module to obtain a state signal with the second bit width which can be processed by a data scrambling module, a third state signal obtained by encoding the second state signal and carrying out direct current balance scrambling on the second state signal by the data scrambling module meets the sending requirement of a high-speed transceiver module, and the high-speed transceiver module of the chip outputs the third state signal to the outside, wherein the second bit width is greater than the first bit width, and the bandwidth of the high-speed transceiver module for outputting the third state signal is greater than the transmission bandwidth of the first state signal, so that the complete output of the state signal of the chip can be realized.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a chip, a signal recovery apparatus, a signal adjustment method, and a signal recovery method.
Background
After the chip is subjected to chip recovery and in the normal use process, the debugging process exists, so that the chip needs to be designed to be capable of outputting specified information to detect the working state of the chip during chip design. In the existing method, a state signal to be acquired is output to a Pin (Pin) of a chip, and the Pin of the chip outputs the state signal, but the output speed of the Pin in the prior art is about 100MHZ at the fastest speed, and the main frequency of a complex chip is generally above 1GHZ, for example, 1 Pin of 100MHZ is used to output the state signal of 1GHZ main frequency chip, so that the Pin can only output and observe 1 state signal every time the chip generates 10 state signals, that is, only the state signal with the sampling rate of 1/10 can be output, and the state signal at the complete GHZ level cannot be output, thereby failing to detect the running state of the chip comprehensively.
Disclosure of Invention
An object of the embodiments of the present application is to provide a chip, a signal recovery apparatus, a signal adjustment method, and a signal recovery method, so as to achieve complete output of a chip status signal. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a chip, including:
the device comprises a functional module, a gearbox module, a data coding and scrambling module and a high-speed transceiving module; the functional module is connected with the gearbox module, the gearbox module is connected with the data scrambling module, and the data scrambling module is connected with the high-speed receiving and transmitting module;
the functional module is used for generating a first state signal with a first bit width;
the transmission module is configured to adjust a first status signal of the first bit width to a second status signal of a second bit width, where the second bit width is greater than the first bit width;
the data scrambling module is used for encoding and carrying out direct current balance scrambling on the second state signal to obtain a third state signal;
the high-speed transceiver module is configured to output the third status signal to the outside, where a bandwidth of the high-speed transceiver module, which is used to output the third status signal, is greater than a transmission bandwidth of the first status signal.
In a second aspect, an embodiment of the present application provides a signal recovery apparatus, including:
the high-speed receiving and transmitting module, the data scrambling and decoding module and the gearbox module are arranged in the transmission box; the high-speed transceiver module is connected with the data scrambling and decoding module, and the data scrambling and decoding module is connected with the gearbox module;
the high-speed transceiver module is used for receiving a third state signal sent by the chip;
the data interference decoding module is used for carrying out direct current balance descrambling and decoding on the third state signal to obtain a second state signal;
and the gearbox module is used for recovering the first state signal from the second state signal.
In a third aspect, an embodiment of the present application provides a chip state detection system, including: a status signal detection device, a chip as described in any of the present applications, and a signal recovery apparatus as described in any of the present applications;
the state signal detection device is used for detecting the first state signal output by the signal recovery device.
In a fourth aspect, an embodiment of the present application provides a signal adjusting method, which is applied to a chip, where the chip includes a high-speed transceiver, and the method includes:
generating a first state signal with a first bit width to be detected;
adjusting the first state signal with the first bit width into a second state signal with a second bit width, wherein the second bit width is larger than the first bit width;
encoding and direct current balance scrambling are carried out on the second state signal to obtain a third state signal;
and outputting the third state signal to the outside by using a high-speed transceiver, wherein the bandwidth of the high-speed transceiver for outputting the third state signal is greater than the transmission bandwidth of the first state signal.
In a fifth aspect, an embodiment of the present application provides a signal recovery method, which is applied to a signal recovery apparatus, where the signal recovery apparatus includes a high-speed transceiver; the method comprises the following steps:
receiving a third state signal sent by the chip by using the high-speed transceiver;
performing direct current balance descrambling and decoding on the third state signal to obtain a second state signal;
and recovering the first state signal from the second state signal.
The embodiment of the application has the following beneficial effects:
according to the chip, the signal recovery device, the signal adjustment method and the signal recovery method provided by the embodiment of the application, the first state signal with the first bit width generated by the functional module is adjusted to the second state signal with the second bit width by using the gearbox module, the state signal with the second bit width which can be processed by the data scrambling module is obtained, the third state signal obtained by encoding the second state signal by using the data scrambling module and performing direct current balance scrambling meets the sending requirement of the high-speed transceiver module, and the third state signal is externally output by the high-speed transceiver module of the chip, wherein the second bit width is larger than the first bit width, and the bandwidth of the high-speed transceiver module for outputting the third state signal is larger than the transmission bandwidth of the first state signal, so that the complete output of the state signal of the chip can be realized. Of course, not all advantages described above need to be achieved at the same time in the practice of any one product or method of the present application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a first schematic diagram of a chip according to an embodiment of the present disclosure;
FIG. 2 is a second schematic diagram of a chip according to an embodiment of the present application;
FIG. 3 is a third schematic diagram of a chip according to an embodiment of the present application;
FIG. 4 is a fourth schematic diagram of a chip according to an embodiment of the present application;
FIG. 5 is a diagram illustrating a chip output status signal according to an embodiment of the present disclosure;
fig. 6 is a first schematic diagram of a signal recovery apparatus according to an embodiment of the present application;
fig. 7 is a second schematic diagram of a signal recovery apparatus according to an embodiment of the present application;
fig. 8 is a third schematic diagram of a signal recovery apparatus according to an embodiment of the present application;
FIG. 9 is a diagram illustrating a signal conditioning method according to an embodiment of the present application;
fig. 10 is a schematic diagram of a signal recovery method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the description herein are intended to be within the scope of the present disclosure.
In order to achieve complete output of the chip status signal, an embodiment of the present application provides a chip, referring to fig. 1, including:
the device comprises a functional module 11, a gearbox module 12, a data scrambling module 13 and a high-speed transceiving module 14; the functional module 11 is connected with the gearbox module 12, the gearbox module 12 is connected with the data scrambling module 13, and the data scrambling module 13 is connected with the high-speed transceiver module 14;
the functional module 11 is configured to generate a first state signal with a first bit width;
the transmission module 12 is configured to adjust the first state signal with the first bit width to a second state signal with a second bit width, where the second bit width is greater than the first bit width;
the data scrambling module 13 is configured to perform encoding and dc balance scrambling on the second state signal to obtain a third state signal;
the high-speed transceiver module 14 is configured to output the third status signal externally, where a bandwidth of the high-speed transceiver module for outputting the third status signal is greater than a transmission bandwidth of the first status signal.
The functional module is used for realizing various functions of the chip, and is a module which needs to be detected in the chip, and the functional module can continuously generate a state signal with a first bit width, namely a first state signal in the operation process. For example, the main frequency of the functional module is a hertz, the first bit width is B bits, and the functional module generates B bits of data per clock (every 1/a second).
The GearBox module is configured to adjust the first state signal with the first bit width to the second state signal with the second bit width, that is, the bit width of each second state signal is the second bit width. The second bit width is determined according to the bit width processed by the data scrambling module each time, and the data scrambling module can only process data with a specified bit width (second bit width) each time, so that the gearbox module is required to adjust the continuous first state signals into a plurality of second state signals with the second bit width.
And the data coding and scrambling module is used for coding and carrying out direct current balance scrambling on the second state signal with the second bit width each time to obtain a third state signal. The high-speed transceiver module outputs a third state signal to the outside. Thereby realizing the output of the state signal of the chip. The high-speed transceiver module includes a high-speed transceiver, and it is understood that the signal output speed of the high-speed transceiver can reach the GHZ level, which is much higher than the output speed of Pin, for example, taking the high-speed transceiver using SerDes (a high-speed serial transceiver), a single SerDes can transmit several G, tens of G, or even hundreds of G data per second. Therefore, the signal output speed of the high-speed transceiver module can reach GHZ level, and the complete output of the state signal of the chip with the main frequency of GHZ level can be realized.
In this embodiment of the application, a first state signal with a first bit width generated by a functional module is adjusted to a second state signal with a second bit width by using a gearbox module, so as to obtain a state signal with the second bit width that can be processed by a data scrambling module, a third state signal obtained by encoding and dc-balance scrambling the second state signal by using the data scrambling module meets the sending requirement of a high-speed transceiver module, and the high-speed transceiver module of a chip outputs the third state signal externally, wherein the second bit width is greater than the first bit width, and the bandwidth of the high-speed transceiver module for outputting the third state signal is greater than the transmission bandwidth of the first state signal, so as to realize complete output of the chip state signal.
For a scenario in which there are multiple functional modules in a chip, in one possible implementation, referring to fig. 2, the chip includes multiple functional modules, and the chip further includes: a MUX (Multiplexer) module 15;
the plurality of functional modules are respectively connected with the multiplexer module, and the multiplexer module is connected with the gearbox module;
and the multiplexer module is used for transmitting the state signal of the appointed function module to the gearbox module.
The MUX module is arranged between the functional module and the gearbox module, and the MUX module can select the first state signal of at least one appointed functional module from the plurality of functional modules and send the first state signal to the gearbox module.
In one possible embodiment, the gearbox module is used in particular for: after receiving an enabling signal of the data scrambling module, judging whether the data length of a first state signal in a first data queue of the data scrambling module is not smaller than the second bit width, if so, adding a preset idle signal in the first state signal of the first data queue to obtain a second state signal with the second bit width; and if not, reading a state signal with the length of a second bit width in the first data queue to obtain a second state signal with the second bit width.
The transmission module includes a first data queue, and the first data queue in the transmission module keeps receiving the first status signal. And when the gearbox module receives the enabling signal, the gearbox module judges whether the data length of the first state signal in the first data queue reaches a second bit width, and if the data length of the first state signal in the first data queue reaches the second bit width, the gearbox module reads the state signal with the second bit width from the first data queue according to a first-in first-out principle to serve as the second state signal with the second bit width. If the second bit width is not reached, a preset idle signal is supplemented into the first data queue, so that the total data length of the state signal and the preset idle signal in the first data queue is the second bit width, and a second state signal with a second bit width is obtained. The transmission module outputs the current second state signal to the next module. The data length of the first status signal in the first data queue is smaller than the second bit width, including the situation that the first status signal is not included in the first data queue at all, and the second status signal at this time is composed of the preset idle signal completely.
In one example, the enable signal may be a tx _ enable signal sent by the data scrambling module, for example, the tx _ enable signal may be output to the transmission module once each time the data scrambling module completes processing of the second status signal of the second bit width. In one example, the First data queue may be a FIFO (First Input First Output) queue. In one example, the preset IDLE signal may be IDLE, where IDLE is a signal with Data being 7bits and CTRL (Control) being 1bit, i.e. IDLE in the standard ethernet protocol.
In order to further increase the output rate of the chip status signal and meet the output requirement of multiple lanes (lines), in a possible embodiment, referring to fig. 3, the high-speed transceiver module includes at least two high-speed transceivers 141, the chip includes at least two data scrambling modules 13, and the high-speed transceivers 141 are in one-to-one correspondence with the data scrambling modules 13;
the data scrambling module 13 is configured to encode and perform direct current balance scrambling on the second state signal received by the data scrambling module to obtain a third state signal, and send the obtained third state signal to a high-speed transceiver corresponding to the data scrambling module;
the high-speed transceiver 141 is configured to output a third status signal received by itself to the outside.
In one example, the transmission module may sequentially send each second bit wide second status signal to each data scrambling module in a polling manner, and the data scrambling module performs encoding and direct-current balanced scrambling on the received second status signal to obtain a third status signal, and sends the obtained third status signal to a corresponding high-speed transceiver.
In order to ensure the synchronization of the signals at the receiving end when there are multiple high-speed transceivers in the chip, in one possible embodiment, referring to fig. 4, the chip further includes: a sync head insertion module 16;
the gear box module is connected with the data coding and scrambling module through the synchronous head inserting module 16;
the gearbox module is further configured to insert a control signal with a fourth bit width after each second state signal with the second bit width, and send the second state signal with the control signal inserted therein to the second data queue of the synchronization header insertion module.
The sync header inserting module 16 is configured to insert a second set number of sync headers into a second data queue when receiving every first set number of second status signals in the second data queue; after selecting data with a third bit width from the second data queue, sending the data with the third bit width to each data scrambling module in a polling manner, wherein the bit width of each synchronization head is the third bit width, and the sum of the second bit width and the fourth bit width is the third bit width; the second set number is the number of high-speed transceivers in the high-speed transceiver module, and the first set number is an integral multiple of the second set number.
The control signal after the second status signal is used to distinguish the status signal from the preset idle signal in the second status signal, in one example, the bit width of the second status signal is an integer multiple of the bit width of the preset idle signal. And presetting the bit width of the idle signal as a fifth bit width, wherein the second bit width is an integral multiple of the fifth bit width, and the fourth bit width = the second bit width/the fifth bit width. For example, if the bit width (second bit width) of the second status signal is 64bits, the bit width (fifth bit width) of the preset idle signal is 8bits, and the bit width (fourth bit width) of the control signal is 64/8=8 bits. Every 1bit of data in the control signal is used for indicating the type of the data with the fifth bit width in the second state signal; for example, the status signal may be represented by 0 and the preset idle signal may be represented by 1. The control signal 00000001 of 8bits indicates that the first 7 × 8bits of data in the second status signal are status signals, and the last 8bits of data are preset idle signals.
The gearbox module sends a second state signal of the insertion control signal to a second data queue in the synchronization head insertion module. For example, the gearbox module sends a 64bits second status signal +8bits control signal to the second data queue in the sync head insertion module.
The number of high-speed transceivers in the high-speed transceiver module is denoted as N, that is, the first set number is N, and the first set number is Y × N. The sync head inserting module comprises a second data queue, and N sync heads are inserted into the second data queue when the second data queue receives Y × N second state signals; and selecting data with a third bit width in the second data queue each time, and sequentially sending the data to each data scrambling module in a polling mode.
The purpose of the periodic insertion of the sync header is to provide Deskew (skew compensation) alignment between multiple lanes. The number of the high-speed transceivers in the high-speed transceiver module is recorded as N, and the sync header insertion module continuously receives the second state signals with the second bit widths from the transmission module, and then adds the second state signals into a second data queue of the sync header insertion module, where the second data queue is an FIFO queue in one example. And counting the bit width of the second state signals added into the second data queue in the second data queue through a periodic counter, and inserting N synchronous heads into the second data queue by the synchronous head inserting module every time Y × N second state signals are added, wherein the bit width of each synchronous head is a third bit width. And the synchronous head inserting module selects data with a third bit width from the second data queue each time according to a first-in first-out principle, and sequentially sends the selected data to each data scrambling module in a polling mode. Thus, each high-speed transceiver can obtain the synchronization head, and the second state signals behind the corresponding synchronization heads of different high-speed transceivers are adjacent in time sequence. In one example, the sync header includes a sync header body and a control signal, the bit width of the sync header body is a second bit width, and the bit width of the control signal in the sync header is a fourth bit width.
In an example, the synchronization head body of the synchronization head may adopt the synchronization head in the Interlaken protocol, and the synchronization head body is set to be a fixed value 0x78f678f678f678f6 (if the second bit width is not reached, the second bit width needs to be filled up).
Taking the high-speed transceiver module including two high-speed transceivers as an example, for example, as shown in fig. 5, the data in the second data queue are sync header 1, sync header 2, second status signal 1, second status signal 2, second status signal 3, and second status signals 4 and … …, respectively; the data encoding and scrambling module 1 respectively encodes and carries out direct current balance scrambling on the synchronization head 1, the second state signal 1 and the second state signal 3 … … to obtain a third state signal 1, a third state signal 3 and a third state signal 5 … …; the data encoding and scrambling module 2 respectively encodes and performs direct current balance scrambling on the synchronization header 2, the second state signal 2 and the second state signal 4 … … to obtain a third state signal 2, a third state signal 4 and a third state signal 6 … …; the data transmitted by the high-speed transceiver 1 is the third status signal 1, the third status signal 3 and the third status signal 5 … … in sequence, and the data transmitted by the high-speed transceiver 2 is the third status signal 2, the third status signal 4 and the third status signal 6 … … in sequence.
In the embodiment of the application, for the case that there are multiple high-speed transceivers in the chip, the synchronization head is inserted into the second state signal through the synchronization head insertion module, so that the receiving end can align the second state signals of different high-speed transceivers based on the synchronization head, thereby implementing Deskew alignment among multiple lanes.
In a possible implementation, the data scrambling module 13 includes:
a 64B66B encoder for encoding the second state signal based on a 64B66B encoding protocol to obtain an encoded signal;
the scrambler is used for carrying out direct current balance scrambling on the coded signal to obtain a third state signal;
and the IP module is used for sending the third state signal to the corresponding high-speed transceiver.
For any data encoding and scrambling module, the second state signal received by the data encoding and scrambling module is firstly input into a 64B66B encoder; the 64B66B encoder sends the encoded signal obtained by encoding to the scrambler, the scrambler performs direct current balance scrambling on the received encoded signal to obtain a third state signal, and sends the third state signal to the IP module, and the IP module sends the received third state signal to the high-speed transceiver corresponding to the data encoding and scrambling module.
The 64B66B encoder is essentially a mapping table that functions to find the boundaries of each second bit-wide second state signal on the data stream received at the high speed transceiver in the opposite direction according to the mapping table rules. The encoder uses a 64B66B encoder, and the second bit width is 64 bits; in one example, taking the fourth bit width as 8bits as an example, the second state signal of the insertion control signal received by the 64B66B encoder each time is: in the form of a 64-bit second state signal plus an 8-bit control signal, a 64B66B encoder encodes the 64-bit second state signal based on the 8-bit control signal to obtain a 66-bit encoding signal; in one example, the 64B66B encoder may also add other control characters to the encoded signal. The role of the scrambler is to ensure dc balance of the data transmitted over the high speed transceiver line, the purpose of scrambling being to equalize the number of 0's and 1's in the signal. The IP module is used for really transmitting the parallel data of the second state signal to the high-speed transceiver line. In one example the high speed transceiver may be a SerDes.
The 64B66B encoder is an encoder specified by standard Ethernet, in the embodiment of the application, the 64B66B encoder is used for realizing the encoding of the state signal, the existing 64B66B encoder in a chip can be directly multiplexed, and the encoder is not required to be additionally added, so that the cost of the chip can be reduced.
For more clearly explaining the working process of the chip in the embodiment of the present application, the main frequency of the functional module of the chip is 1.2Ghz, and the first bit width of the generated first state signal is 40 bits. It is understood that the numerical values herein are only examples and are not intended to limit the scope of the present application, and those skilled in the art can adjust the corresponding numerical values in the chip under the inventive concept of the present application, which still falls within the scope of the present application.
The main frequency of the chip is 1.2GHZ, the bandwidth of a first state signal transmitted by a functional module communicated with the MUX module is 40bits × 1.2GHZ = 48Gbits/s, in order to realize the transmission of a signal with a bandwidth of 48Gbits/s, the high-speed transceiver module may adopt two Serdes of 25.78125GHZ, and considering the bandwidth loss after 64B66B coding, the total bandwidth of the two Serdes is: 25.78125Gbits/s 64/66 × 2 = 50 Gbits/s. Obviously, 50Gbits/s is larger than 48Gbits/s, so that the transmission bandwidth of the status signal can be satisfied.
The first data queue of the gearbox module receives a status signal of 40bits continuously from the MUX module, i.e. every 1/(1.2 × 10)9) A 40bits status signal is received second. Every time the gearbox module receives the tx _ enable signal of the 64B66B encoder, a signal with 64bits of bit width is selected from the first data queue as a second state signal, and if the bit width of the first state signal in the first data queue is less than 64bits, IDLE can be inserted to make up for 64bits of data, so as to obtain a 64bits of bit wide second status signal, and when the first data queue has no first status signal, the gearbox module can continuously spit out a 64bits second status signal composed of a plurality of IDLE bytes, so as to make up for the bandwidth difference between the inside of the chip and the Serdes line. In one example, the transmission module may output a 64-bit second status signal + 8-bit CTRL signal at a time, where the 8-bit CTRL signal is control signaling and is not within the second bit width of the second status signal.
The synchronization header insertion module is for achieving Deskew alignment among multiple lanes, so when there are only 1 Serdes, the module may not be enabled. The synchronous head is inserted into the module to continuously receive data of 64bits +8bits from the gearbox module, and the received data is placed into a second data queue. A periodic counter may be set at the entry of the second data queue, for example, N × 2048, where N is the number of Serdes, which is 2 in this embodiment. And 2 synchronous heads with fixed content are inserted into the second data queue every time 2 x 2048 second state signals with 64bits of bit width are written in the counting process. Thus, each Serdes can obtain a sync header, and the second status signals after the corresponding sync header of different Serdes are adjacent in time sequence. The Interlaken protocol may be employed to set the sync header to a fixed value of 0x78f678f678f678f 6. After receiving the tx _ enable signal output by the 64B66B encoder, the sync header insertion module reads 1 64-bit Data (here, Data is the second status signal or sync header) and 8-bit CTRL signal from the second Data queue and sends the Data to the Data scrambling module.
The chip comprises two data scrambling modules, and the state signals sent by the synchronous head inserting module are respectively sent to each data scrambling module for processing in a polling mode. The data encoding and scrambling module comprises a 64B66B encoder, a scrambler and an IP module. The data coding and scrambling module can be directly realized according to related Ethernet standards, and the data coding and scrambling module can be realized by utilizing the original Ethernet interface in the chip, so that the chip cost is reduced, and the chip area is reduced. The 64B66B encoder is essentially a mapping table, and its role is that the peer receiving direction can find the 64bits boundary from the data stream received from Serdes according to the mapping table, and can add other control characters, such as IDLE control characters, above the normal 64bits data. The role of the scrambler is to ensure DC (direct current) balance of the data transmitted on the Serdes line, even if the number of 0 s and 1 s is equal. In order to meet the transmission rate of 1.2Ghz, a 64-bit third state signal can be split into two 32-bit signals to be transmitted, and the IP module is used for really transmitting 32-bit parallel data to a Serdes line.
In the embodiment of the application, the output of the complete state signal under the GHZ-level main frequency chip can be realized, and the support is provided for the chip debugging process. Meanwhile, the existing Serdes of the chip can be multiplexed, so that an additional circuit is avoided; compared with the prior art that only the jump state of the state signal in a discrete clock period can be observed, the jump state of the state signal in each clock period can be continuously observed in the embodiment of the application.
In order to restore the third state signal output by the chip, an embodiment of the present application further provides a signal recovery apparatus, referring to fig. 6, including:
a high-speed transceiver module 21, a data scrambling and decoding module 22 and a gearbox module 23; the high-speed transceiver module 21 is connected with the data scrambling and decoding module 22, and the data scrambling and decoding module 22 is connected with the gearbox module 23;
the high-speed transceiver module 21 is configured to receive a third status signal sent by the chip;
the data descrambling module 22 is configured to perform dc balanced descrambling and decoding on the third state signal to obtain a second state signal;
the transmission module 23 is configured to recover the first status signal from the second status signal.
The state signal sent by the chip needs to be analyzed by utilizing the signal recovery device outside the chip in a reverse direction, and the signal recovery device can be realized by the chip and can also be realized by a programmable logic device, which are all within the protection scope of the application.
The number of high-speed transceivers in the high-speed transceiver module of the signal recovery apparatus should be not less than the number of high-speed transceivers in the high-speed transceiver module of the chip, and in one example, the number of high-speed transceivers in the high-speed transceiver module of the signal recovery apparatus is the same as the number of high-speed transceivers in the high-speed transceiver module of the chip in order to reduce the loss of hardware resources. The data scrambling and decoding module corresponds to the data scrambling and decoding module in the chip and is used for carrying out direct current balanced descrambling on the third state signal and decoding the descrambled state signal so as to obtain a second state signal. The direct current balance descrambling mode of the data scrambling and decoding module needs to be corresponding to the direct current balance scrambling mode of the data scrambling and coding module in the chip, and the decoding mode of the data scrambling and decoding module needs to be corresponding to the coding mode of the data scrambling and coding module in the chip.
It can be understood that the signal recovery device is configured to welcome the third status signal output by the chip as the first status signal, and therefore the first status signal, the second status signal, and the third status signal in the signal recovery device respectively correspond to the first status signal, the second status signal, and the third status signal in the chip.
In one possible embodiment, referring to fig. 7, the high-speed transceiver module comprises at least two high-speed transceivers 211; the signal recovery device comprises at least two data scrambling and decoding modules 22, and the high-speed transceivers are in one-to-one correspondence with the data scrambling and decoding modules;
the high-speed transceiver 211 is configured to send the third status signal to a data scrambling/decoding module 22 corresponding to the high-speed transceiver;
and the data scrambling and decoding module 22 is configured to perform dc balanced descrambling and decoding on the received third state signal to obtain a second state signal.
Corresponding to the data scrambling module in the chip, in a possible implementation, the data scrambling and decoding module includes:
the IP module is used for receiving a third state signal sent by the corresponding high-speed transceiver;
the scrambler is used for carrying out direct-current balanced descrambling on the third state signal to obtain a coded signal;
a 64B66B decoder for encoding the encoded signal based on a 64B66B decoding protocol to obtain a second state signal.
For any data scrambling and decoding module, an IP module in the data scrambling and decoding module receives a third state signal from a high-speed transceiver corresponding to the data scrambling and decoding module, and then sends the third state signal to a scrambler; the scrambler carries out direct current balance descrambling on the third state signal received by the scrambler to obtain an encoded signal, the encoded signal is sent to a 64B66B decoder, and the 64B66B decoder encodes the encoded signal received by the scrambler to obtain a second state signal.
And corresponding to the realization of the chip side, the IP module is used for acquiring a third state signal from the high-speed transceiver, the realization flow of the scrambler is the reverse process of the realization flow of the encoder, and the realization flow of the 64B66B decoder is the reverse process of the realization flow of the 64B66B encoder.
The implementation process of the transmission module in the signal recovery device is the inverse process of the implementation process of the transmission module in the chip, and in one possible implementation, the transmission module in the signal recovery device is specifically configured to: and removing the preset idle signal in the received second state signal to obtain a first state signal. For example, the gearbox module is used to remove the IDLE byte from the second status signal, thereby obtaining the first status signal.
In one possible embodiment, referring to fig. 7, the apparatus further comprises: a skew compensation module 24; the data scrambling and decoding module is connected with the gearbox module through the skew compensation module 24;
the skew compensation module 24 is configured to receive second state signals respectively sent by each data scrambling/decoding module, and align each path of the second state signals according to a synchronization head in each path of the second state signals; sending the aligned second status signal to the transmission module.
The skew compensation module corresponds to a synchronization head insertion module in a chip, and for the case of multiple high-speed transceivers, the skew compensation module is required to ensure that status signals output by the multiple high-speed transceivers are aligned in time. In one example, a separate FIFO is provided after each of the 64B66B decoders, and the data capacity of each FIFO can be designed to be M times the second bit width, where M is an integer, and M can be set to 10, 16, 24, or 30, for example, according to the maximum timing skew during multiple Lane (multiple high speed transceiver lines) transmission. The skew compensation module looks up the synchronization head to determine the read pointer offset between the plurality of FIFOs, thereby achieving synchronization of the status signals between the plurality of paths. In one example, the skew compensation module may delete the sync header, retain the second state signal and the IDLE control word, and combine the multiple paths of data into one path of data, and enter a subsequent module.
In a possible embodiment, with reference to fig. 8, the device further comprises:
an LVDS (Low-Voltage Differential Signaling) pin output module 25, configured to output the first state signal by using a plurality of LVDS pins.
After the first state signal is recovered in the clock domain, the first state signal can be output to the outside of the device through the LVDS pin, so that the first state signal is sampled and analyzed by using an external oscilloscope or a logic analyzer.
In a possible embodiment, with reference to fig. 8, the device further comprises: a data queue 26, a trigger condition detection module 27, and an ethernet interface 28;
the data queue 26 is used for storing the first state signal;
the trigger condition detecting module 27 is configured to detect whether a first status signal to be output currently in the data queue meets a preset trigger condition, output the first status signal to be output currently through the ethernet interface if the first status signal to be output currently in the data queue meets the preset trigger condition, and discard the first status signal to be output currently if the first status signal to be output currently is not met.
In a possible implementation manner, the triggering condition detecting module 27 is further configured to generate a corresponding triggering condition according to the setting information of the user;
the first status signal may be parsed and sent to the data queue 26 continuously, and in one example, the data queue 26 may be a FIFO. The outlet of the data queue 26 is connected to a trigger condition detection module, which can generate a corresponding trigger condition according to the setting information of the client. The trigger condition is used to determine which portion of the data in the first status signal is retained, and data that is not hit by the trigger condition is discarded at the exit of the data queue 26, thereby ensuring that the data queue 26 does not overflow. When the trigger condition is hit, the trigger condition detection module controls the entrance of the data queue 26 to stop inserting new data, the exit of the data queue 26 stops discarding data, and the data queue is connected to the ethernet interface, and the ethernet interface can package the data in the data queue 26 according to the UDP message format and transmit the data to the external computer. In one example, the data transmission needs to agree on a corresponding protocol to determine the bit width boundary that the computer can recognize the status signal. In one example, the first status signal is 40bits, i.e., 5 bytes, and the computer parses the received data in units of 1 byte of 5 bytes.
A software can be run on the computer to analyze the UDP packet, and find the bit width boundary of the first status signal according to an agreed protocol, for example, the bandwidth of the first status signal generated by the functional module is 40bits × 1.2Ghz = 48Gbits/s, then the first status signal is 40bits per clock, the software in the computer processes the UDP data by using 5 bytes as a unit, and the specific meaning of 40bits is analyzed according to the actual digit meaning of the first status signal of the chip, for example, 0 to 31 in 40bits is data, and 32 to 39 is a control signal. The data obtained by analysis can be displayed on a screen in the form of graphics or characters, so that the state signal of a certain functional module in the chip is completely presented on a computer.
An embodiment of the present application further provides a chip state detection system, including: the chip described in any of the above embodiments, the signal recovery apparatus described in any of the above embodiments, and the status signal detection device; the state signal detection device is used for detecting the first state signal output by the signal recovery device.
The state signal detection equipment can be an oscilloscope, a logic analyzer, a computer or the like, and can be selected according to actual detection requirements.
The embodiment of the application also provides a signal adjusting method, which is applied to a chip, wherein the chip comprises a high-speed transceiver; referring to fig. 9, the method includes:
s901, generating a first state signal with a first bit width to be detected;
s902, adjusting the first state signal with the first bit width into a second state signal with a second bit width, wherein the second bit width is larger than the first bit width;
s903, encoding and direct current balance scrambling are carried out on the second state signal to obtain a third state signal;
s904, outputting the third status signal to the outside by using a high-speed transceiver, where a bandwidth of the high-speed transceiver for outputting the third status signal is greater than a transmission bandwidth of the first status signal.
In one possible embodiment, the first status signal is stored in a first data queue; the adjusting the first state signal with the first bit width to a second state signal with a second bit width includes:
after the enable signal is acquired, judging whether the data volume of the first state signal in the first data queue is not smaller than the second bit width, if so, adding a preset idle signal in the first state signal of the first data queue to obtain a second state signal with the second bit width; and if not, reading a state signal with a second bit width from the first data queue to obtain a second state signal with the second bit width.
In one possible embodiment, the second status signal is stored in a second data queue; the chip comprises at least two high-speed transceivers, the method further comprising:
for each second state signal with the second bit width, inserting a control signal with a fourth bit width after the second state signal;
when a second state signal after a first set number of inserted control signals is stored in the second data queue, inserting a second set number of synchronization heads into the second data queue;
after selecting data with a third bit width from the second data queue, respectively sending the data with the third bit width by using the at least two high-speed transceivers according to a polling mode, wherein the bit width of each synchronization head is the third bit width, and the sum of the second bit width and the fourth bit width is the third bit width; the second set number is the number of high-speed transceivers in the high-speed transceiver module, and the first set number is an integral multiple of the second set number.
In a possible implementation, the encoding and dc-balanced scrambling the second state signal to obtain a third state signal includes:
encoding the second state signal based on a 64B66B encoding protocol to obtain an encoded signal;
carrying out direct current balance scrambling on the coded signal to obtain a third state signal;
and sending the obtained third state signal to a corresponding high-speed transceiver.
The embodiment of the application also provides a signal recovery method, which is applied to a signal recovery device, wherein the signal recovery device comprises a high-speed transceiver; referring to fig. 10, the method includes:
s1001, receiving a third state signal sent by a chip by using a high-speed transceiver;
s1002, performing direct current balance descrambling and decoding on the third state signal to obtain a second state signal;
and S1003, recovering the first state signal from the second state signal.
In one possible embodiment, the recovering the first state signal from the second state signal includes:
and removing the preset idle signal in the second state signal to obtain a first state signal.
In one possible embodiment, the signal recovery device comprises at least two high-speed transceivers;
the performing dc-balanced descrambling and decoding on the third state signal to obtain a second state signal includes:
respectively carrying out direct current balance descrambling and decoding on the third state signals received by each high-speed transceiver to obtain a plurality of paths of second state signals;
the method further comprises the following steps: and aligning the second state signals according to the synchronous head in the second state signals.
In a possible implementation manner, the performing dc balanced descrambling and decoding on the third status signals received by each of the high-speed transceivers respectively to obtain multiple second status signals includes:
respectively acquiring third state signals sent by the high-speed transceivers;
respectively carrying out direct current balance descrambling on each path of third state signal to obtain each path of coded signal;
and respectively coding each path of coded signals based on a 64B66B decoding protocol to obtain each path of second state signals.
In one possible embodiment, the first status signal is stored in a data queue; the method further comprises the following steps:
and detecting whether the first state signal to be output currently in the data queue meets the trigger condition, if so, outputting the first state signal to be output currently by using an Ethernet interface, and if not, discarding the first state signal to be output currently.
In one possible implementation, the signal recovery apparatus further includes a plurality of LVDS pins; the method further comprises the following steps:
outputting the first state signal using a plurality of LVDS pins.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It should be noted that, in this document, the technical features in the various alternatives can be combined to form the scheme as long as the technical features are not contradictory, and the scheme is within the scope of the disclosure of the present application. Relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present specification are described in a related manner, each embodiment focuses on differences from other embodiments, and the same and similar parts in the embodiments are referred to each other.
The above description is only for the preferred embodiment of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.
Claims (13)
1. A chip, comprising:
the device comprises a functional module, a gearbox module, a data coding and scrambling module and a high-speed transceiving module; the functional module is connected with the gearbox module, the gearbox module is connected with the data scrambling module, and the data scrambling module is connected with the high-speed receiving and transmitting module;
the functional module is used for generating a first state signal with a first bit width;
the gearbox module is used for judging whether the data length of a first state signal in a first data queue of the gearbox module is not less than a second bit width or not after receiving an enabling signal of the data scrambling module, and if the data length of the first state signal in the first data queue is not less than the second bit width, a preset idle signal is added into the first state signal in the first data queue to obtain a second state signal with the second bit width; if not, reading a state signal with a length of a second bit width in the first data queue to obtain a second state signal with the second bit width, wherein the second bit width is larger than the first bit width;
the data scrambling module is used for encoding and carrying out direct current balance scrambling on the second state signal to obtain a third state signal;
the high-speed transceiver module is configured to output the third status signal to the outside, where a bandwidth of the high-speed transceiver module, which is used to output the third status signal, is greater than a transmission bandwidth of the first status signal.
2. The chip according to claim 1, wherein the high-speed transceiver module comprises at least two high-speed transceivers, the chip comprises at least two data scrambling modules, the high-speed transceivers are in one-to-one correspondence with the data scrambling modules, and a total bandwidth of each of the high-speed transceivers in the high-speed transceiver module is greater than a bandwidth of the functional module for transmitting the first status signal;
the data scrambling module is used for encoding and carrying out direct current balance scrambling on the second state signal to obtain a third state signal, and sending the obtained third state signal to a high-speed transceiver corresponding to the third state signal;
and the high-speed transceiver is used for outputting the third state signal received by the high-speed transceiver to the outside.
3. The chip of claim 2, wherein the data scrambling module comprises:
a 64B66B encoder for encoding the second state signal based on a 64B66B encoding protocol to obtain an encoded signal;
the scrambler is used for carrying out direct current balance scrambling on the coded signal to obtain a third state signal;
and the IP module is used for sending the third state signal to the corresponding high-speed transceiver.
4. The chip of claim 2, wherein the chip further comprises: a synchronization head insertion module;
the gear box module is connected with the data scrambling module through the synchronous head inserting module;
the gearbox module is further configured to insert a control signal with a fourth bit width after each second state signal with a second bit width, and write the second state signal into which the control signal is inserted into a second data queue of the synchronization header insertion module;
the synchronization head inserting module is used for inserting a second set number of synchronization heads into a second data queue when receiving a first set number of second state signals in the second data queue; after selecting data with a third bit width from the second data queue, sending the data with the third bit width to each data scrambling module in a polling manner, wherein the bit width of each synchronization head is the third bit width, and the sum of the second bit width and the fourth bit width is the third bit width; the second set number is the number of high-speed transceivers in the high-speed transceiver module, and the first set number is an integral multiple of the second set number.
5. A signal recovery apparatus, comprising:
the high-speed receiving and transmitting module, the data scrambling and decoding module and the gearbox module are arranged in the transmission box; the high-speed transceiver module is connected with the data scrambling and decoding module, and the data scrambling and decoding module is connected with the gearbox module;
the high-speed transceiver module is used for receiving a third state signal sent by the chip;
the data interference decoding module is used for carrying out direct current balance descrambling and decoding on the third state signal to obtain a second state signal;
and the gearbox module is used for removing a preset idle signal in the second state signal to obtain a first state signal.
6. The apparatus of claim 5, wherein the high-speed transceiver module comprises at least two high-speed transceivers; the signal recovery device comprises at least two data interference decoding modules, and the high-speed transceivers are in one-to-one correspondence with the data interference decoding modules;
the high-speed transceiver is used for sending the third state signal to a data interference decoding module corresponding to the high-speed transceiver;
and the data interference decoding module is used for carrying out direct current balance descrambling and decoding on the third state signal received by the data interference decoding module to obtain a second state signal.
7. The apparatus of claim 6, wherein the data scrambling decoding module comprises:
the IP module is used for receiving a third state signal sent by the corresponding high-speed transceiver;
the scrambler is used for carrying out direct-current balanced descrambling on the third state signal to obtain a coded signal;
a 64B66B decoder for encoding the encoded signal based on a 64B66B decoding protocol to obtain a second state signal.
8. The apparatus of claim 6, further comprising: a skew compensation module; the data scrambling and decoding module is connected with the gearbox module through the skew compensation module;
the skew compensation module is used for receiving second state signals respectively sent by the data scrambling and decoding modules and aligning the second state signals according to the synchronous heads in the second state signals; sending the aligned second status signal to the transmission module.
9. The apparatus of claim 5, further comprising: the device comprises a data queue, a trigger condition detection module and an Ethernet interface;
the data queue is used for storing the first state signal;
the trigger condition detection module is configured to detect whether a first status signal to be currently output in the data queue meets a preset trigger condition, output the first status signal to be currently output through the ethernet interface if the first status signal to be currently output in the data queue meets the preset trigger condition, and discard the first status signal to be currently output if the first status signal to be currently output in the data queue does not meet the preset trigger condition.
10. A signal conditioning method applied to a chip, the chip including a high-speed transceiver, the method comprising:
generating a first state signal with a first bit width to be detected; wherein the first status signal is stored in a first data queue;
after the enabling signal is acquired, judging whether the data volume of the first state signal in the first data queue is not smaller than a second bit width, if so, adding a preset idle signal in the first state signal of the first data queue to obtain a second state signal with the second bit width; if not, reading a state signal with a second bit width from the first data queue to obtain a second state signal with the second bit width, wherein the second bit width is larger than the first bit width;
encoding and direct current balance scrambling are carried out on the second state signal to obtain a third state signal;
and outputting the third state signal to the outside by using a high-speed transceiver, wherein the bandwidth of the high-speed transceiver for outputting the third state signal is greater than the transmission bandwidth of the first state signal.
11. The method of claim 10, wherein the second status signal is stored in a second data queue; the chip comprises at least two high-speed transceivers, the method further comprising:
for each second state signal with the second bit width, inserting a control signal with a fourth bit width after the second state signal;
when a second state signal after a first set number of inserted control signals is stored in the second data queue, inserting a second set number of synchronization heads into the second data queue;
after selecting data with a third bit width from the second data queue, respectively sending the data with the third bit width by using the at least two high-speed transceivers according to a polling mode, wherein the bit width of each synchronization head is the third bit width, and the sum of the second bit width and the fourth bit width is the third bit width; the second set number is the number of high-speed transceivers in the high-speed transceiver module, and the first set number is an integral multiple of the second set number.
12. A signal recovery method is applied to a signal recovery device, wherein the signal recovery device comprises a high-speed transceiver; the method comprises the following steps:
receiving a third state signal sent by the chip by using the high-speed transceiver;
performing direct current balance descrambling and decoding on the third state signal to obtain a second state signal;
and removing the preset idle signal in the second state signal to obtain a first state signal.
13. The method of claim 12, wherein the signal recovery device comprises at least two high-speed transceivers;
the performing dc-balanced descrambling and decoding on the third state signal to obtain a second state signal includes:
respectively carrying out direct current balance descrambling and decoding on the third state signals received by each high-speed transceiver to obtain a plurality of paths of second state signals;
the method further comprises the following steps: and aligning the second state signals according to the synchronous head in the second state signals.
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