CN112073037A - Digital calibration method and circuit of real-time clock - Google Patents
Digital calibration method and circuit of real-time clock Download PDFInfo
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- CN112073037A CN112073037A CN202010804485.5A CN202010804485A CN112073037A CN 112073037 A CN112073037 A CN 112073037A CN 202010804485 A CN202010804485 A CN 202010804485A CN 112073037 A CN112073037 A CN 112073037A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F5/00—Apparatus for producing preselected time intervals for use as timing standards
- G04F5/04—Apparatus for producing preselected time intervals for use as timing standards using oscillators with electromechanical resonators producing electric oscillations or timing pulses
- G04F5/06—Apparatus for producing preselected time intervals for use as timing standards using oscillators with electromechanical resonators producing electric oscillations or timing pulses using piezoelectric resonators
- G04F5/063—Constructional details
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Abstract
The invention relates to the technical field of integrated circuit design and discloses a digital calibration method and a digital calibration circuit for a real-time clock. The method comprises the following steps: the device comprises a counting unit, a calibration value configuration unit, a decoding unit, a comparison unit, a calibration pulse generation unit and a logic AND unit. First, a calibration window is generated by the counting unit (every 2)21One source clock cycle); secondly, configuring a calibration value (the number of clock pulses to be reduced within the calibration window) by a calibration value configuration unit; thirdly, the decoding unit decodes the configured calibration value to obtain a decoding value (a calibration window count value corresponding to the calibration value); then, comparing by a comparison unit, and generating a calibration pulse after matching; and finally, performing logical AND on the calibration pulse generation unit and the source clock through a logical AND unit to obtain a calibrated clock. The digital calibration method provided by the invention solves the problem that the real-time clock is not accurately influenced by the error of the external crystal oscillator, the calibration distribution is uniform, and the calibration precision reaches 0.477 ppm.
Description
Technical Field
The invention relates to the technical field of clock calibration, in particular to a high-precision and uniform real-time clock digital calibration method and circuit.
Background
Real-time clock chips are one of the most widely used consumer electronics products in daily life. The time reference device provides accurate real-time for people or provides an accurate time reference for an electronic system, and is suitable for all occasions requiring low power consumption and accurate timing.
At present, a crystal oscillator with high precision is mostly adopted by a real-time clock chip as a clock source, the crystal oscillator is influenced by factors such as temperature, humidity and aging of external environment, the clock frequency cannot be kept at a desired value, the clock timing is inaccurate and the error is large as the service time is prolonged.
Therefore, in order to solve the problem that the real-time clock is affected by crystal oscillator errors and inaccurate in timing, the invention provides a digital calibration method and a digital calibration circuit for the real-time clock.
Disclosure of Invention
The invention aims to solve the technical problem of providing a digital calibration method of a real-time clock, which can flexibly and uniformly adjust in a digital calibration mode when the crystal oscillator of a real-time clock chip is influenced by external environmental factors and has larger error so as to ensure the accurate timing of the real-time clock.
The invention comprises the following contents: the method comprises the following steps: the device comprises a counting unit, a calibration value configuration unit, a decoding unit, a comparison unit, a calibration pulse generation unit and a logic AND unit. First, a calibration window is generated by a counting unit (2)21One source clock cycle); secondly, configuring a calibration value (the number of clock pulses to be reduced within the calibration window) by a calibration value configuration unit; thirdly, the decoding unit decodes the configured calibration value to obtain a decoding value (a calibration window count value corresponding to the calibration value); then, comparing by a comparison unit, and generating a calibration pulse after matching; and finally, performing logical AND on the calibration pulse generation unit and the source clock through a logical AND unit to obtain a calibrated clock. The method can realize high-precision uniform digital calibration of the real-time clock, the calibration precision reaches 0.477ppm, the calibration range is 0-487.971 ppm, and the requirements of most applications can be met.
Drawings
FIG. 1 is a circuit diagram of a real time clock calibration circuit;
FIG. 2 is a schematic diagram of a calibration waveform of the real-time clock calibration circuit.
Detailed Description
The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
the circuit structure of the digital calibration method and the circuit of the real-time clock of the invention is shown in figure 1, and comprises the following steps: the device comprises a counting unit, a calibration value configuration unit, a decoding unit, a comparison unit, a calibration pulse generation unit and a logic AND unit.
One end of the counting unit is connected with the source clock to generate a calibration window, and the other end of the counting unit is connected with the comparison unit; the calibration value configuration unit is used for configuring a calibration value and is connected with the decoding unit; one end of the decoding unit is connected with the calibration value configuration unit and used for decoding the configuration calibration value, and the other end of the decoding unit is connected with the comparison unit; one end of the comparison unit is connected with the counting unit, the other end of the comparison unit is connected with the decoding unit, and the decoding value is compared with the counting value; one end of the calibration pulse generating unit is connected with the comparison unit, and generates a calibration pulse after the comparison result is matched, and the other end of the calibration pulse generating unit is connected with the logic connection unit; one end of the logic and unit is connected with the source clock, the other end of the logic and unit is connected with the calibration pulse generating unit, and the calibrated clock is finally obtained through the logical AND of the calibration pulse and the source clock.
Firstly, generating a calibration window by a counting unit; secondly, configuring a calibration value through a calibration value configuration unit; thirdly, the decoding unit decodes the configured calibration value to obtain a decoded value; then, comparing by a comparison unit, and generating a calibration pulse after matching; and finally, performing logical AND on the calibration pulse generation unit and the source clock through a logical AND unit to obtain a calibrated clock. The method is realized by the following five steps:
step 1, generating a calibration window through a counting unit, and periodically counting by adopting a 21-bit counter, wherein each time 221The source clock period is a calibration window.
And 2, configuring an expected calibration value through a calibration value configuration unit according to an actual calibration requirement, namely configuring the number of clock pulses needing to be reduced in a calibration window, wherein the range is 0-1023.
And 3, decoding the calibration value obtained in the step 2 through a decoding unit to realize the following steps:
in combination with the above decoding manner, the calibration value configuration unit can configure the calibration window to reduce 1023 source clock pulses at most, and ensure that the decoded values of the decoding unit are uniformly distributed in the calibration window, thereby making the calibration distribution uniform.
And 4, comparing the decoding value obtained in the step 3 with the counting value of the counting unit in the step 1 through a comparison unit, and generating a calibration pulse. When the decoded value matches the count value of the counter unit, a calibration pulse is generated by the falling edge trigger of the source clock. Referring to FIG. 2, a calibration waveform diagram of a real time clock circuit is shown, wherein org _ clk is the source clock, bit21_ cntr is the count cell counter value, and cal _ pulses represents the calibration pulse; fig. 2 illustrates the calibration process, the calibration value configuration unit is configured as 2, which is indicated at 221The counting period is reduced by 2 source clock pulses, which are uniformly distributed at 0x80000 and 0x180000, and cal _ pulses are generated by the falling edge trigger of the clock.
And 5, the calibration circuit realizes logical AND of the calibration pulse obtained in the step 4 and the source clock to obtain a calibrated clock. As shown in fig. 2, the calibration pulse cal _ pulses obtained in step 3 is logically anded with the source clock org _ clk to finally obtain the calibrated clock cal _ clk.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (6)
1. A digital calibration method of a real-time clock is characterized in that a series of uniformly distributed digital calibrations are carried out on the real-time clock in a software and hardware cooperative working mode, and the digital calibration method is realized by the following steps:
step 1, generating a calibration window through a counting unit;
step 2, configuring an expected calibration value through a calibration value configuration unit according to an actual calibration requirement;
step 3, decoding the calibration value through a decoding unit;
step 4, comparing the decoded value with the counting value of the counting unit through a comparison unit to generate a calibration pulse;
and 5, performing logical AND on the calibration pulse and the source clock through a logical AND unit to obtain a calibrated clock.
2. The digital calibration method according to claim 1, wherein step 1, generating a calibration window by a counting unit: periodically, every 2 bits, using a 21bit counter21The source clock period is a calibration window.
3. The digital calibration method according to claim 1, wherein step 2, according to the actual calibration requirement, configures the expected calibration value by the calibration value configuration unit: the calibration value is set through the calibration value configuration unit, namely the number of clock pulses needing to be reduced in the calibration window ranges from 0 to 1023.
4. The digital calibration method according to claim 1, wherein in step 3, the calibration value is decoded by a decoding unit: the decoding unit decodes the configured calibration value to obtain a decoding value, and the decoding value ensures that the calibration is uniformly distributed in the calibration window.
5. The digital calibration method according to claim 1, wherein in step 4, the comparison of the decoded value and the count value of the counting unit is implemented by a comparison unit, and a calibration pulse is generated: when the decoded value matches the count value of the counter unit, a calibration pulse is generated by the falling edge trigger of the source clock.
6. A digital calibration circuit for a real-time clock, for implementing the digital calibration method of claim 1, mainly comprising: the device comprises a counting unit, a calibration value configuration unit, a decoding unit, a comparison unit, a calibration pulse generation unit and a logic AND unit; wherein:
a counting unit: one end of the calibration window is connected with the source clock to generate a calibration window, and the other end of the calibration window is connected with the comparison unit;
a calibration value configuration unit: the calibration value is used for configuring the calibration value and is connected with the decoding unit;
a decoding unit: one end of the calibration value configuration unit is connected with the calibration value configuration unit and used for decoding the configuration calibration value, and the other end of the calibration value configuration unit is connected with the comparison unit;
a comparison unit: one end of the decoding unit is connected with the counting unit, the other end of the decoding unit is connected with the decoding unit, and the decoding value is compared with the counting value;
a calibration pulse generating unit: one end of the logic connection unit is connected with the logic output unit, and the other end of the logic connection unit is connected with the comparison unit;
a logic AND unit: one end of the calibration pulse generator is connected with the source clock, the other end of the calibration pulse generator is connected with the calibration pulse generating unit, and the calibrated clock is finally obtained through logical AND of the calibration pulse and the source clock.
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| CN202010804485.5A CN112073037A (en) | 2020-08-12 | 2020-08-12 | Digital calibration method and circuit of real-time clock |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120112804A1 (en) * | 2010-11-09 | 2012-05-10 | Li Kuofeng | Calibration method and apparatus for clock signal and electronic device |
| CN103529904A (en) * | 2012-06-29 | 2014-01-22 | 瑞萨电子株式会社 | Clock correction circuit and clock correction method |
| CN105656456A (en) * | 2014-11-30 | 2016-06-08 | 中国科学院沈阳自动化研究所 | High-speed and high-precision digital pulse generating circuit and pulse generating method |
| CN106130547A (en) * | 2016-06-20 | 2016-11-16 | 大唐微电子技术有限公司 | A kind of clock frequency calibration steps and device |
| CN106549655A (en) * | 2015-09-21 | 2017-03-29 | 深圳市博巨兴实业发展有限公司 | A kind of self-alignment method and system of IC clock frequencies |
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- 2020-08-12 CN CN202010804485.5A patent/CN112073037A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120112804A1 (en) * | 2010-11-09 | 2012-05-10 | Li Kuofeng | Calibration method and apparatus for clock signal and electronic device |
| CN103529904A (en) * | 2012-06-29 | 2014-01-22 | 瑞萨电子株式会社 | Clock correction circuit and clock correction method |
| CN105656456A (en) * | 2014-11-30 | 2016-06-08 | 中国科学院沈阳自动化研究所 | High-speed and high-precision digital pulse generating circuit and pulse generating method |
| CN106549655A (en) * | 2015-09-21 | 2017-03-29 | 深圳市博巨兴实业发展有限公司 | A kind of self-alignment method and system of IC clock frequencies |
| CN106130547A (en) * | 2016-06-20 | 2016-11-16 | 大唐微电子技术有限公司 | A kind of clock frequency calibration steps and device |
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Application publication date: 20201211 |