CN112071906A - Thyristor chip, thyristor and manufacturing method thereof - Google Patents
Thyristor chip, thyristor and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 122
- 239000002184 metal Substances 0.000 claims abstract description 122
- 238000000034 method Methods 0.000 claims abstract description 50
- 239000010409 thin film Substances 0.000 claims abstract description 20
- 239000010408 film Substances 0.000 claims description 33
- 238000005137 deposition process Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 6
- 150000001335 aliphatic alkanes Chemical class 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 238000001914 filtration Methods 0.000 claims description 3
- 238000007737 ion beam deposition Methods 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 150000002739 metals Chemical class 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 230000017525 heat dissipation Effects 0.000 description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 6
- 229910052799 carbon Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000969 carrier Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004549 pulsed laser deposition Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7428—Thyristor-type devices, e.g. having four-zone regenerative action having an amplifying gate structure, e.g. cascade (Darlington) configuration
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Abstract
The invention discloses a thyristor chip and a manufacturing method thereof, wherein the chip comprises an N-type base region and a P-type base region which are positioned on an anode P-type layer; the cathode N-type region is positioned in the upper surface of the P-type base region; a cathode metal over the cathode emission N-type region; amplifying gate metal and central gate metal on the surface of the P-type base region; a dielectric thin film layer of a given thickness between the gate cathode metals; and an anode metal under the anode P-type layer. The invention does not need to change the design and the process of a mature thyristor, does not influence each parameter of the thyristor, can improve the di/dt tolerance, is beneficial to improving the performance of the thyristor and prolongs the service life.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a thyristor chip, a thyristor and a manufacturing method thereof.
Background
The thyristor chip is a three-terminal four-layer semiconductor device, as shown in fig. 1, three terminals of a conventional thyristor are an anode metal 31, a cathode metal 32, and a gate metal 33 (including an amplifying gate metal 34), and four layers are: an anode P type layer 35 and a low-resistance N type base region 36 of the deep diffusion layer, a P type base region 37 of the deep diffusion layer and a high-concentration cathode N type region 38 are formed by diffusion, ohmic contact type metal electrodes are led out from the anode P type layer 35 and the cathode N type region 38 and are used as anode and cathode terminals respectively, and an ohmic contact type metal electrode is led out from the P type base region 37 and is used as a gate electrode.
The on-state current rise rate di/dt of the thyristor refers to the maximum on-state current rise rate which the thyristor can bear without causing damage to the thyristor from blocking to conducting. That is, at the moment when the thyristor is triggered to conduct, if the anode current increase speed (di/dt) is too high, even if the current value does not exceed the rated value of the element, the current inside the thyristor does not have time to expand to the PN junction surface and the PN junction surface burns due to too high current density, so when the thyristor is used, the current increase rate of the circuit cannot be greater than the on-state current increase rate di/dt of the thyristor, otherwise the thyristor will be damaged.
The firing process of the thyristor includes 3 stages of delay, rise and extension. In the delay stage, although the voltage on the device is high, the current is very small, so the instantaneous power is small; in the rising stage, the voltage at the two ends of the device rapidly drops, the current rapidly rises, and the instantaneous power is maximum; during the expansion phase, the voltage slowly drops, and the current is basically maintained at a stable current value, and the instantaneous power of the current is much smaller than that of the rising phase. Since the on-current in the ramp-up phase is concentrated in the initial on-region, the higher the di/dt, the more advanced the peak of the instantaneous power, and the more concentrated it is on the smaller initial on-region area.
The di/dt that the thyristor can withstand is related to the thermal capacity of the conduction region, in addition to the size of the initial conduction region area and the propagation speed. Since the specific heat of silicon is small, the heat capacity is also small, and the thermal conductivity (148W/m.k) is low, most of the gate heat generated by the current is concentrated in the conducting region at the rising end, and only a small amount of heat can be transferred out, so that the temperature of the conducting region rises rapidly. When the temperature reaches a certain critical value, the hot carriers already exceed the injected carriers, which in turn leads to thermal feedback, the higher the current, the higher the temperature, and the lower the bulk resistance of the conducting region. At this point, more current will flow through this region, and the temperature will rise further. By circulating in this way, the current is concentrated on the certain point with the highest temperature in a short time to form hot spots, so that the device can not work normally and even be burnt. According to the relevant literature, the destruction temperature range resulting from a di/dt failure of the opening is between 1100 ℃ and 1300 ℃. This temperature is only slightly lower than the melting point of silicon (1415℃.) or the temperature caused by the failure is far above the melting point of the metal-semiconductor contact, causing the device to burn out in a very short time. The phenomenon of di/dt damage is usually that a small but very distinct hole is ablated near the gate.
The prior art method for improving thyristor di/dt comprises the following steps: strong triggering to improve the expansion speed; improving the photolithographic layout design to increase the length of the initial conducting line; the crystal orientation, the section resistivity uniformity and the residual minority carrier lifetime of the single crystal material are improved; coordinating the design problems of di/dt and dv/dt, and the like, the thermal conductive paste is covered on the silicon between the gate cathode electrodes to be matched with other measures to effectively improve the di/dt capability of the thyristor. .
The technical problem that the technical personnel in the field want to solve is that the design and the process of a mature thyristor do not need to be changed, each performance parameter of the thyristor is not influenced, and the capability of improving the di/dt tolerance of the thyristor is always improved, so that a new structure and a manufacturing method for improving the di/dt tolerance of the thyristor without greatly improving the cost are needed.
Disclosure of Invention
The invention solves the technical problem of the di/dt tolerance of the thyristor without influencing various performance parameters of the thyristor, improves the di/dt tolerance of the thyristor, improves the electrical performance of the thyristor and prolongs the service life.
The invention provides a thyristor chip, which is characterized by comprising:
the N-type base region is positioned on the anode P-type layer, and the P-type base region is positioned on the N-type base region;
the cathode N-type region is positioned in a partial region of the P-type base region, and the upper surface of the cathode N-type region is flush with the upper surface of the P-type base region, wherein the cathode N-type region comprises a cathode emission N-type region and a gate electrode N-type region which is closer to the center of the chip in the direction parallel to the surface of the P-type base region;
the cathode metal is positioned on the cathode emission N-type region and exposes part of the upper surface of the cathode emission N-type region;
the amplifying gate electrode metal is positioned on the surface of the P-type base region and is simultaneously contacted with the P-type base region and the gate electrode N-type region, and the central gate electrode metal is positioned on the upper surface of the P-type base region and is not contacted with the gate electrode N-type region;
a dielectric thin film layer with a specified thickness is positioned on the P-type base region which is not covered by the cathode metal, the amplifying gate electrode metal and the central gate electrode metal;
in an embodiment of the present invention, it is,
the thicknesses of the amplifying gate metal and the cathode metal are the same, and the thickness of the dielectric thin film is far smaller than the thicknesses of the amplifying gate metal and the cathode metal.
In an embodiment of the present invention, it is,
the designated thickness of the medium thin film layer is set to be 20-500 nm.
The total thickness of the chip is set to be 1.2 mm;
the thicknesses of the amplifying gate metal and the cathode metal are set to be 30 mu m;
the carrier concentration of the N-type base region is set to be 1013cm-3；
The anode P-type layer and the P-type base region are doped with aluminum, and the concentration of current carriers is set to be 1014cm-3～ 1016cm-3；
The cathode N-type region is doped with phosphorus, and the carrier concentration is set to be 1019cm-3；
The medium film layer comprises a DLC film and an aluminum nitride film;
the anode metal, the cathode metal and the gate metal comprise aluminum.
The invention provides a thyristor, which is characterized in that,
a thyristor chip comprising any of the above.
The invention provides a method for manufacturing a thyristor chip, which is characterized by comprising the following steps:
synchronously forming an anode P-type layer and a P-type base region on the lower surface and the upper surface of the N-type substrate respectively;
forming a cathode N-type region with the upper surface flush with the upper surface of the P-type base region in the partial region of the P-type base region, wherein the cathode N-type region comprises a cathode emission N-type region and a gate electrode N-type region;
forming ohmic contact electrode metal on the cathode emission N-type region, the P-type base region, the gate electrode N-type region and below the anode P-type layer synchronously, wherein cathode metal exposing part of the upper surface of the cathode emission N-type region is formed on the cathode emission N-type region, amplified gate electrode metal simultaneously contacting with the P-type base region and the gate electrode N-type region is formed on the surface of the P-type base region, central gate electrode metal not contacting with the gate electrode N-type region is formed on the upper surface of the P-type base region, and anode metal is formed below the anode P-type layer;
and forming a first medium thin film layer with a designated thickness on the amplifying gate metal through a deposition process.
In an embodiment of the present invention, it is,
the deposition process comprises a chemical vapor deposition process, a physical vapor deposition process, an ion beam deposition process, a filtering type vacuum cathode arc process, a pulse laser deposition process and a magnetron sputtering process, wherein the chemical vapor deposition process comprises a PECVD process;
the thickness of the amplifying gate metal is the same as that of the cathode metal, the thickness of the dielectric film layer is far smaller than that of the amplifying gate metal and that of the cathode metal, and the dielectric film layer comprises a DLC film and an aluminum nitride film.
In an embodiment of the present invention, it is,
the designated thickness of the dielectric thin film layer is set to be 20-500 nm;
the PECVD process parameters for depositing the DLC film comprise the following settings:
the vacuum pressure of the deposition chamber is set to 10-6Pa；
The flow range of the alkane gas is set to be 0-500 sccm;
setting the pressure intensity range in the deposition cavity to be 0-66.5 Pa;
the radio frequency source is set to 13.56 MHz;
setting the time range of the deposition process to be 3-10 minutes;
the temperature of the chip is kept constant in the deposition process, and the temperature of the chip in the deposition process is less than or equal to 300 ℃.
The invention provides a manufacturing method of a thyristor, which comprises the manufacturing method of the thyristor chip in any one of the above contents.
One or more embodiments of the present invention may have the following advantages over the prior art:
according to the invention, the DLC (diamond-like carbon) film material is applied to the structure of the thyristor chip, and the DLC is a good heat dissipation material, so that the heat dissipation capability near the gate pole is improved, the design and process change of a mature thyristor are not needed, and the di/dt tolerance of the thyristors in various types, sizes and structures can be improved without influencing various parameters of the thyristor, thereby being beneficial to improving the performance of the thyristor and prolonging the service life.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a conventional thyristor chip structure;
FIG. 2 is a schematic diagram of gate and cathode structures in a conventional thyristor chip;
FIG. 3 is a schematic structural diagram of a thyristor chip according to an embodiment of the invention;
FIG. 4 is a schematic flow chart of a method for manufacturing a thyristor chip according to an embodiment of the invention;
fig. 5-6 are schematic structural diagrams of the thyristor chip performing step 3 according to an embodiment of the invention;
FIG. 7 is a schematic structural diagram of a thyristor chip for performing step 4 according to an embodiment of the invention;
fig. 8 is a schematic diagram of a PEVCD process according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following detailed description of the present invention with reference to the accompanying drawings is provided to fully understand and implement the technical effects of the present invention by solving the technical problems through technical means. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
First embodiment
FIG. 2 is a schematic diagram of gate and cathode structures in a conventional thyristor chip;
fig. 3 is a schematic structural diagram of a thyristor chip according to an embodiment of the invention.
As shown in fig. 3, the present embodiment provides a thyristor chip, including: anode metal 31 (not shown), cathode metal 32, center gate metal 33, amplifying gate metal 34, anode P-type layer 35, N-type base region 36, P-type base region 37, cathode N-type region 38 (including cathode emitter N-type region 381 and gate N-type region 382), DLC thin film layer 391.
A Diamond-like carbon (DLC) film is a metastable type film of amorphous carbon containing a certain amount of Diamond bonds (sp3), the main component of the film is carbon, and carbon atoms therein are bonded by covalent bonds, and the film has excellent properties such as high infrared transmittance, high hardness, low friction coefficient, high corrosion resistance, high electrical resistivity, high thermal conductivity, high chemical stability, and the like, and has many applications in the field of power semiconductor chip manufacturing.
The embodiment provides a thyristor chip, including:
an N-type base region 36 located above the anode P-type layer 35, and a P-type base region 37 located above the N-type base region 36;
a cathode N-type region 38 located in a partial region of the P-type base region 37 and having an upper surface flush with an upper surface of the P-type base region 37, wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382;
a cathode metal 32 overlying cathode emission N-type region 381 and exposing a portion of the upper surface of cathode emission N-type region 381;
an enlarged gate metal 34 on the upper surface of the P-type base region 37 and in contact with both the P-type base region 37 and the gate N-type region 382, and a central gate metal 33 on the surface of the P-type base region 37 and not in contact with the gate N-type region 382;
a DLC thin film layer 391 of a prescribed thickness on the P-type base region 37 not covered with the cathode metal 32, the amplifying gate metal 34 and the center gate metal 33;
and an anode metal 31 under the anode P-type layer 35.
Specifically, the 4 layers of materials of the thyristor chip of the present embodiment are all made of semiconductor material silicon, and the total thickness of the thyristor chip is set to be 1.2 mm. An N-type base region 36 is arranged on the anode P-type layer 35, and a P-type base region 37 is arranged on the N-type base region 36; a cathode N-type region 38 which does not completely cover the P-type base region 37 is arranged in the upper surface of the P-type base region 37, wherein the cathode N-type region 38 comprises a cathode emission N-type region 381 and a gate N-type region 382 which is closer to the center of the chip in the direction parallel to the surface of the P-type base region 37;
the anode P-type layer 35 and the P-type base region 37 comprise aluminum doping with a carrier concentration set to 1014cm-3～ 1016cm-3(ii) a The carrier concentration of the N-type base region 36 is set to 1013cm-3(ii) a The cathode N-type region 38 is doped with phosphorus and has a carrier concentration of 1019cm-3；
The cathode metal 32 which does not completely cover the cathode emission N-type region 381 is arranged on the cathode emission N-type region 381, the enlarged gate metal 34 which is simultaneously contacted with the P-type base region 37 and the gate electrode N-type region 382 is arranged on the upper surface of the P-type base region 37, the central gate metal 33 which is not contacted with the gate electrode N-type region 382 is arranged on the surface of the P-type base region 37, the thicknesses of the enlarged gate metal 34 and the cathode metal 32 are the same, the thicknesses of the enlarged gate metal and the cathode metal are set to be 30 mu m, the anode metal 31 is arranged below the anode P-type layer 35, and the anode metal, the cathode metal and the gate metal are all made of aluminum.
A dielectric thin film layer 391 with a specified thickness is further arranged on the upper surface of the P-type base region 37 which is not covered by the cathode metal 32, the amplifying gate metal 34 and the central gate metal 33, the specified thickness of the dielectric thin film layer 391 is set to be 20-500 nm, and the dielectric thin film layer comprises a DLC thin film and an aluminum nitride thin film.
In the embodiment, a DLC (diamond-like carbon) film is deposited on the amplifying gate metal 34, the DLC film is a good heat conducting material and has ultrahigh heat conductivity (more than 900W/m.k), and the set thickness is a nano pole, so that heat near a gate can be conducted out when the thyristor is switched on, the temperature of an initial conduction region is reduced, and the high di/dt resistance of the thyristor is improved; meanwhile, the DLC film is also a good insulating medium material and has very high resistivity (more than 10)7Omega ∙ cm) and the thickness of the thyristor is 20-500 nm, and other parameter characteristics and packaging structures of the thyristor cannot be influenced. The invention can improve the background technologyThe heat dissipation capability near the gate electrode is used for conducting heat in the chip to the outside of the chip as soon as possible in a heat conduction mode, so that the di/dt resistance capability of the thyristor is improved, mature thyristor design and process change are not needed, parameters of the thyristor are not affected, the performance of the thyristor is favorably improved, and the service life is prolonged.
In summary, one or more embodiments of the present invention have the following advantages:
according to the invention, the DLC (diamond-like carbon) film material is applied to the structure of the thyristor chip, and the DLC is a good heat dissipation material, so that the heat dissipation capability near the gate pole is greatly improved, the design and process change of a mature thyristor is not required, and the di/dt resistance capability of the thyristors in various types, sizes and structures can be improved without influencing various parameters of the thyristor, thereby being beneficial to improving the performance of the thyristor and prolonging the service life.
Second embodiment
The present embodiment provides a thyristor, which includes the thyristor chip having any one of the structures in the first embodiment, and has the advantages of the first embodiment.
Third embodiment
FIG. 2 is a schematic structural diagram of a thyristor chip according to an embodiment of the invention;
FIG. 4 is a schematic flow chart of a method for manufacturing a thyristor chip according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of a thyristor chip for performing step 3 according to an embodiment of the invention;
fig. 6 and 7 are schematic structural diagrams of a thyristor chip for performing step 4 according to an embodiment of the invention;
fig. 8 is a schematic diagram of a PEVCD process according to an embodiment of the invention.
As shown in fig. 2, the thyristor chip manufactured by the method for manufacturing a thyristor chip according to this embodiment includes: anode metal 31, cathode metal 32, center gate metal 33, amplifying gate metal 34, anode P-type layer 35, N-type base region 36, P-type base region 37, cathode N-type region 38 (including cathode emitter N-type region 381 and gate N-type region 382), DLC thin film layer 391.
The embodiment provides a method for manufacturing a thyristor chip, which comprises the following steps:
step 1, synchronously forming an anode P-type layer 35 and a P-type base region 37 on the lower surface and the upper surface of the N-type substrate respectively.
And step 2, forming a cathode N-type region 38 with the upper surface flush with the upper surface of the P-type base region 37 in a partial region of the P-type base region 37, wherein the cathode N-type region 38 comprises a cathode emission N-type region 381 and a gate N-type region 382 closer to the center of the chip in a direction parallel to the surface of the P-type base region 37.
Specifically, after the surface lithography process on the P-type base region 37, ions are implanted at corresponding positions to form a cathode N-type region 38 that does not completely cover the P-type base region 37, wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382 closer to the center of the chip in a direction parallel to the surface of the P-type base region 37.
And step 3, simultaneously forming ohmic contact electrode metal on the cathode emission N-type region 381, the P-type base region 37 and the gate electrode N-type region 382 and below the anode P-type layer 35, wherein the cathode metal 32 exposing part of the upper surface of the cathode emission N-type region 381 is formed on the cathode emission N-type region 381, the amplified gate electrode metal 34 simultaneously contacting with the P-type base region 37 and the gate electrode N-type region 382 is formed on the upper surface of the P-type base region 37, the central gate electrode metal 33 not contacting with the gate electrode N-type region 382 is formed on the upper surface of the P-type base region 37, and the anode metal is formed below the anode P-type layer.
Specifically, an extremely high metal layer is deposited on the upper surface of the P-type base region 37 of the thyristor silicon-based chip through an evaporation/sputtering process; then, obtaining a photoresist layer consistent with a target pattern on the metal layer through a photoetching process; the metal layer at the non-target position is removed by etching to obtain a metal layer with a target pattern, and the photoresist is removed, so as to obtain a cathode metal 32 on the cathode emission N-type region 381, which does not completely cover the cathode emission N-type region 381, an enlarged gate metal 34 on the upper surface of the P-type base region 37 and in contact with the P-type base region 37 and the gate N-type region 382, and a central gate metal 33 on the upper surface of the P-type base region 37 and in contact with the gate N-type region 382, as shown in fig. 5. The enlarged gate metal 34 and cathode metal 32 are the same thickness. An anode metal 31 is deposited under the anode P-type layer 35 at the same time of forming a metal layer on the upper surface of the P-type base region 37.
And 4, a dielectric thin film layer 391 with a specified thickness is further arranged on the upper surface of the P-type base region 37 which is not covered by the cathode metal 32, the amplifying gate metal 34 and the central gate metal 33.
Specifically, photoresist is coated on the surfaces of the enlarged gate metal 34, the central gate metal 33, the cathode metal 32 and the P-type base region 37 which is not covered by metal, as shown in fig. 6, a dielectric film 39 with a specified thickness is formed on the photoresist and the surface of the P-type base region 37 which is not covered by the cathode metal 32, the enlarged gate metal 34 and the central gate metal 33 by deposition through a PECVD process, as shown in fig. 7, and then the photoresist is removed, so as to form the thyristor chip structure shown in fig. 2. The thickness of the dielectric film layer is far less than that of the amplifying gate metal and cathode metal, and the dielectric film layer comprises a DLC film and an aluminum nitride film.
As shown in FIG. 8, the PECVD process places the thyristor chip to be deposited with DLC film on the heating plate, and the deposition chamber is evacuated to 10 deg.C-6Pa; setting the flow rate of the alkane gas to be 0-500 sccm, and spraying the alkane gas into the cavity; then, the pressure in the cavity is automatically adjusted to be 0-500 mTorr, namely 0-66.5 Pa, through a vacuum adjusting valve; the alkane gas sprayed into the cavity is decomposed into C under the excitation of a 13.56MHz radio frequency sourcenHm+(ii) a The radio frequency power supply is arranged at two ends of the parallel plate capacitor, the heating plate is used as a cathode and is grounded, the deposition chamber wall is used as an anode, and the areas of the cathode plate and the anode plate are different; under the excitation of a radio frequency source, the movement rates of ions and electrons in the plasma are different, the negative bias voltage of 200-1000V exists between the polar plates due to the different polar plate areas, and CnHm+Bombarding a substrate material at a high speed under the action of negative bias voltage, obtaining a DLC film with the thickness of about 20-500 nm in the deposition process time of 3-10 min, setting the heating plate temperature to be constant in the deposition process, setting the chip temperature to be not more than 300 ℃ in the deposition process, and causing a deposited diamond structure (sp) if the temperature is too high3) Towards the graphitic structure (sp)2) And (4) converting.
The deposition process further comprises a chemical vapor deposition process, a physical vapor deposition process, an ion beam deposition process, a filtering type vacuum cathode arc process, a pulsed laser deposition process and a magnetron sputtering process, wherein the chemical vapor deposition process comprises a PECVD process.
In summary, the present embodiment has the following advantages:
the manufacturing method of the embodiment applies the DLC (diamond-like carbon) film material to the structure of the thyristor chip, and as the DLC is a good heat dissipation material, the heat dissipation capability near the gate pole is greatly improved, the design and the process of a mature thyristor are not required to be changed, and the parameters of the thyristor are not influenced, so that the di/dt resistance capability of the thyristors in various types, sizes and structures can be improved, the performance of the thyristor can be improved, and the service life of the thyristor can be prolonged.
Fourth embodiment
This embodiment provides a method for manufacturing a thyristor, including the method for manufacturing a thyristor chip in the third embodiment, and the advantages are as described in the third embodiment.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as disclosed, and that the scope of the invention is not to be limited to the particular embodiments disclosed herein but is to be accorded the full scope of the claims.
Claims (10)
1. A thyristor chip, comprising:
the N-type base region is positioned on the anode P-type layer, and the P-type base region is positioned on the N-type base region;
the cathode N-type region is positioned in a partial region of the P-type base region, and the upper surface of the cathode N-type region is flush with the upper surface of the P-type base region, wherein the cathode N-type region comprises a cathode emission N-type region and a gate electrode N-type region which is closer to the center of the chip in the direction parallel to the surface of the P-type base region;
the cathode metal is positioned on the cathode emission N-type region and exposes part of the upper surface of the cathode emission N-type region;
the amplifying gate electrode metal is positioned on the surface of the P-type base region and is simultaneously contacted with the P-type base region and the gate electrode N-type region, and the central gate electrode metal is positioned on the upper surface of the P-type base region and is not contacted with the gate electrode N-type region;
a dielectric thin film layer with a specified thickness is positioned on the P-type base region which is not covered by the cathode metal, the amplifying gate electrode metal and the central gate electrode metal;
and an anode metal under the anode P-type layer.
2. The thyristor chip of claim 1,
the thicknesses of the amplifying gate metal and the cathode metal are the same, and the thickness of the dielectric thin film is far smaller than the thicknesses of the amplifying gate metal and the cathode metal.
3. The thyristor chip of claim 2,
the designated thickness of the dielectric thin film layer is set to be 20-500 nm;
the total thickness of the chip is set to be 1.2 mm;
the thicknesses of the amplifying gate metal and the cathode metal are set to be 30 mu m.
4. The thyristor chip of claim 3,
the carrier concentration of the N-type base region is set to be 1013cm-3；
The anode P-type layer and the P-type base region comprise aluminum element doping, and the carrier concentration is set to be 1014cm-3～1016cm-3；
The cathode N-type region is doped with phosphorus, and the carrier concentration is set to be 1019cm-3。
5. The thyristor chip of claim 2,
the medium film layer comprises a DLC film and an aluminum nitride film;
the anode metal, the cathode metal and the gate metal comprise aluminum.
6. A thyristor, characterized in that,
a thyristor chip comprising the thyristor of any one of claims 1 to 5.
7. A method for manufacturing a thyristor chip is characterized by comprising the following steps:
synchronously forming an anode P-type layer and a P-type base region on the lower surface and the upper surface of the N-type substrate respectively;
forming a cathode N-type region with the upper surface flush with the upper surface of the P-type base region in the partial region of the P-type base region, wherein the cathode N-type region comprises a cathode emission N-type region and a gate electrode N-type region;
forming ohmic contact electrode metal on the cathode emission N-type region, the P-type base region, the gate electrode N-type region and below the anode P-type layer synchronously, wherein cathode metal exposing part of the upper surface of the cathode emission N-type region is formed on the cathode emission N-type region, amplified gate electrode metal simultaneously contacting with the P-type base region and the gate electrode N-type region is formed on the surface of the P-type base region, central gate electrode metal not contacting with the gate electrode N-type region is formed on the upper surface of the P-type base region, and anode metal is formed below the anode P-type layer;
and forming a dielectric thin film layer with a specified thickness on the upper surface of the P-type base region which is not covered by the cathode metal, the amplifying gate metal and the central gate metal.
8. The method of claim 7,
the deposition process comprises a chemical vapor deposition process, a physical vapor deposition process, an ion beam deposition process, a filtering type vacuum cathode arc process, a pulse laser deposition process and a magnetron sputtering process, wherein the chemical vapor deposition process comprises a PECVD process;
the thickness of the amplifying gate metal is the same as that of the cathode metal, the thickness of the dielectric film layer is far smaller than that of the amplifying gate metal and that of the cathode metal, and the dielectric film layer comprises a DLC film and an aluminum nitride film.
9. The method of claim 8,
the designated thickness of the dielectric thin film layer is set to be 20-500 nm;
the PECVD process parameters for depositing the DLC film comprise the following settings:
the vacuum pressure of the deposition chamber is set to 10-6Pa；
The flow range of the alkane gas is set to be 0-500 sccm;
setting the pressure intensity range in the deposition cavity to be 0-66.5 Pa;
the radio frequency source is set to 13.56 MHz;
setting the time range of the deposition process to be 3-10 minutes;
the temperature of the chip is kept constant in the deposition process, and the temperature of the chip in the deposition process is less than or equal to 300 ℃.
10. A method for fabricating a thyristor, which is characterized in that,
a method of making a thyristor chip comprising any one of claims 7 to 9.
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| JP2000332231A (en) * | 1999-05-19 | 2000-11-30 | Mitsubishi Electric Corp | Semiconductor device |
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| CN212659546U (en) * | 2020-07-14 | 2021-03-05 | 株洲中车时代半导体有限公司 | Thyristor chip and thyristor |
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| JP2000332231A (en) * | 1999-05-19 | 2000-11-30 | Mitsubishi Electric Corp | Semiconductor device |
| US20070222023A1 (en) * | 2006-03-14 | 2007-09-27 | Infineon Technologies Austria Ag | Integrated circuit having a semiconductor arrangement and method for producing it |
| CN104253150A (en) * | 2013-06-26 | 2014-12-31 | 英飞凌科技股份有限公司 | Semiconductor device and method for producing same |
| CN104409491A (en) * | 2013-08-26 | 2015-03-11 | 湖北台基半导体股份有限公司 | High-voltage quick-turn-on thyristor and manufacturing method thereof |
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