CN112071345B - Non-electric volatile combined memory device and operation method thereof - Google Patents
Non-electric volatile combined memory device and operation method thereof Download PDFInfo
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- CN112071345B CN112071345B CN202010811131.3A CN202010811131A CN112071345B CN 112071345 B CN112071345 B CN 112071345B CN 202010811131 A CN202010811131 A CN 202010811131A CN 112071345 B CN112071345 B CN 112071345B
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0028—Word-line or row circuits
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- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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- G—PHYSICS
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- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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Abstract
The invention provides two non-electric volatile combined memory devices and operation methods thereof, wherein the device mainly comprises: the resistive random access memory comprises a resistive random access memory, a transistor and a storage capacitor; when the resistive random access memory and the storage capacitor are connected in series, the other end of the storage capacitor is connected with the source end of the transistor, the resistive random access memory is connected with the source line, a second word line is led out between the storage capacitor and the resistive random access memory, the grid electrode of the transistor is connected with the first word line, and the drain electrode of the transistor is connected with the bit line; when the resistive random access memory and the storage capacitor are connected in parallel, the common end of the storage capacitor connected with the resistive random access memory in parallel is connected with the source end of the transistor, the storage capacitor is grounded, the resistive random access memory is connected with the source line, the grid electrode of the transistor is connected with the word line, and the drain electrode of the transistor is connected with the bit line. In addition, the storage capacitor can be manufactured by adopting a stacked type or a groove type. Therefore, the two structures of the application have the characteristics of non-volatility, high speed and low power consumption, and also have the characteristics of flexibility in process manufacturing and easiness in realizing low-cost manufacturing.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to two non-volatile combined memory devices and methods of operating the same.
Background
In computer memory devices, the research of combining a dynamic memory with a non-electric volatile memory to obtain a combined memory device with low power consumption, high speed and non-electric volatility is becoming a hot spot.
Among them, nonvolatile memories which are used in many cases are resistance random access memories. However, in the prior art, in the method of combining the dynamic memory and the resistive random access memory, the materials used by the resistive random access memory and the storage capacitors are respectively arranged at two ends of the transistor, so that in the process manufacturing, in order to extract the word line between the source end of the transistor and the storage capacitors, the capacitors of the combined memory device must adopt stacked capacitors, and the situation that the trench capacitors are not used is avoided, thereby limiting the manufacturing mode of the nonvolatile memory device; in addition, the stacked capacitor exists between different polysilicon layers, which leads to the problems of complex process, high manufacturing cost and the like.
Disclosure of Invention
The present invention is directed to solving, at least in part, one of the technical problems in the related art.
Therefore, the invention aims to provide two nonvolatile combined memory devices and an operation method thereof, and aims to provide two nonvolatile combined memory device structures which have the characteristics of nonvolatile property, high speed and low power consumption, process manufacturing flexibility and easy realization of low-cost manufacturing.
A first nonvolatile combined memory device according to the present invention comprises: memory cells, each memory cell comprising: a resistive memory, a storage capacitor and a transistor, a first word line, a second word line, a bit line, a parasitic capacitor and a source line, wherein,
one end of the storage capacitor is connected with the source end of the transistor, and the other end of the storage capacitor is connected with one end of the resistive random access memory;
the other end of the resistive random access memory is connected with a source line, and a second word line is led out between the storage capacitor and the resistive random access memory;
the grid electrode of the transistor is connected with the first word line, and the drain electrode of the transistor is connected with the bit line;
one end of the parasitic capacitor is connected with the bit line, and the other end of the parasitic capacitor is grounded.
A second nonvolatile combined memory device according to the present invention includes: memory cells, each memory cell comprising: a resistive memory, a storage capacitor, a transistor, a word line, a bit line, a parasitic capacitor, and a source line, wherein,
the storage capacitor is connected with the resistive random access memory in parallel, the common end of the storage capacitor connected with the resistive random access memory in parallel is connected with the source end of the transistor, the other end of the storage capacitor is grounded, and the other end of the resistive random access memory is connected with the source line;
the grid electrode of the transistor is connected with the word line, and the drain electrode of the transistor is connected with the bit line;
one end of the parasitic capacitor is connected with the bit line, and the other end of the parasitic capacitor is grounded.
In addition, the nonvolatile combined memory device according to the present invention may further have the following additional technical features:
according to some embodiments of the invention, the storage capacitor is a stacked capacitor or a trench capacitor.
According to some embodiments of the present invention, the resistive random access memory may also be a phase change memory or a magnetic memory.
Based on the nonvolatile combined memory device, the invention also provides an operation method of the nonvolatile combined memory device, and the purpose is to control the nonvolatile combined memory device to complete reading and writing of data.
A first method of operating a nonvolatile combined memory device according to the present invention includes: setting first word lines of all the memory units to be low potential, setting second word lines to be establishment voltage of the resistive random access memory, grounding a source line, and writing the resistive random access memory into a low resistance state by potential difference between the second word lines and the source line; grounding the second word line, setting the first word line of the selected memory cell to be high potential, and writing in the storage capacitor; when the write data is 1, setting the bit line of the storage unit to be high potential, and charging the storage capacitor; when the write data is 0, the bit line of the storage unit is set to be a low potential, and the storage capacitor discharges; in the reading operation, the first word line and the second word line are set to be zero potential, the bit line is set to be precharge voltage, and the first word line of the selected memory cell is set to be high potential; the sense amplifier determines the direction of the current and reads out the data stored in the storage capacitor.
In addition, the operation method of the first nonvolatile combined memory device according to the present invention may further have the following additional technical features:
according to some embodiments of the present invention, when it is detected that the power supply is not powered down, the read data is rewritten into the storage capacitor using a refresh circuit in the dynamic memory circuit; when power failure is detected, writing the data read from the storage capacitor into the resistive random access memory through a cache; when the stored data is 0, setting the second word line to be zero potential, setting reset voltage on the source line, and writing the resistive random access memory to be in a high-resistance state; when the stored data is 1, the resistive random access memory is not modified; and when the power-on is detected, setting the second word line as the reading voltage of the resistive random access memory, setting the source line as zero potential, reading data stored in the resistive random access memory, rewriting the data stored in the resistive random access memory into the storage capacitor, and setting the resistive random access memory to be in a low resistance state.
According to further embodiments of the present invention, a second method of operating a non-electrical volatile combined memory device of the present invention includes: setting a bit line as the establishment voltage of the resistive random access memory to change the resistive random access memory into a low-resistance state; setting a source line to zero potential and setting a word line to high potential; when the write data is 1, setting the bit line of the storage unit to be high potential, and charging the storage capacitor; when the write data is 0, the bit line of the storage unit is set to be low potential, and the storage capacitor is discharged; in a read operation, all source lines are set to zero potential, word lines are set to zero potential, bit lines are set to precharge voltage, and word lines of a selected memory cell are set to high potential; the sense amplifier judges the current direction to read out the data stored in the storage capacitor.
According to some embodiments of the present invention, when it is detected that the power supply is not powered down, the read data is rewritten into the storage capacitor using a refresh circuit in the dynamic memory circuit; when power failure is detected, writing the data read from the storage capacitor into the resistive random access memory through a cache; when the stored data is 0, setting a high potential for a word line, setting a reset voltage on a source line, and writing the resistive random access memory into a high resistance state; when the stored data is 1, the resistive random access memory is not modified; when the power-on is detected, all word lines are set to be in a high potential, reading voltage of the resistive random access memory is set in all bit lines, the source lines are set to be in a zero potential, data stored in the resistive random access memory are read out, the data stored in the resistive random access memory are rewritten into the storage capacitor, and the resistive random access memory is set to be in a low resistance state.
The non-electric volatile combined memory device and the operation method thereof provided by the embodiment of the invention have the following beneficial effects:
according to the present invention, a nonvolatile combined memory device and an operating method thereof, wherein the device includes: memory cells, each memory cell comprising: when the resistive random access memory and the storage capacitor are connected in series, the other end of the storage capacitor is connected with the source end of the transistor, the resistive random access memory is connected with a source line, a second word line is led out between the storage capacitor and the resistive random access memory, the grid electrode of the transistor is connected with the first word line, and the drain electrode of the transistor is connected with a bit line; when the resistive random access memory and the storage capacitor are connected in parallel, the common end of the storage capacitor connected with the resistive random access memory in parallel is connected with the source end of the transistor, the storage capacitor is grounded, the resistive random access memory is connected with the source line, the grid electrode of the transistor is connected with the word line, and the drain electrode of the transistor is connected with the bit line. In addition, the storage capacitor can be manufactured by adopting a stacked type or a groove type. When the nonvolatile combined memory device based on the invention is normally powered on, the operation method of the nonvolatile combined memory device can realize the data reading with high speed and low power consumption; when the nonvolatile combined memory device based on the invention is powered down, the operation method of the nonvolatile combined memory device can realize the storage of data and reload the data after powering on again. Therefore, the two structures of the application have the characteristics of non-volatility, high speed and low power consumption, and have the characteristics of flexibility in process manufacturing and easiness in low-cost manufacturing.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1a is a schematic diagram of a series structure of memory cells according to an embodiment of the present invention;
FIG. 1b is a schematic diagram of a memory cell structure with a parallel structure according to an embodiment of the present invention;
FIG. 2a is a schematic structural diagram of a non-volatile combined memory device according to an embodiment of the present invention;
FIG. 2b is a schematic structural diagram of another non-volatile combined memory device according to an embodiment of the present invention;
fig. 3 is a schematic process diagram of a memory cell according to an embodiment of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and intended to explain the present invention and should not be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like, are used in the orientations and positional relationships indicated in the drawings, which are based on the orientations and positional relationships indicated in the drawings, and are used for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The invention aims to provide two non-electric volatile combined memory devices and operating methods thereof, and the two structures of the non-electric volatile combined memory device have the characteristics of non-electric volatility, high speed and low power consumption, and also have the characteristics of process manufacturing flexibility and easiness in realizing low-cost manufacturing.
The resistive random access memory is a type of nonvolatile memory which is developed rapidly in recent years, and the working principle of the resistive random access memory is to store data by using the phenomenon that voltage sensitive materials can present different resistance states under the conditions of high voltage and reverse high voltage. Meanwhile, due to the advantage of small volume of the material of the resistive random access memory, the storage density of the resistive random access memory is very high, and the resistive random access memory can adapt to the production of high-density storage equipment.
The dynamic memory is a kind of electric volatile memory, but the dynamic memory has fast read-write speed, low power consumption and small size, and is the mainstream mass data memory at present.
The invention provides two nonvolatile combined memory devices combining the advantages of a dynamic memory and a resistive random access memory, wherein the nonvolatile combined memory device comprises a plurality of memory cells, and each memory cell comprises: the resistance Random Access Memory comprises a Resistance Random Access Memory (RRAM), a storage capacitor Cm and a transistor, wherein when the Resistance Random Access Memory (RRAM) is connected with the storage capacitor Cm in series, the resistance Random Access Memory further comprises a first Word Line (WL), a second Word Line (WL), a Bit Line (BL), a parasitic capacitor (Cs) and a Source Line (SL); when the resistive random access memory is connected with the storage capacitor in parallel, the resistive random access memory further comprises a word line WL, a bit line BL, a parasitic capacitor Cs and a source line SL, wherein the source end of the transistor is connected with the storage capacitor and the resistive random access memory.
When the resistive random access memory is connected with the storage capacitor in series, one end of the storage capacitor is connected with the source end of the transistor, and the other end of the storage capacitor is connected with one end of the resistive random access memory; the other end of the resistive random access memory is connected with a source line, and a second word line is led out between the storage capacitor and the resistive random access memory; the grid electrode of the transistor is connected with the first word line, and the drain electrode of the transistor is connected with the bit line; one end of the parasitic capacitor is connected with the bit line, and the other end of the parasitic capacitor is grounded.
When the resistive random access memory is connected with the storage capacitor in parallel, the common end of the storage capacitor connected with the resistive random access memory in parallel is connected with the source end of the transistor, the other end of the storage capacitor is grounded, and the other end of the resistive random access memory is connected with the source line; the grid electrode of the transistor is connected with the word line, and the drain electrode of the transistor is connected with the bit line; one end of the parasitic capacitor is connected with the bit line, and the other end of the parasitic capacitor is grounded.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
The memory cell of the nonvolatile combined memory device according to the embodiment of the present invention has two structures, as shown in (a) of fig. 1, (a) is a series arrangement of a resistance change memory and a storage capacitor, and the memory cell includes: the resistance change memory 201, the storage capacitor 202, the transistor 203, the first word line 204, the second word line 205, the bit line 206, the parasitic capacitor 207 and the source line 208.
One end of the storage capacitor 202 is connected with the source end of the transistor 203, and the other end of the storage capacitor 202 is connected with one end of the resistive random access memory 201; the other end of the resistive random access memory 201 is connected with a source line 208, a second word line 204 is led out between the storage capacitor 202 and the resistive random access memory 201, the gate of the transistor 203 is connected with the first word line 205, the drain of the transistor 203 is connected with the bit line 206, a parasitic capacitor 207 is led out of the bit line 206, and the other end of the parasitic capacitor 207 is grounded.
Fig. 1 (b) shows another structure of a memory cell, in which a resistive random access memory and a storage capacitor are arranged in parallel, wherein the memory cell includes: a resistance change memory 301, a storage capacitor 302, a transistor 303, a word line 304, a bit line 305, a parasitic capacitor 306, and a source line 307.
The common end of the storage capacitor 302 and the resistive random access memory 301 is connected with the source end of the transistor 303, the other end of the storage capacitor 302 is grounded, the other end of the resistive random access memory 301 is connected with the source line 307, the gate of the transistor 303 is connected with the word line 304, the drain of the transistor 303 is connected with the bit line 305, the parasitic capacitor 306 is led out of the bit line 305, and the other end of the parasitic capacitor 306 is grounded.
The nonvolatile combined memory device of the embodiment of the invention is composed of a plurality of memory cells, each memory cell is positioned in the intersection area of a first word line and a bit line, each memory cell comprises a resistive random access memory, a transistor and a storage capacitor, as shown in fig. 2a and fig. 2b, the two memory cells are structural diagrams of the nonvolatile combined memory device based on the invention, the resistive random access memory and the storage capacitor are positioned at the same end of the transistor in both structures, as shown in fig. 3, in the production process, G represents the grid electrode of the transistor, D represents the drain electrode of the transistor, S represents the source end of the transistor, and GND represents the ground wire. Fig. 3 (a) illustrates a processing method of a resistive random access memory and a storage capacitor parallel structure using a trench capacitor; fig. 3 (b) illustrates a trench capacitor process method for a series structure of a resistive random access memory and a storage capacitor; fig. 3 (c) illustrates a process method of using a stacked capacitor for a parallel structure of a resistive random access memory and a storage capacitor; fig. 3 (d) illustrates a process method of using a stacked capacitor for a series structure of a resistive random access memory and a storage capacitor. The two structures according to the application have the characteristics of non-volatility, high speed and low power consumption, and also have the characteristics of process manufacturing flexibility and easiness in realizing low-cost manufacturing.
In addition, in some embodiments of the present invention, a phase change memory or a magnetic memory may be used instead of the resistive random access memory to implement data storage after power down and data loading at the beginning of power up of the nonvolatile combined memory device according to the present application.
As can be seen from the above, in the embodiments of the present invention, the two structures of the present application have the characteristics of non-volatility, high speed, and low power consumption, as well as the characteristics of process flexibility and easiness in low-cost manufacturing.
In order to achieve the technical effects of the nonvolatile combined memory device, the invention also provides an operation method of the nonvolatile combined memory device based on the nonvolatile combined memory device.
The method of operation of the non-electrical volatile combined memory device of the present invention is described in detail below with reference to fig. 2a, in which:
in fig. 2a, 201 to 203 are bit lines, 204 to 206 are first word lines, 207 to 209 are second word lines, 210 to 218 are memory cells of the non-volatile combined memory device of the present invention, 219 to 221 are parasitic capacitances on the bit lines, 222 is a row decoder 1, 223 is a row decoder 2, 224 is a multiplexer 1, 225 is a multiplexer 2, 226 is a column decoder, 227 is a multiplexer, 228 is a sense amplifier, 229 is a refresh circuit, 230 is a write driver, 231 is a buffer, 232 is an input/output, and 233 to 235 is a source line.
The specific operation of the present invention is further illustrated below:
prior to performing read and write operations on the non-volatile combination memory device disclosed by embodiments of the present invention,
setting the first word lines of all the memory units to be at a low potential, setting the second word lines to be the establishment voltage of the resistive random access memory, grounding the source line, and writing the resistive random access memory into a low resistance state by the potential difference between the second word lines and the source line;
grounding the second word line, setting the first word line of the selected memory unit to be high potential, and writing in the storage capacitor; when the write data is 1, setting the bit line of the storage unit to be high potential, and charging the storage capacitor; when the write data is 0, the bit line of the storage unit is set to be a low potential, and the storage capacitor discharges;
in the reading operation, the first word line and the second word line are set to be zero potential, the bit line is set to be pre-charging voltage, and the first word line of the selected memory unit is set to be high potential;
judging the current direction through a sense amplifier so as to read out data stored in a storage capacitor;
when detecting that the power supply is not powered down, rewriting the read data into the storage capacitor by using a refreshing circuit in the dynamic memory circuit;
when power failure is detected, writing the data read from the storage capacitor into the resistive random access memory through a cache;
when the stored data is 0, setting the second word line to be zero potential, setting reset voltage on the source line, and writing the resistive random access memory to be in a high-resistance state;
when the stored data is 1, the resistive random access memory is not modified;
and when the power-on is detected, setting the second word line as the reading voltage of the resistive random access memory, setting the source line as the zero potential, reading the data stored in the resistive random access memory, rewriting the data stored in the resistive random access memory into the storage capacitor, and setting the resistive random access memory in a low resistance state.
The method of operating a non-volatile combined memory device of another structure according to the present invention is described in detail below with reference to fig. 2b, in which:
in FIG. 2b, 301-303 are bit lines, 304-306 are word lines, 307-315 are memory cells of the non-volatile combined memory device of the present invention, 316-318 are parasitic capacitances on the bit lines, 319 is a row decoder, 320 is a column decoder, 321-322 are multiplexers, 323 are sense amplifiers, 324 are refresh circuits, 325 are write drivers, 326 are buffers, 327 are inputs and outputs, and 328-330 are source lines.
The specific operation of the present invention is further illustrated below:
before performing read-write operation on the nonvolatile combined memory device disclosed by the embodiment of the invention, setting a bit line as an establishing voltage of the resistive random access memory to enable the resistive random access memory to be in a low-resistance state; setting the source line to zero potential and the word line to high potential;
when the write data is 1, setting the bit line of the storage unit to be high potential, and charging the storage capacitor; when the write data is 0, the bit line of the storage unit is set to be a low potential, and the storage capacitor discharges;
in a read operation, all source lines are set to zero potential, word lines are set to zero potential, bit lines are set to precharge voltage, and a first word line of a selected memory cell is set to high potential;
judging the current direction through a sense amplifier so as to read out data stored in a storage capacitor;
when detecting that the power supply is not powered down, rewriting the read data into the storage capacitor by using a refreshing circuit in the dynamic memory circuit;
when power failure is detected, writing the data read from the storage capacitor into the resistive random access memory through a cache;
when the stored data is 0, setting a high potential for the word line, setting a reset voltage on a source line, and writing the resistive random access memory into a high resistance state;
when the stored data is 1, the resistive random access memory is not modified;
when the power-on is detected, all word lines are set to be in a high potential, reading voltage of the resistive random access memory is set in all bit lines, the source lines are set to be in a zero potential, data stored in the resistive random access memory are read out, the data stored in the resistive random access memory are rewritten into the storage capacitor, and the resistive random access memory is set to be in a low resistance state.
As can be seen from the above description, in the embodiment of the present invention, the operation method of the nonvolatile combined memory device according to the present invention can control the two nonvolatile combined memory devices provided by the present invention to operate in the dynamic memory mode with low power consumption and high speed when the power supply is stable, and can store data in the operation mode of the nonvolatile resistive random access memory when the power supply is powered off, so as to implement the operation of the two nonvolatile combined memory devices with low power consumption, high speed and nonvolatile property according to the present invention.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
The logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, and the program may be stored in a computer readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (8)
1. A method of operating a non-electrical volatile combination memory device, the non-electrical volatile combination memory device comprising: memory cells, each of the memory cells comprising: the memory comprises a resistive random access memory, a storage capacitor, a transistor, a first word line, a second word line, a bit line, a parasitic capacitor and a source line, wherein one end of the storage capacitor is connected with the source end of the transistor, the other end of the storage capacitor is connected with one end of the resistive random access memory, the other end of the resistive random access memory is connected with the source line, the second word line is led out from the middle of the storage capacitor and the resistive random access memory, the grid electrode of the transistor is connected with the first word line, the drain electrode of the transistor is connected with the bit line, one end of the parasitic capacitor is connected with the bit line, and the other end of the parasitic capacitor is grounded; wherein the method of operating the non-electrical volatile combination memory device includes the steps of:
setting the first word lines of all the storage units to be at a low potential, setting the second word lines to be the establishment voltage of the resistive random access memory, grounding the source line, and writing the resistive random access memory into a low resistance state by the potential difference between the second word lines and the source line;
grounding the second word line, setting the first word line of the selected memory unit to be high potential, and writing the memory capacitor;
when the write data is 1, setting the bit line of the memory cell to be high potential, and charging the storage capacitor;
when the write data is 0, the bit line of the storage unit is set to be at a low potential, and the storage capacitor discharges;
in the reading operation, the first word line and the second word line are set to be zero potential, the bit line is set to be precharge voltage, and the first word line of the selected memory unit is set to be high potential;
and judging the current direction through a sense amplifier so as to read the data stored in the storage capacitor.
2. The method of operation of claim 1, further comprising:
when detecting that the power supply is not powered down, utilizing a refreshing circuit in the dynamic memory circuit to rewrite the read data into the storage capacitor;
when power failure is detected, writing the data read from the storage capacitor into the resistive random access memory through a cache;
when the stored data is 0, setting the second word line to be zero potential, setting a reset voltage on the source line, and writing the resistive random access memory to be in a high-resistance state;
when the stored data is 1, the resistive random access memory is not modified;
when the resistance change memory is detected to be powered on, the second word line is set to be the reading voltage of the resistance change memory, the source line is set to be the zero potential, data stored in the resistance change memory are read out, the data stored in the resistance change memory are rewritten into the storage capacitor, and the resistance change memory is set to be in a low resistance state.
3. The method of claim 1 or 2, wherein the storage capacitor is a stacked capacitor or a trench capacitor.
4. The operating method according to claim 1 or 2, wherein the resistive random access memory is further a phase change memory or a magnetic memory.
5. A method of operating a non-electrical volatile combination memory device, the non-electrical volatile combination memory device comprising: memory cells, each of the memory cells comprising: the resistive random access memory comprises a resistive random access memory, a storage capacitor, a transistor, a word line, a bit line, a parasitic capacitor and a source line, wherein the storage capacitor is connected with the resistive random access memory in parallel, a common end of the storage capacitor connected with the resistive random access memory in parallel is connected with a source end of the transistor, the other end of the storage capacitor is grounded, the other end of the resistive random access memory is connected with the source line, a grid electrode of the transistor is connected with the word line, a drain electrode of the transistor is connected with the bit line, one end of the parasitic capacitor is connected with the bit line, and the other end of the parasitic capacitor is grounded; wherein the method of operating the nonvolatile combination memory device includes the steps of:
setting the bit line as the establishment voltage of the resistive random access memory to change the resistive random access memory into a low-resistance state;
setting the source line to a zero potential and the word line to a high potential;
when the write data is 1, setting the bit line of the storage unit to be high potential, and charging the storage capacitor;
when the write data is 0, the bit line of the storage unit is set to be at a low potential, and the storage capacitor discharges;
in a read operation, setting all the source lines to zero potential, the word lines to zero potential, the bit lines to a precharge voltage, and the word lines selecting the memory cells to high potential;
and judging the current direction through a sense amplifier so as to read the data stored in the storage capacitor.
6. The method of operation of claim 5, further comprising:
when detecting that the power supply is not powered down, rewriting the read data into the storage capacitor by using a refreshing circuit in the dynamic memory circuit;
when power failure is detected, writing the data read from the storage capacitor into the resistive random access memory through a cache;
when the stored data is 0, setting the word line to be at a high potential, setting a reset voltage on the source line, and writing the resistive random access memory to be in a high-resistance state;
when the stored data is 1, the resistive random access memory is not modified;
when the resistance change memory is electrified, setting all the word lines to be at a high potential, setting the read voltage of the resistance change memory in all the bit lines, setting the source lines to be at a zero potential, reading data stored in the resistance change memory, rewriting the data stored in the resistance change memory into the storage capacitor, and setting the resistance change memory to be in a low resistance state.
7. The method of claim 5 or 6, wherein the storage capacitor is a stacked capacitor or a trench capacitor.
8. The operating method according to claim 5 or 6, wherein the resistive random access memory is further a phase change memory or a magnetic memory.
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| CN112509624B (en) * | 2020-12-14 | 2022-11-01 | 北京大学 | Circuit for setting resistive random access memory and operation method thereof |
| CN116762131A (en) * | 2021-03-18 | 2023-09-15 | 华为技术有限公司 | Memory and electronic equipment |
| CN113629013B (en) * | 2021-07-01 | 2024-03-15 | 芯盟科技有限公司 | Manufacturing method of memory device and memory |
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