KR20090060120A - Non volatile memory device and the reading method of the same - Google Patents

Abstract

A nonvolatile memory and a reading method for reading a memory cell without the interference of the adjacent memory cell are provided to reduce the number of sense amplifier by connecting the sense amplifier on a lower part of bit lines. A nonvolatile memory comprises a memory cell array(10), an upper bit line, a lower bit line, a word line and a sense amplifier. The memory cell array comprises the selection unit and the resistance unit. The resistance unit is connected to one end of the selection element. The upper bit line is connected to one end of the memory cell. The upper bit line is extended in row. The lower bit line is connected to the other end of the memory cell. The lower bit line is extended to the line writing direction. The word line is connected to the selection element.

Description

NON VOLATILE MEMORY DEVICE AND THE READING METHOD OF THE SAME}

The present invention relates to a memory device, and more particularly, to a nonvolatile memory device using a resistance element and a reading method thereof.

Nonvolatile random access memory (RAM) capable of high-speed operation in place of flash memory, including ferro-electric random access memory (FeRAM), magnetic resistance random access memory (MRAM), polymer random access memory (PoRAM), and phase change (PRAM) Various memory devices have been proposed, such as random access memory. FeRAM and MRAM are difficult to integrate. On the other hand, in the case of PoRAM using an organic material, high integration is easy. The PoRAM includes an upper electrode and a lower electrode, and an organic material is interposed between the upper electrode and the lower electrode. The amount of charge trapped in the organic material is changed according to the applied voltage. The resistance of the holding material changes with the amount of trapped charge. Thus, PoRAM is a storage device capable of storing binary information in accordance with the resistance of the organic material. The memory cell of the PoRAM may have a single resistance structure in which a resistance element is disposed between the word line and the bit line at the point where the word line and the bit line cross each other, which is advantageous in terms of high integration. However, a crosstalk phenomenon or a leakage current may occur in the memory cell array due to the electrical coupling effect of the resistor. The crosstalk or leakage current may cause the PoRAM to malfunction.

1 is a block diagram illustrating a method of reading a PoRAM according to the prior art. Referring to FIG. 1, the memory cell array 110 includes mxn memory cells arranged at intersections of word lines WL1 to WLm extending in a row direction and bit lines BL1 to BLn extending in a column direction. Has a structure. Each memory cell is composed of a resistance element (Mij). One end of the resistance element Mij is connected to the word line WLi and the other end is connected to the bit line BLj. The word lines WL1 to WLm are connected to the X-decoder 130, and the bit lines BL1 to BLn are connected to the Y-decoder 120.

When the resistance element is a polymer memory (PoRAM), a method of selecting and reading one memory cell M11 from a memory cell array will be described. The X-decoder 130 supplies a high voltage to the selected word line WL1 and applies a ground voltage to the unselected word lines WL2 to WLm. The Y-decoder 120 supplies a ground voltage to the selected bit line BL1 and applies a high voltage to the unselected bit lines BL2 to BLn. Under these conditions, a current path is formed through the selected word line WL1, the memory cell M11, and the selected bit line BL1. According to the resistance state of the memory cell M11, the current flowing through the selected bit line BL1 is different, so that information stored in the memory cell M11 may be read. However, a high voltage is also applied to unselected bit lines BL2 to BLn, so that a leakage current may flow through the unselected memory cells. Therefore, there is a need for a memory cell structure that can reduce interference between cells and accurately read the resistance state of a memory cell.

One object of the present invention is to provide a nonvolatile memory device that can be read without interference by adjacent memory cells.

One technical problem of the present invention is to provide a reading method of a nonvolatile memory device which can be read without interference by adjacent memory cells.

A nonvolatile memory device according to an embodiment of the present invention includes a memory cell including a resistance element and a selection element connected to one end of the resistance element, an upper bit line connected to one end of the memory cell and running in a row direction; A lower bit line connected to the other end of the memory cell and running in a row direction, and a word line connected to the selection device and running in a column direction, wherein a resistance state of the resistance element is determined according to electrical characteristics of the lower bit line. When detected, the memory cells are arranged in rows and columns to form a memory cell array.

In one embodiment of the present invention, the electrical characteristics of the lower bit line may be current or voltage.

In one embodiment of the present invention, the other end of the resistance element may be connected to the upper bit line.

In one embodiment of the present invention, further comprising a sense amplifier connected to the lower bit line, the sense amplifier may sense the current flowing through the upper bit line, the cell, the lower bit line.

In one embodiment of the present invention, further comprising a sense amplifier connected to the lower bit line, the sense amplifier may be provided for each of the lower bit line.

In one embodiment of the present invention, the sense amplifier further includes a buffer, the buffer may temporarily store data sensed by the sense amplifier.

The memory cell array may include a plurality of the lower bit lines, and further includes a sense amplifier connected to the lower bit line, wherein the sense amplifier is connected to the plurality of lower bit lines. Can be connected.

In one embodiment of the present invention, the memory cell may be any one of a polymer cell, a magnetoresistive memory cell, a phase change memory cell.

In a nonvolatile memory device according to an embodiment of the present invention, a nonvolatile memory device includes a memory cell in which a selection device and one end of the selection device are connected to one end of a resistance element, and one row of the memory cell are connected in a row direction. A lower bit line connected to the other end of the memory cell and proceeding in a row direction, and a word line connected to the selection device and traveling in a column direction, wherein the resistance state of the resistance element is Sensing according to the electrical characteristics of the lower bit line, the memory cells arranged in rows and columns to form a memory cell array, applying a first voltage to a word line connected to the selected memory cell, the upper bit connected to the selected memory cell Applying a third voltage to the line, and sensing a current flowing through the resistive element .

In an embodiment of the present disclosure, the sensing of the current flowing through the resistor element may be performed by a sense amplifier sensing the current flowing through the upper bit line, the cell, and the lower bit line.

In one embodiment of the present invention, the memory cell may be a polymer memory cell.

In a nonvolatile memory device according to an embodiment of the present invention, a nonvolatile memory device includes a memory cell in which a selection device and one end of the selection device are connected to one end of a resistance element, and one row of the memory cell are connected in a row direction. A lower bit line connected to the other end of the memory cell and proceeding in a row direction, and a word line connected to the selection device and traveling in a column direction, wherein the resistance state of the resistance element is The memory cells are sensed according to the electrical characteristics of the lower bit line, and the memory cells are arranged in rows and columns to form a memory cell array. In the method of reading the memory device, a memory cell connected to the word line by applying a first voltage to the word line Selecting a second voltage, applying a third voltage to upper bit lines connected to the selected memory cells, and the memo Sensing current flowing through the resistive element of the cells.

According to an embodiment of the present disclosure, in the sensing of a current flowing through the resistance element of the memory cells, a sense amplifier connected to each of the lower bit lines may include the upper bit line, the cell, And sensing current flowing through the lower bit line.

Selected memory cells of the nonvolatile memory device of the present invention can be read without interference by adjacent memory cells. In addition, the sense amplifier is commonly connected to the lower bit lines so that the number of sense amplifiers required is reduced. Therefore, the directivity of the nonvolatile memory device according to the present invention can be improved. Further, the nonvolatile memory device of the present invention can read a plurality of information at the same time.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 2, the control circuit 60 may receive an address signal through the address line 62. The address signal may be input to the X-decoder 30 and the Y-decoder 20 to select a specific memory cell of the memory cell array 10. Data of the selected memory cell is read through the read circuit 40 and input to the control circuit 60. The control circuit 60 may communicate the data with an external device (not shown) through the data line 63.

The control circuit 60 receives a control signal through the control line 61 to control the X-decoder 30, the Y-decoder 20, the readout circuit 40, and the voltage generation circuit 50. Can be. The control circuit 60 controls devices 20, 30, 40, and 50 arranged around the memory cell array 10 according to a read operation, a write operation, an erase operation, and the like of the memory cell array 10. can do. The X-decoder 30 may select a specific upper bit line by using the address signal. The Y-decoder 20 may select a specific word line using the address signal. The read circuit 40 may read data of a specific memory cell of the memory cell array. The read circuit 40 may be connected to the lower bit line. Data read by the read circuit 40 may be input to the control circuit 60. The control circuit 60 may transmit the data to an external device (not shown) through the data line 63. The voltage generation circuit 50 may supply a voltage necessary for the X-decoder 30, the Y-decoder 20, and the readout circuit 40. The voltage generation circuit 50 may generate a first voltage V1, a second voltage V2, a third voltage V3, and a fourth voltage V4. The first voltage V1 may be 3 V or less. The third voltage V2 may be 2 V or less. The second voltage V2 and the fourth voltage V4 may be grounded or floated.

In a read operation, the first voltage V1 is a voltage applied to a selected word line, a second voltage V2 is a voltage applied to an unselected word line, and a third voltage V3 is applied to a selected upper bit line. The voltage applied to the fourth voltage V4 may be a voltage applied to the unselected upper bit line.

3 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3, the memory cell Cij includes a selection element Tij and a resistor element Mij connected to one end of the selection element Tij. One end of the memory cell Cij is connected to the upper bit line BLia running in the row direction, and the other end of the memory cell Cij is connected to the lower bit line BLib running in the row direction. The word line WLj is connected to the selection element Tij and runs in the column direction. The memory array 210 includes a plurality of memory cells arranged in rows and columns. The resistance state of the resistance element Mij is sensed according to the electrical characteristics of the lower bit line BLib. The electrical property may be current or voltage.

The memory cell array 210 has a structure in which m x n memory cells are disposed at an intersection of word lines WL1 to WLn extending in a column direction and upper bit lines BL1 to BLm extending in a row direction. The memory cell Cij has a form in which the selection element Tij and the resistance element Mij are connected in series. The other end of the resistance element may be connected to the upper bit line or the lower bit line. The selection element Tij may be a transistor. The resistance element Mij may be any one of a polymer memory device, a magnetoresistive memory device, and a phase change memory device. The resistance element Mij may include other elements that may store information according to a resistance state, without being limited to the above-described elements. The memory cell array 210 may form an m x n matrix. For example, when the resistance element (Mij) is a polymer memory device, the resistance element (Mij) may include an organic material between the upper electrode and the lower electrode.

The word line WLj is connected to the selection element Tij of the memory cell Cij. When the selection element Tij is a transistor, the word line WLj may be connected to a gate of the transistor. The word line WLj proceeds in a column direction and may be connected to the selection element Tij of each memory cell Cij. The word line WLj may be connected to the Y decoder 220. The Y decoder 220 may select the word line WLj of the memory cell array 210 corresponding to the address line.

The bit line BL includes an upper bit line BLia and a lower bit line BLib. The upper bit line BLia may be connected to the other end of each memory cell Cij while going in a row direction. The upper bit line BLia may be electrically connected to the x decoder 230. The x-decoder 230 may select the upper bit line BLia of the memory cell array 210 corresponding to the address line. The lower bit line BLib is connected to the other end of the memory cell Cij and proceeds in a row direction. The lower bit line BLib is connected to the read circuit 240.

The read circuit 240 may include a sense amplifier 241. The sense amplifier 241 detects current flowing through the upper bit line BLia, the memory cell Cij, and the lower bit line BLib, and reads information stored in the memory cell Cij. Can be. Information stored in the memory cell Cij may be determined according to the resistance state of the resistor element Mij. The sense amplifier 241 may be commonly connected to the plurality of lower bit lines BL1 to BLm extending in the row direction. Specifically, a method of extracting information stored in the memory cell Cij will be described. The Y decoder 220 selects the word line WLj. Accordingly, the voltage of the selected word line WLj is changed to the first voltage V1, and the selection elements T1j to Tmj in the column direction connected to the word line WLj are turned on. do. However, voltages of word lines other than the selected word line WLj may be the second voltage V2. The X-decoder 230 may apply a third voltage V3 to the upper bit line BLia connected to the memory cell Cij. Accordingly, a voltage drop occurs between the upper bit line BLia and the lower bit line BLib. The sense amplifier 241 may sense a current flowing in the lower bit line BLib and determine a resistance state of the reservoir Mij according to the amount of the current.

4A and 4B are block diagrams illustrating memory cells of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, the memory cell C11 includes a selector T11 and a resistor M11 connected to one end of the selector T11. One end of the memory cell C11 is connected to the upper bit line BL1a running in the row direction, and the other end of the memory cell C11 is connected to the lower bit line BL1b running in the row direction. The word lines WL1 and 6 are connected to the selection element T11 and run in the column direction. The resistance state of the resistance elements M11 and 2 is sensed according to the electrical characteristics of the lower bit line BL1b. The other end of the resistance element M11 is connected to the upper bit line BL1a, and the other end of the selection element T11 is connected to the lower bit line BL1b. The lower bit line BL1b is connected to the sense amplifier SA. The sense amplifier SA may determine a resistance state of the resistance element M11 by measuring a current flowing in the lower bit line BL1b or a voltage of the lower bit line BL1b.

Referring to FIG. 4B, the other end of the resistance element M11 is connected to the lower bit line BL1b, and the other end of the selection element T11 is connected to the upper bit line BL1a. The lower bit line BL1b is connected to the sense amplifier SA. The sense amplifier SA may determine a resistance state of the resistance element M11 by measuring a current flowing in the lower bit line BL1b or a voltage of the lower bit line BL1b.

5 is a block diagram illustrating a nonvolatile memory device according to another embodiment of the present invention. Descriptions overlapping with those described in FIG. 3 will be omitted. Referring to FIG. 5, the sense amplifier 341 may be disposed for each lower bit line BL1b to BLmb. Accordingly, the output signal of the sense amplifier may be input to the buffer 344. The buffer 344 may temporarily store data sensed by the sense amplifier 341. The plurality of sense amplifiers 341 may form a sense amplifier block 342. The determination circuit 340 may include the sense amplifier block 342 and the buffer 344.

A method of reading in units of blocks according to this embodiment will be described. Specifically, a method of extracting stored information of the memory cells Ci1 will be described. I may be any one of 1 to m. That is, memory cells Ci1 connected to the first word line WL1 may be simultaneously read. The Y decoder 320 selects the word line WL1. Accordingly, the voltage of the word line WL1 is changed to the first voltage V1 to turn on the selection elements T11 to Tm1 in the column direction connected to the word line WL1. Can be. However, voltages of the word lines WL2 to WLn other than the selected word line WL1 may be the second voltage V2. The X decoder 30 may change the voltages of the upper bit lines BL1a to BLma connected to the memory cells Ci1 to a third voltage V3. As a result, a voltage difference occurs between the upper bit lines BL1a to BLma and the lower bit lines BL1b to BLmb. Sense amplifiers 341 connected to the lower bit lines BL1b to BLmb sense current flowing through the lower bit lines BL1b to BLmb, and sense the current flowing through the lower bit lines BL1b to BLmb. The resistance state can be determined simultaneously. The sense amplifiers 341 form a sense amplifier block 342. Information detected by the sense amplifier block 342 may be temporarily stored in the buffer 344. As described above, the plurality of memory cells may be simultaneously read by simultaneously applying the third voltage V3 to the upper bit lines BL1a to BLma.

6 is a block diagram schematically illustrating a computing system 1500 including a semiconductor memory system according to the present invention.

Referring to FIG. 6, the computing system 1500 may include a processor 1510, a controller 1520, input devices 1530, output devices 1540, nonvolatile memory 1550, and main memory 1560. It includes. Solid lines in the figures represent the system bus through which data or commands travel.

The computing system 1500 according to the present invention receives data from the outside through the input devices 1530 (keyboard, camera, etc.). The input data may be a command by a user or multimedia data such as image data by a camera or the like. The input data is stored in the nonvolatile memory device 1550 or the main memory device 1560.

The processing result by the processor 1510 is stored in the nonvolatile memory device 1550 or the main memory device 1560. The output devices 1540 output data stored in the nonvolatile memory device 1550 or the main memory device 1560. The output devices 1540 output digital data in a human detectable form. For example, the output device 1540 includes a display or a speaker.

An access method according to the present invention will be applied to the nonvolatile memory device 1550. As the reliability of the nonvolatile memory device 1550 is improved, the reliability of the computing system 1500 will also be proportionally improved.

The nonvolatile memory device 1550 and / or the controller 1520 may be mounted using various types of packages. For example, the nonvolatile memory device 1550 and / or the controller 1520 may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual. In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) , Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) ), Such as Wafer-Level Processed Stack Package (WSP).

Although not shown in the drawings, it is apparent to those skilled in the art that a power supply for supplying power for the operation of the computing system 1500 is required. In addition, when the computing system 1500 is a mobile device, a battery for supplying operating power of the computing system 1500 may be additionally required.

The semiconductor memory system according to the present invention can be used as a removable storage device. Therefore, it can be used as a storage device of MP3, digital camera, PDA, e-Book. It can also be used as a storage device such as a digital TV or a computer.

It will be apparent to those skilled in the art that the structure of the present invention may be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is believed that the present invention includes modifications and variations of this invention provided they come within the scope of the following claims and their equivalents.

1 is a block diagram illustrating a method of reading a PoRAM according to the prior art.

2 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

3 is a block diagram illustrating a nonvolatile memory device according to another embodiment of the present invention.

4A and 4B are block diagrams illustrating a memory cell of a nonvolatile memory device according to an embodiment of the present invention.

4 is a block diagram illustrating a nonvolatile memory device according to still another embodiment of the present invention.

6 is a block diagram schematically illustrating a computing system including a semiconductor memory system according to the present invention.

Claims (1)

 In the reading method of a nonvolatile memory device, The nonvolatile memory device includes a memory cell including a select element and a resistor connected to one end of the select element, an upper bit line connected to one end of the memory cell and running in a row direction, and connected to the other end of the memory cell. A lower bit line running in a row direction, a word line connected to the selection element and running in a column direction, and a sense amplifier connected to the lower bit line, wherein the memory cells are arranged in rows and columns to form a memory cell array; Lower bit lines are electrically connected to each other and are connected to the sense amplifier, Applying a first voltage to the word line connected to the selection device; Applying a second voltage to the upper bit line; And And detecting the current flowing through the resistive element by the sense amplifier.

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