KR20100050847A - Resistive memory chip - Google Patents
Resistive memory chip Download PDFInfo
- Publication number
- KR20100050847A KR20100050847A KR1020080109945A KR20080109945A KR20100050847A KR 20100050847 A KR20100050847 A KR 20100050847A KR 1020080109945 A KR1020080109945 A KR 1020080109945A KR 20080109945 A KR20080109945 A KR 20080109945A KR 20100050847 A KR20100050847 A KR 20100050847A
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- Prior art keywords
- array
- resistive memory
- read
- data
- memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
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- Semiconductor Memories (AREA)
Abstract
Description
The present invention relates to a resistive memory chip, and more particularly, to a resistive memory chip having improved performance and reduced manufacturing cost.
Nonvolatile memory chips using a resistive material include a resistive memory chip (RRAM), a phase change random access memory (PRAM), and a magnetic memory chip (MRAM). Dynamic memory (DRAM) or flash memory devices use charge to store data, while nonvolatile memory devices using resistors are used for resistive change (RRAM) and chalcogenide alloys in variable resistors. Data is stored using a state change (PRAM) of a phase change material such as an alloy), a resistance change (MRAM) of a magnetic tunnel junction (MTJ) thin film according to a magnetization state of a ferromagnetic material, and the like.
Here, the resistive memory cell includes a variable resistance material between the upper electrode and the lower electrode, and has a characteristic that the resistance level of the variable resistance material changes according to voltages provided to the upper and lower electrodes. Examples of such a resistive memory cell are disclosed in US Patent Publication No. 2005-58009, US Patent Publication No. 2004-27849, and the like. In particular, a filament is formed in the variable resistance material to serve as a current path of the cell current, and the state in which the filament is partially broken is defined as a reset state, a high resistance state, and reset data (1 data). The filament connected state is defined as set state, low resistance state and set data (0 data).
Write reset data to a resistor memory cell by providing a reset voltage having a voltage level sufficient to break the filament, and write set data to a resistor memory cell by providing a set voltage having a voltage level that can connect the filament again. . In addition, a voltage having a voltage level low enough that the filament state does not change is provided to read whether the stored data is reset data or set data.
SUMMARY OF THE INVENTION An object of the present invention is to provide a resistive memory chip having improved performance and reduced manufacturing cost.
The problem to be solved by the present invention is not limited to the above-mentioned problem, another task that is not mentioned will be clearly understood by those skilled in the art from the following description.
One aspect of the resistive memory chip of the present invention for solving the above problems is a plurality of resistive memory cells in which a plurality of bit lines, a plurality of word lines and each resistive memory cell are coupled with each bit line and each word line. A first memory comprising a first array comprising: And a second array including a plurality of bit lines, a plurality of word lines, and a plurality of resistive memory cells coupled to each bit line and each word line, the second array having a different array size from the first array. And a second memory comprising an array.
Another aspect of the resistive memory chip of the present invention for solving the above problems includes a first array and a second array having a different array size from the first array. The resistive memory chip includes a memory interface in which a first interface that accesses the first array and a second interface that access the second array are physically integrated into one.
Other specific details of the invention are included in the detailed description and drawings.
Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.
When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected to or coupled with another element or through another element in between. This includes all cases. On the other hand, when one device is referred to as "directly connected to" or "directly coupled to" with another device indicates that no other device is intervened. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.
Although the first, second, etc. are used to describe various elements, components and / or sections, these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first device, the first component, or the first section mentioned below may be a second device, a second component, or a second section within the spirit of the present invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.
Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.
1 is a block diagram illustrating a resistive memory chip according to example embodiments.
Referring to FIG. 1, the
The
In the present invention, an array may be defined as a set of resistive memory cells that become a minimum operation unit. Here, the minimum operation unit may be a minimum unit that is activated to read data from a cell or write data to a cell. In this case, active means applying a voltage to a word line and a bit line. After activation, data may be read from or written to selected cells included in the array. Or an array is a set of cells that can be selected by either
The
The
Although not shown exactly in the figure, the
The resistive memory cell may include a variable resistance element having different resistance levels according to data, and an access element for controlling a cell current flowing through the variable resistance element. The variable resistance element may have a filament formed as a current path of the cell current inside. The reset data may be defined as a case where the filament is partially broken, and the set data may be defined as a case where the filament is connected. have. Such a variable resistance element may use, for example, a material such as NiO. In addition, the access element may be a FET transistor, a diode, a PNP bipolar transistor, an NPN bipolar transistor, or the like.
The
The sense amplifier and write
The
The
The
The X-decoder 620 and the Y-
The
Specifically, a DRAM will be described in detail. In the DRAM, a refresh operation is essential. The refresh operation is described below. Each memory cell of a DRAM is composed of one switching transistor and one information storage capacitor. The DRAM also includes a sense amplifier consisting of a pair of bit lines and bit bar lines. When the refresh command is input to the DRAM, the selected word line is boosted to turn on the switching transistor. Then, the data stored in the information storage capacitor is moved to the bit line or bit bar line. At this point, the potential difference between the bit line and the bitbar line is small, but the slight difference is sensed by the sense amplifier and amplified by information of '1' or '0', respectively. After amplification, when the word line is pushed down and the switching transistor is turned off, the information in the memory cell is preserved as amplified data. However, as the array size of the DRAM increases, the bit line may become longer and the capacitance of the bit line may increase. If the capacitance of this bit line is too large, the noise for the potential difference that the sense amplifier senses can be large. Therefore, in the case of DRAM, there is a limitation as described above for adjusting the array size.
Unlike these, the
In the
FIG. 2 is a block diagram illustrating the high speed array of FIG. 1 included in the resistive memory chip according to the first exemplary embodiment of the present invention. 2 illustrates an X-decoder 620 and a Y-
Referring to FIG. 2, the
According to the structure shown in FIG. 2, for example, a global bit line (not shown) may be provided to reduce the number of cells of the sense amplifier and write
3 is a block diagram illustrating the high speed array of FIG. 1 included in a resistive memory chip according to a second exemplary embodiment of the present invention. 3 illustrates an X-decoder 620 and a Y-
Referring to FIG. 3, the
According to the structure shown in FIG. 3, compared to the structure shown in FIG. 2, since the sense amplifier and the
In a resistive memory chip according to example embodiments, different sensing schemes may be used according to each resistive memory. 4 to 14, different sensing schemes are used according to each resistance memory.
Fig. 4 is a circuit diagram showing one cell of a read sense amplifier and a write driver used in a storage memory.
The read sense amplifier and write
If the high density array has a memory capacity of, for example, 16Gbit, the read sense amplifier and write driver used for the memory for storage need cells of 4Kbyte to 16Kbyte, so the size of each cell must be made small.
Referring to FIG. 4, the read sense amplifier and the
5 to 7, the write method in the read sense amplifier and the
First, referring to FIG. 5, an address for writing data is set up, the transistor Den is turned on, and the data is stored in a latch through the transistor DI / transistor nDI (Data Loading). .
Subsequently, referring to FIG. 6, the word line WL and the bit line BL are precharged (BL precharge). The voltage Vpp may be applied to the gate of the transistor BLSi, and each word line WL may be a ground voltage (for example, 0V) by the charge path illustrated in FIG. 6.
Subsequently, referring to FIG. 7, zero or one data is written by adjusting a voltage applied to the gate of the transistor SET / transistor RESET and a current flowing through the drain / source of the transistor SET / transistor RESET. (WL Enable). At this time, the voltage of the selected word line (Sel. WL) may be Vwrite.
Subsequently, the write process is terminated through a recovery period.
Meanwhile, the read sense amplifier and the
First, referring to FIG. 8, the transistor Den is turned on and a latch is reset through the transistor nDI. At the same time, the bit line is discharged through the transistor DIS.
9, the word line is enabled (WL Enable), and the bit line connected to the resistive memory cell to read data is developed. At this time, the voltage of the selected word line Sel. WL may be Vread.
Next, referring to FIG. 10, sensing and data latching are performed. A transistor connected in series with the transistor BLSi, the transistor LCH and the transistor LCH is turned on, and a closed loop shown by an arrow in FIG. 10 is formed to form a bit line connected with a resistive memory cell to read data. The voltage level is sensed and can also latch data.
This completes the read process.
Fig. 11 is a circuit diagram showing one cell of a read sense amplifier and a write driver used in the random access memory.
The read sense amplifier and write
When the high speed array has a memory capacity of, for example, 16 Mbit, the read sense amplifier and write
Referring to FIG. 11, unlike in FIG. 4, the
Since the write method of the
The
First, referring to FIG. 12, an address for reading data is set up, and a bit line is discharged through a transistor DIS (BL Discharge).
13, the word line is enabled (WL Enable). At this time, the voltage of the selected word line Sel. WL may be Vread.
14, the bit line BL is set up (BL Set-up) and data is output through the comparator (Data Out).
In more detail, a constant current may flow in a transistor Vbias in which a constant bias voltage is applied to the gate and a transistor connected in series with the drain and the gate. In addition, a variable current may flow in the transistor REN to which the read enable signal is applied to the gate and the transistor connected in series. The magnitude of the variable current depends on the resistance level of the resistive memory cell to be read, resulting in the magnitude of the voltage applied to the plus terminal of the comparator. The comparator may output a logic high or logic low value to the output terminal Dout of the comparator by comparing the magnitude of the voltage applied to the plus terminal and the reference voltage ref applied to the minus terminal.
This completes the read process.
According to the current sensing, data can be read at a higher speed than in the case of voltage sensing. This is because voltage sensing does not require the required developer time. Therefore, such a current sensing can improve the data rate in the random access memory.
Referring to FIG. 15, a memory interface of a resistive memory chip according to an exemplary embodiment will be described. 15 is a block diagram illustrating a memory interface of a resistive memory chip according to an exemplary embodiment of the present invention.
In the
Referring to FIG. 15, it may be configured to physically include one memory access interface (Memory I / F), but logically operate as if it includes two memory access interfaces. Specifically, the access mode may be switched by providing a mode selection signal to control data latency and data access speed of the
Alternatively, you can switch the access mode by changing the pin map. For example, if the mode selection signal is logical 0, it has a pin map of the storage access interface, and if the
By physically including only one memory access interface (Memory I / F), not only the address pin and the data pin can be shared, but also the command pin and the control pin can be shared, thereby reducing manufacturing costs.
Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.
1 is a block diagram illustrating a resistive memory chip according to example embodiments.
FIG. 2 is a block diagram illustrating the high speed array of FIG. 1 included in the resistive memory chip according to the first exemplary embodiment of the present invention.
3 is a block diagram illustrating the high speed array of FIG. 1 included in a resistive memory chip according to a second exemplary embodiment of the present invention.
Fig. 4 is a circuit diagram showing one cell of a read sense amplifier and a write driver used in a storage memory.
5 to 7 are circuit diagrams for describing a write method of the read sense amplifier and the write driver illustrated in FIG. 4.
8 through 10 are circuit diagrams for describing a read method of the read sense amplifier and the write driver illustrated in FIG. 4.
Fig. 11 is a circuit diagram showing one cell of a read sense amplifier and a write driver used in the random access memory.
12 to 14 are circuit diagrams for describing a read method of the read sense amplifier illustrated in FIG. 11.
15 is a block diagram illustrating a memory interface of a resistive memory chip according to an exemplary embodiment of the present invention.
(Explanation of symbols for the main parts of the drawing)
10: resistive memory chip 20: host
100: memory for storage 110: high density array
120: X-decoder 130: Y-decoder
200: sense amplifier and light driver
500: mode controller 600: random access memory
800: peripheral circuit area
Claims (10)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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KR1020080109945A KR20100050847A (en) | 2008-11-06 | 2008-11-06 | Resistive memory chip |
US12/613,832 US8045363B2 (en) | 2008-11-06 | 2009-11-06 | Variable resistance memory devices including arrays of different sizes |
Applications Claiming Priority (1)
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KR1020080109945A KR20100050847A (en) | 2008-11-06 | 2008-11-06 | Resistive memory chip |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10204670B2 (en) | 2012-05-17 | 2019-02-12 | Samsung Electronics Co., Ltd. | Spin transfer torque magnetic random access memory for supporting operational modes with mode register |
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2008
- 2008-11-06 KR KR1020080109945A patent/KR20100050847A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10204670B2 (en) | 2012-05-17 | 2019-02-12 | Samsung Electronics Co., Ltd. | Spin transfer torque magnetic random access memory for supporting operational modes with mode register |
US10446207B2 (en) | 2012-05-17 | 2019-10-15 | Samsung Electronics Co., Ltd. | Spin transfer torque magnetic random access memory for supporting operational modes with mode register |
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