CN112054866A - Clock synchronization device with clock holding capability - Google Patents
Clock synchronization device with clock holding capability Download PDFInfo
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- CN112054866A CN112054866A CN202010834679.XA CN202010834679A CN112054866A CN 112054866 A CN112054866 A CN 112054866A CN 202010834679 A CN202010834679 A CN 202010834679A CN 112054866 A CN112054866 A CN 112054866A
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- 239000013078 crystal Substances 0.000 claims description 18
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000003044 adaptive effect Effects 0.000 claims description 3
- 230000006870 function Effects 0.000 claims description 3
- 230000014759 maintenance of location Effects 0.000 claims description 2
- 238000012423 maintenance Methods 0.000 claims 3
- 238000005259 measurement Methods 0.000 abstract description 28
- 238000010586 diagram Methods 0.000 description 7
- 239000013307 optical fiber Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/24—Arrangements for preventing or reducing oscillations of power in networks
- H02J3/242—Arrangements for preventing or reducing oscillations of power in networks using phasor measuring units [PMU]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/70—Smart grids as climate change mitigation technology in the energy generation sector
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/22—Flexible AC transmission systems [FACTS] or power factor or reactive power compensating or correcting units
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a clock synchronization device with clock holding capacity, comprising: the system comprises an Ethernet interface module, a clock frequency division module, a processor module, a power supply circuit and a connector; the output end of the Ethernet interface module is respectively connected with the input end of the clock frequency division module, the input end of the processor module and the input end of the connector; the output end of the clock frequency division module is respectively connected with the input end of the Ethernet interface module, the input end of the processor module and the input end of the connector; the output end of the processor module is respectively connected with the input end of the Ethernet interface module, the input end of the clock frequency division module and the input end of the connector; the power supply circuit provides power for the Ethernet interface module, the clock frequency division module and the processor module. The clock synchronization device with the clock holding capacity can synchronize the time of the phasor measurement unit and realize high-precision high-stability time synchronization, thereby ensuring the measurement precision of each synchronized phasor measurement unit.
Description
Technical Field
The invention relates to the technical field of synchronous clocks of power systems, in particular to a clock synchronization device with clock holding capacity.
Background
A Global Positioning System (GPS) -based Wide Area Measurement System (WAMS) is a new technology rapidly developed in recent years, and adopts a synchronous phase angle measurement technology to realize real-time high-speed acquisition of a whole network synchronous phase angle and main data of a power grid by gradually arranging synchronous phase angle measurement units (PMUs) of key measurement points of the whole network. The synchronous Phasor Measurement Unit (PMU) is an important device, is a high-precision measurement device capable of measuring the voltage phasor of the bus, can be used in the fields of dynamic monitoring, system protection, system analysis and prediction and the like of a power system, and is an important device for ensuring the safe operation of a power grid.
Therefore, a synchronous clock device capable of ensuring the measurement accuracy of each phasor measurement unit is required.
Disclosure of Invention
The embodiment of the invention provides a clock synchronization device with clock holding capacity, which can synchronize the time of a phasor measurement unit and realize high-precision high-stability time synchronization, thereby ensuring the measurement precision of each synchronized phasor measurement unit.
An embodiment of the present invention provides a clock synchronization apparatus with clock holding capability, including: the system comprises an Ethernet interface module, a clock frequency division module, a processor module, a power supply circuit and a connector;
the output end of the Ethernet interface module is respectively connected with the input end of the clock frequency division module, the input end of the processor module and the input end of the connector;
the output end of the clock frequency division module is respectively connected with the input end of the Ethernet interface module, the input end of the processor module and the input end of the connector;
the output end of the processor module is respectively connected with the input end of the Ethernet interface module, the input end of the clock frequency division module and the input end of the connector;
the power supply circuit provides power for the Ethernet interface module, the clock frequency division module and the processor module.
As an improvement of the scheme, the Ethernet interface module comprises an 10/100MHz self-adaptive 1588v2 precision network synchronous protocol switch chip.
As an improvement of the above scheme, the clock division module includes: the constant-temperature crystal oscillator, the digital-to-analog converter, the clock synchronization circuit and the clock frequency division circuit;
the frequency of the constant-temperature crystal oscillator is 10MHz, and the frequency stability of the constant-temperature crystal oscillator is more than 0.01 ppm; the constant-temperature crystal oscillator also has a voltage-controlled frequency fine-tuning function, and the frequency adjusting range is not less than +/-2 ppm.
As an improvement of the scheme, the clock synchronization circuit and the clock frequency division circuit comprise CPLDs with digital phase-locked loops.
As an improvement of the above scheme, the processor module comprises a single chip microcomputer and a memory;
the single chip microcomputer is based on an ARM-cortex series single chip microcomputer, the operating frequency is not less than 200MHz, and the single chip microcomputer is provided with an MII Ethernet interface.
As an improvement of the scheme, the memory is a NOR-Flash memory chip with an SPI interface, the capacity of the memory is not less than 8Mbyte, and the read-write clock frequency is not less than 30 MHz.
As an improvement of the above scheme, the power supply circuit comprises a synchronous BUCK conversion chip; the synchronous BUCK voltage reduction conversion chip generates 3.3V and 1.2V voltages from 5V input voltage, so that power is supplied to the Ethernet interface module, the clock frequency division module and the processor module.
As a modification of the above, the connectors include an ethernet signal connector and a clock/configuration signal connector.
The clock synchronization device with the clock holding capability provided by the embodiment of the invention has the following beneficial effects:
the precision clock synchronization protocol standard IEEE1588v2 based on the network measurement and control system adopts optical fiber or electric Ethernet, can realize the high-precision high-stability synchronization of the synchronized phasor measurement device and the synchronized master clock device, the estimated synchronization error is less than or equal to 50ns, and can meet the requirement of synchronized phasor measurement;
the adjusted and calibrated voltage-controlled constant-temperature crystal oscillator is used as a core of local clock timekeeping, and can still maintain higher synchronization precision under the condition that a main clock synchronization time reference signal is lost for a short time, the timekeeping precision is less than or equal to 10us/24h, and the requirement of synchronous phasor measurement can be met; the time synchronization device can synchronize the time of the phasor measurement unit with high precision and high stability, thereby ensuring the measurement precision of each synchrophasor measurement unit.
Drawings
Fig. 1 is a schematic structural diagram of a clock synchronization apparatus with clock holding capability according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of an ethernet interface module according to an embodiment of the present invention.
Fig. 3 is a block diagram of a clock divider module according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a digital-to-analog converter and a constant temperature crystal oscillator in the clock divider module according to the embodiment of the present invention.
FIG. 5 is a block diagram of a processor module according to an embodiment of the invention.
Fig. 6 is a schematic diagram of a power supply circuit provided by an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a schematic structural diagram of a clock synchronization apparatus with clock holding capability according to an embodiment of the present invention is shown, including: the system comprises an Ethernet interface module 1, a clock frequency division module 2, a processor module 3, a power supply circuit 4 and a connector 5;
the output end of the Ethernet interface module 1 is respectively connected with the input end of the clock frequency division module 2, the input end of the processor module 3 and the input end of the connector 5;
the output end of the clock frequency division module 2 is respectively connected with the input end of the Ethernet interface module 1, the input end of the processor module 3 and the input end of the connector 5;
the output end of the processor module 3 is respectively connected with the input end of the Ethernet interface module 1, the input end of the clock frequency division module 2 and the input end of the connector 5;
the power supply circuit 4 supplies power to the ethernet interface module 1, the clock divider module 2 and the processor module 3 via the connector 5.
Specifically, the connector 5 is a high-speed connector; the clock frequency division module 2 is provided with 1PPS and two paths of adjustable clock signals which are connected to the connector 5, and is provided with two paths of clock signals of 1PPS and 25MHz and an Ethernet interface module. The processor module 3 has a UART1 and a UART2 two-way serial interface connected to the connector 5, and has an SPI interface and a 10MHz clock signal connected to the clock divider module 2. The power supply circuit 4 obtains 5V input voltage through the connector 5 to generate two paths of power supplies of 3.3V and 1.2V. The digital Ground (GND) and the Analog Ground (AGND) are connected via a feedthrough inductor L1.
Specifically, the ethernet interface module 1 has two hundred mega ethernet signals connected to the outside through an ethernet signal connector, and three signals, i.e., a 1PPS (pulse per second), a control signal (SPI interface), and an MII (media independent interface) interface, are connected to the processor module 3. As shown in fig. 2, the ethernet interface module 1 adopts an 10/100MHz adaptive 1588v2 precision network synchronization protocol switch chip with model number KSZ8463 manufactured by MicroChip company, and can realize sub-microsecond synchronization by using a hardware-based timestamp and a transparent clock. The chip is provided with 1 path of MII interfaces, can provide no less than two paths of external and external network interfaces, and can support optical fibers or electric Ethernet. The supply voltage of the ethernet interface module 1 is 3.3V and 1.2V.
Specifically, as in the ethernet interface module 1 shown in fig. 2, the signals of the ethernet interface module 1 and the clock divider module are 1PPS and 25 MHZ.
Specifically, in the ethernet interface module 1 shown in fig. 2, signals of the ethernet interface module 1 connected to the ethernet signal connector are shown in the following table:
specifically, in the ethernet interface module 1 shown in fig. 2, signals of the ethernet interface module 1 connected to the processor module 3 are shown in the following table:
further, the ethernet interface module 1 comprises an 10/100MHz adaptive 1588v2 precision network synchronous protocol switch chip.
Specifically, the ethernet interface module 1 can provide at least two external network interfaces, and can support optical fiber or electrical ethernet.
Further, the clock division block 2 includes: the constant-temperature crystal oscillator, the digital-to-analog converter, the clock synchronization circuit and the clock frequency division circuit;
wherein the frequency of the constant-temperature crystal oscillator is 10MHz, and the frequency stability of the constant-temperature crystal oscillator is more than 0.01 ppm; the constant temperature crystal oscillator also has a voltage-controlled frequency fine adjustment function, and the frequency adjustment range is not less than +/-2 ppm.
Further, the clock synchronization circuit and the clock division circuit include a CPLD provided with a digital phase locked loop.
Specifically, as shown in fig. 3, the clock dividing circuit included in the clock dividing module 2 is composed of a CPLD having a digital phase-locked loop, the model of which is MAX5M160Z, and has 160 logic units and two digital phase-locked loops, the pin count of which is 64, and the power supply voltage is 3.3V.
Specifically, as shown in fig. 3 and 4, the D/a converter is designed by a DAC8851-Q1 digital-to-analog converter, and the processor module 3 sends data to the digital-to-analog converter through an SPI interface, and the data is converted into an analog quantity of 0-2.5V by the chip, so as to fine-tune the output frequency of the voltage-controlled constant-temperature crystal oscillator to calibrate the constant-temperature crystal oscillator. In fig. 4, U2 denotes a D/a converter, XO2 denotes a voltage-controlled oven crystal, and C30 denotes a capacitor.
Further, the processor module 3 comprises a single chip microcomputer and a memory;
the singlechip is based on ARM-cortex series singlechip, the operating frequency is not less than 200MHz, and the singlechip is provided with an MII Ethernet interface.
As shown in fig. 5, the processor module 3 includes a single chip and a memory, and is connected to the ethernet interface module 1 and the clock divider module 2. The specific type of the singlechip adopted by the processor module 3 is STM32F765, the singlechip has an Arm 32-bit Cortex-M7 inner core, and is provided with a double-precision floating point operation unit, the operation frequency is 216MHz, and the singlechip is provided with a Flash memory with the capacity of 2MB and an SRAM memory with the capacity of 512 kB. The system comprises a hundred-mega Ethernet controller with an MII or RMII interface, a 6-path SPI interface controller and a 4-path UART interface controller.
Further, the memory is a NOR-Flash (non-volatile Flash) memory chip with an SPI interface, the capacity of the memory chip is not less than 8Mbyte, and the read-write clock frequency is not less than 30 MHz.
Further, the power supply circuit 4 includes a synchronous BUCK conversion chip; the synchronous BUCK voltage reduction conversion chip generates 3.3V and 1.2V voltages from 5V input voltage, so that power is supplied to the Ethernet interface module 1, the clock frequency division module 2 and the processor module 3.
As shown in fig. 6, the power supply circuit 4 is composed of a synchronous BUCK conversion chip, and can generate 3.3V and 1.2V voltages from a 5V input voltage to supply power to the ethernet high-precision synchronous clock module with clock retention capability. The model of a chip generating 3.3V voltage is NCP3170B, the maximum output current is 3A, the model of a chip generating 1.2V voltage is TPS622242, and the maximum output current is 0.5A.
Specifically, as shown in fig. 6, the chip model number that generates a voltage of 3.3V is NCP3170B, and the maximum output current of the chip is 3A. The chip generates 3.3V voltage through the cooperation of resistors R2, R3, R5 and C5, in addition, R4 and C6 form a soft start circuit, L3 is an output inductor, and C3 and C4 are filter capacitors.
Specifically, as shown in fig. 6, the chip model number generating 1.2V is TPS622242, and the maximum output current is 0.5A. In the figure, L2 is an output inductor, and C1 and C2 are filter capacitors.
Further, the connector 5 comprises an ethernet signal connector 5 and a clock/configuration signal connector 5.
The clock synchronization device, the clock synchronization device and the storage medium with the clock holding capacity provided by the embodiment of the invention have the following beneficial effects:
the precision clock synchronization protocol standard IEEE1588v2 based on the network measurement and control system adopts optical fiber or electric Ethernet, can realize the high-precision high-stability synchronization of the synchronized phasor measurement device and the synchronized master clock device, the estimated synchronization error is less than or equal to 50ns, and can meet the requirement of synchronized phasor measurement;
the adjusted and calibrated voltage-controlled constant-temperature crystal oscillator is used as a core of local clock timekeeping, and can still maintain higher synchronization precision under the condition that a main clock synchronization time reference signal is lost for a short time, the timekeeping precision is less than or equal to 10us/24h, and the requirement of synchronous phasor measurement can be met; the time synchronization device can synchronize the time of the phasor measurement unit with high precision and high stability, thereby ensuring the measurement precision of each synchrophasor measurement unit.
It should be noted that the above-described device embodiments are merely illustrative, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of the embodiment of the apparatus provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, and may be specifically implemented as one or more communication buses or signal lines. One of ordinary skill in the art can understand and implement it without inventive effort.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (8)
1. A clock synchronization apparatus having clock holding capability, comprising: the system comprises an Ethernet interface module, a clock frequency division module, a processor module, a power supply circuit and a connector;
the output end of the Ethernet interface module is respectively connected with the input end of the clock frequency division module, the input end of the processor module and the input end of the connector;
the output end of the clock frequency division module is respectively connected with the input end of the Ethernet interface module, the input end of the processor module and the input end of the connector;
the output end of the processor module is respectively connected with the input end of the Ethernet interface module, the input end of the clock frequency division module and the input end of the connector;
the power supply circuit provides power for the Ethernet interface module, the clock frequency division module and the processor module through the connector.
2. The clock synchronization apparatus with clock maintenance capability of claim 1, wherein the ethernet interface module comprises an 10/100MHz adaptive 1588v2 precision network synchronization protocol switch chip.
3. The clock synchronization apparatus with clock maintenance capability of claim 1, wherein the clock division module comprises: the constant-temperature crystal oscillator, the digital-to-analog converter, the clock synchronization circuit and the clock frequency division circuit;
the frequency of the constant-temperature crystal oscillator is 10MHz, and the frequency stability of the constant-temperature crystal oscillator is more than 0.01 ppm; the constant-temperature crystal oscillator also has a voltage-controlled frequency fine-tuning function, and the frequency adjusting range is not less than +/-2 ppm.
4. A clock synchronization apparatus with clock hold capability as claimed in claim 3 wherein said clock synchronization circuit and clock divider circuit comprise CPLDs with digital phase locked loops.
5. The clock synchronization apparatus with clock maintenance capability of claim 1, wherein the processor module comprises a single chip and a memory;
the single chip microcomputer is based on an ARM-cortex series single chip microcomputer, the operating frequency is not less than 200MHz, and the single chip microcomputer is provided with an MII Ethernet interface.
6. The clock synchronization apparatus with clock retention capability of claim 5, wherein the memory is a NOR-Flash memory chip with SPI interface, and has a capacity not less than 8Mbyte and a read-write clock frequency not less than 30 MHz.
7. The clock synchronization apparatus with clock holding capability of claim 1, wherein the power supply circuit comprises a synchronous BUCK conversion chip; the synchronous BUCK voltage reduction conversion chip generates 3.3V and 1.2V voltages from 5V input voltage, so that power is supplied to the Ethernet interface module, the clock frequency division module and the processor module.
8. The clock synchronization apparatus with clock holding capability of claim 1, wherein the connectors comprise an ethernet signal connector and a clock/configuration signal connector.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010834679.XA CN112054866A (en) | 2020-08-18 | 2020-08-18 | Clock synchronization device with clock holding capability |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010834679.XA CN112054866A (en) | 2020-08-18 | 2020-08-18 | Clock synchronization device with clock holding capability |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113096293A (en) * | 2021-03-17 | 2021-07-09 | 国网河北省电力有限公司邯郸供电分公司 | Intelligent access system of transformer substation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102781090A (en) * | 2012-06-28 | 2012-11-14 | 华为技术有限公司 | Multimode base station and implementation method |
| US9094908B1 (en) * | 2014-04-22 | 2015-07-28 | Freescale Semiconductor, Inc. | Device and method for synchronization in a mobile communication system |
| CN106209342A (en) * | 2016-08-25 | 2016-12-07 | 四川灵通电讯有限公司 | The system and method for low-frequency clock transmission are realized in xDSL transmission system |
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2020
- 2020-08-18 CN CN202010834679.XA patent/CN112054866A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102781090A (en) * | 2012-06-28 | 2012-11-14 | 华为技术有限公司 | Multimode base station and implementation method |
| US9094908B1 (en) * | 2014-04-22 | 2015-07-28 | Freescale Semiconductor, Inc. | Device and method for synchronization in a mobile communication system |
| CN106209342A (en) * | 2016-08-25 | 2016-12-07 | 四川灵通电讯有限公司 | The system and method for low-frequency clock transmission are realized in xDSL transmission system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113096293A (en) * | 2021-03-17 | 2021-07-09 | 国网河北省电力有限公司邯郸供电分公司 | Intelligent access system of transformer substation |
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Application publication date: 20201208 |