CN112054004A - Chip, substrate, chip packaging assembly, packaging method of chip packaging assembly and camera module - Google Patents

Chip, substrate, chip packaging assembly, packaging method of chip packaging assembly and camera module Download PDF

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Publication number
CN112054004A
CN112054004A CN201910492134.2A CN201910492134A CN112054004A CN 112054004 A CN112054004 A CN 112054004A CN 201910492134 A CN201910492134 A CN 201910492134A CN 112054004 A CN112054004 A CN 112054004A
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Prior art keywords
chip
substrate
outer side
terminal
open slot
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CN201910492134.2A
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Chinese (zh)
Inventor
王文君
刘新建
李旻彦
张源吉
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Nanchang OFilm Optoelectronics Technology Co Ltd
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Nanchang OFilm Optoelectronics Technology Co Ltd
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Priority to CN201910492134.2A priority Critical patent/CN112054004A/en
Publication of CN112054004A publication Critical patent/CN112054004A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The invention relates to a chip, a substrate, a chip packaging assembly, a packaging method thereof and a camera module. The chip comprises: the first body comprises a first surface, a second surface and an outer side surface which are opposite; the first welding terminal is arranged on the outer side surface; when the chip is packaged on the substrate provided with the open slot, the outer side surface of the chip is matched with the inner side surface of the substrate, so that the chip is supported on the substrate through the mutually matched abutting force in the circumferential direction, and the first welding terminal is abutted and electrically connected with the second welding terminal arranged on the inner side surface of the open slot. When the chip is packaged with the corresponding substrate, the step of bonding a gold thread between the first welding terminal of the chip and the second welding terminal of the substrate can be omitted, and the space occupied by the arc-shaped gold thread in the chip packaging assembly is avoided. And the chip and the substrate are supported on the substrate through the mutually matched abutting force in the circumferential direction, so that a chip packaging assembly with smaller thickness is more favorably obtained.

Description

Chip, substrate, chip packaging assembly, packaging method of chip packaging assembly and camera module
Technical Field
The invention relates to the technical field of chips, in particular to a chip, a substrate, a chip packaging assembly, a packaging method of the chip packaging assembly and a camera module.
Background
The chip is known as the heart of the electronic product. In recent years, as the electronic product market has been increasingly demanding for miniaturization, high performance, and high reliability of electronic devices, new requirements for chip packaging have been made. The chip package is further developed toward miniaturization, ultra-thinning, integration and high performance. The mainstream packaging methods in the market at present include cob (chip on board) packaging, fc (flip chip) packaging, and the like.
As shown in fig. 1, in the COB package, a chip 2 is directly attached to a substrate 1 through an electrically/thermally conductive adhesive, and then a Bonder machine is used to bond a metal wire 3 with a bonding terminal (pin) corresponding to the chip 2 and the substrate 1, so that the COB package is low in price, small in size and mature in process. Because the chip is directly attached to the substrate in the conventional COB package and the metal wire bonding is adopted, the thickness of the chip and the space position of the metal wire are required to be reserved in the conventional COB package, and the ultra-thinning is difficult to realize.
Disclosure of Invention
Therefore, it is necessary to provide a chip, a substrate, a chip package assembly, a packaging method thereof, and a camera module, in order to solve the problems that the conventional COB package cannot overcome the thickness of the chip itself, needs to reserve a space position for a metal wire, and is difficult to realize ultra-thinning.
A chip, comprising:
the first body comprises a first surface, a second surface and an outer side surface, wherein the first surface and the second surface are opposite, and the outer side surface is used for connecting the first surface and the second surface; and
the first welding terminal is arranged on the outer side surface;
when the chip is packaged on the substrate provided with the open slot, the outer side face of the chip is matched with the inner side face of the substrate, so that the chip is supported on the substrate through the circumferential matched abutting force, and the first welding terminal is mutually abutted and electrically connected with the second welding terminal arranged on the inner side face of the open slot.
When the chip is packaged with the corresponding substrate, the step of bonding a gold thread between the first welding terminal of the chip and the second welding terminal of the substrate can be omitted, the space of the chip packaging assembly is prevented from being occupied by the arc-shaped gold thread, so that the safe interval for avoiding the gold thread is not required to be reserved when other elements are assembled on the substrate, and the miniaturized electronic equipment is favorably obtained. And the chip and the substrate are supported on the substrate through the mutually matched abutting force in the circumferential direction, and the chip is supported on the substrate relative to a supporting layer (for example, an open slot for accommodating the chip is a structure with an open end and a closed end, and the closed end is the supporting layer) which is reserved on the substrate and used for bearing the chip, so that a chip packaging assembly with smaller thickness can be obtained more favorably.
In one embodiment, the number of the outer side surfaces is multiple, the outer side surfaces are connected end to end and surround a circle, the outer side surface provided with the first welding terminal is a functional outer side surface, and the functional outer side surface is an inclined surface. The function lateral surface of inclined plane form has the guide effect for the function lateral surface of vertical form, more does benefit to equipment chip and base plate, and more does benefit to chip and base plate electric conductance and makes the chip support on the base plate, but also can increase the area that sets up the lateral surface of first welding terminal.
In one embodiment, the first surface and the second surface are polygons with the same shape, and a plurality of side lines of the first surface correspond to a plurality of side lines of the second surface respectively, and the length of an intersection line of the functional outer side surface and the first surface is greater than the length of an intersection line of the functional outer side surface and the second surface; the included angle between the functional outer side face and the first surface is a first included angle which is larger than or equal to 45 degrees and smaller than 90 degrees. Therefore, the chip and the substrate are more conductive, the chip is supported on the substrate, and the second surface is ensured to have a proper area.
In one embodiment, the first surface and the second surface are polygons with the same shape, and a plurality of side lines of the first surface correspond to a plurality of side lines of the second surface respectively, and the length of an intersection line of the functional outer side surface and the first surface is greater than the length of an intersection line of the functional outer side surface and the second surface; the chip is a photosensitive chip, and the first surface is a photosensitive surface of the chip. Therefore, the photosensitive surface with a larger area is convenient to obtain.
In one embodiment, the first surface and the second surface are polygons with the same shape, and a plurality of side lines of the first surface correspond to a plurality of side lines of the second surface respectively, and the length of an intersection line of the functional outer side surface and the first surface is greater than the length of an intersection line of the functional outer side surface and the second surface; the plurality of outer side faces are the functional outer side faces. The plurality of outer side surfaces are all functional outer side surfaces, and the outer side surfaces can be provided with enough outer side surfaces on which the first welding terminals are arranged.
In one embodiment, the first solder terminal is embedded in the first body, and the first solder terminal has a first terminal surface exposed to the outer side surface, the first terminal surface is coplanar with the outer side surface where the first terminal surface is located, and the first terminal surface is used for being abutted and electrically connected with the second solder terminal on the inner side surface of the open slot. Thus, when the first and second solder terminals are abutted, the plurality of outer side surfaces are abutted (fitted to each other) with the plurality of inner side surfaces, respectively. At this time, the contact area between the chip and the substrate is enlarged from the contact area between the first and second solder terminals to the contact area between the plurality of outer surfaces and the plurality of inner surfaces, so that the connection between the chip and the substrate is firmer.
In one embodiment, the chip further includes a solder bump protruding from the first terminal surface, and the solder bump is configured to abut against and electrically connect to a second solder terminal on an inner side surface of the open slot. Therefore, the first welding terminal is more convenient to abut against and electrically connect with the second welding terminal through the welding convex point.
A substrate, comprising:
the second body comprises a third surface and a fourth surface which are opposite, and the fourth surface is provided with an open slot for packaging the chip; and
the second welding terminal is arranged on the inner side surface of the open slot;
when the chip is packaged in the open slot, the outer side surface of the chip is matched with the inner side surface of the substrate, so that the chip is supported on the substrate through the circumferential matched abutting force, and the second welding terminal is abutted and electrically connected with the first welding terminal arranged on the outer side surface of the chip.
When the substrate is packaged with the corresponding chip, the step of bonding a gold thread between the first welding terminal of the chip and the second welding terminal of the substrate can be omitted, the arc-shaped gold thread is prevented from occupying the space of the chip packaging assembly, and therefore when other elements are assembled on the substrate, the safe distance for avoiding the gold thread does not need to be reserved, and the miniaturized electronic equipment is favorably obtained. And the chip and the substrate are supported on the substrate through the mutually matched abutting force in the circumferential direction, and the chip is supported on the substrate relative to a supporting layer (for example, an open slot for accommodating the chip is a structure with an open end and a closed end, and the closed end is the supporting layer) which is reserved on the substrate and used for bearing the chip, so that a chip packaging assembly with smaller thickness can be obtained more favorably.
In one embodiment, the open slot is a through hole. At this time, the thickness of the substrate may be equal to that of the chip, so that the thickness of the chip package assembly is determined by the chip having the smaller thickness, and thus the chip package assembly having the smaller thickness may be obtained.
In one embodiment, the open slot is a blind hole, that is, the chip is arranged in the blind hole of the substrate, so that one surface of the chip is supported by the substrate, and the supporting strength can be improved.
In one embodiment, the number of the inner side surfaces is multiple, the inner side surfaces are connected end to end and surround a circle, the inner side surface provided with the second welding terminal is a supporting inner side surface, and the supporting inner side surface is an inclined surface. The support medial surface of inclined plane form has the guide effect for the support medial surface of vertical form, more does benefit to equipment chip and base plate, and more does benefit to chip and base plate electric conductance and makes the chip support on the base plate, but also can increase the area that sets up the medial surface of second solder terminal.
In one embodiment, in the arrangement direction from the fourth surface to the third surface, the support inner side surface is inclined outward, an included angle between the support inner side surface and the third surface is a second included angle, and the second included angle is greater than or equal to 45 ° and smaller than 90 °.
In one embodiment, each of the plurality of medial surfaces is the support medial surface.
In one embodiment, the second solder terminal is embedded in the second body, and the second solder terminal has a second terminal surface exposed to the inner side surface, the first terminal surface and the outer side surface where the first terminal surface is located are coplanar, and the second terminal surface is used for abutting against and electrically connecting with the first solder terminal arranged on the outer side surface of the chip.
A chip package assembly comprising:
the above chip; and
the above substrate;
the chip is packaged in the open slot, the outer side face of the chip is matched with the inner side face of the substrate, the chip is supported on the substrate through the circumferential matched abutting force, the second welding terminal is abutted to the first welding terminal on the outer side face of the chip and electrically connected with the first welding terminal, the first surface is located on the same side as the fourth surface, and the second surface is located on the same side as the third surface.
In one embodiment, the semiconductor package assembly further includes an insulating sealant disposed at a peripheral edge of at least one of the first surface and the second surface of the first body, so that the peripheral edge of the at least one of the first surface and the second surface is sealed with the open end of the open slot, and the chip is bonded and fixed to the substrate.
In one embodiment, the first surface and the second surface of the chip are both located in the open slot.
A packaging method of a chip packaging assembly comprises the following steps:
providing the chip and the substrate;
inserting the chip to a preset position of the open slot so that the first welding terminal and the second welding terminal are mutually abutted and electrically connected; and
and maintaining the chip at the preset position for a preset period of time under the action of external force and heating, so that the chip is stably maintained at the preset position after the external force and the heating are removed.
In one embodiment, in the step of maintaining the chip at the preset position for a predetermined time, the preset position is maintained for the predetermined time under the action of an external force, heating and ultrasonic vibration, at least one of the external force and the heating is performed simultaneously with the ultrasonic vibration, so that the chip is stably maintained at the preset position after the external force, the heating and the ultrasonic vibration are removed.
In one embodiment, after the external force and the heating are removed, the peripheral edge of the chip and the opening end of the open slot are sealed by using an insulating sealant, so that the chip and the substrate are bonded and fixed.
In order to show the application effect of the chip, the substrate, the chip packaging assembly and the packaging method thereof, the invention also provides a camera module.
A camera module, comprising:
in the above chip package assembly, the chip is a photosensitive chip, and the first surface is a photosensitive surface of the photosensitive chip;
the bracket is arranged on the fourth surface of the substrate, the bracket is of a hollow structure with two open ends, and the chip is positioned in the bracket; and
the lens assembly is arranged at one end, far away from the substrate, of the support.
Drawings
Fig. 1 is a schematic structural view of a COB packaged chip package assembly;
fig. 2 is a schematic structural diagram of a semiconductor package assembly according to an embodiment of the invention;
FIG. 3 is a schematic cross-sectional view of the semiconductor package assembly of FIG. 2 along line A-A;
fig. 4 is a partial enlarged view of the chip package assembly of fig. 3 at B;
FIG. 5 is a schematic diagram of a chip of the chip package assembly shown in FIG. 2;
fig. 6 is a schematic view of a substrate of the semiconductor package assembly shown in fig. 2;
fig. 7 is a flowchart of a method for packaging a semiconductor package according to an embodiment of the present invention;
fig. 8 is a schematic cross-sectional view of a camera module according to an embodiment of the invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 2 to 4, a chip package assembly 10 according to an embodiment of the invention includes a chip 100 and a substrate 200, wherein a first bonding terminal 120 of the chip 100 is located on an outer side 116 of the chip 100, the substrate 200 is provided with an open slot 230 for accommodating the chip 100, and a second bonding terminal 220 of the substrate 200 is located on an inner side 232 of the open slot 230. When the chip 100 is packaged in the open slot 230, the outer side surface 116 of the chip 100 and the inner side surface 232 of the open slot 230 are mutually matched, the chip 100 is supported on the substrate 200 by the mutually matched abutting force in the circumferential direction, and the first welding terminal 120 and the second welding terminal 220 are mutually abutted and electrically connected, so that the chip 100 and the substrate 200 are electrically conducted.
Compared with the traditional chip packaging assembly, the chip packaging assembly 10 omits the step of gold thread bonding between the first welding terminal 120 of the chip 100 and the second welding terminal 220 of the substrate 200, and can avoid the arc-shaped gold thread from occupying the space of the chip packaging assembly 10, so that when other elements are assembled on the substrate 200, the safe distance for avoiding the gold thread does not need to be reserved, and the miniaturized electronic equipment is favorably obtained.
Moreover, the chip 100 and the substrate 200 are supported on the substrate 200 by the mutually-matched abutting force in the circumferential direction, and the chip 100 is supported on the substrate 200 by a supporting layer (for example, an open slot for accommodating the chip is a structure with an open end and a closed end, i.e., the supporting layer) reserved on the substrate 200 for bearing the chip 100, which is more beneficial to obtaining the chip package assembly 10 with a smaller thickness.
For example, when a supporting layer for supporting the chip 100 is reserved on the substrate 200, if the chip 100 is required to be completely accommodated in the substrate 200, the thickness of the substrate 200 needs to be greater than that of the chip 100, and the chip 100 is supported on the substrate 200 by the abutting force in the circumferential direction, and if the chip 100 is required to be completely accommodated in the substrate 200, the open slot 230 may be a structure with two open ends (in this case, the open slot 230 is a through hole), and the thickness of the substrate 200 may be equal to that of the chip 100, so that the thickness of the chip package assembly 10 is determined by the chip 100 with smaller thickness, and the chip package assembly 10 with smaller thickness may be obtained. Meanwhile, according to the actual application requirement of the product, the open slot 230 may also be a structure with one open end and one closed end (at this time, the open slot 230 is a blind hole), so that the closed end of the open slot 230 may be used as a supporting layer structure to improve the supporting strength and reliability.
As shown in fig. 3 and 4, the chip 100 includes a first body 110 and a first bonding terminal 120. The first body 110 includes a first surface 112 and a second surface 114 opposite to each other, and an outer side 116 connecting the first surface 112 and the second surface 114. The first solder terminal 120 is disposed on the outer side surface 116. The substrate 200 includes a second body 210 and a second solder terminal 220. The second body 210 includes a third surface 212 and a fourth surface 214 opposite to each other, and the fourth surface 214 defines an opening groove 230 for packaging the chip 100. The second welding terminal 220 is provided on an inner side surface 232 of the open groove 230.
In some embodiments, the shape of the outer side 116 of the chip 100 matches the shape of the inner side 232 of the substrate 200 to achieve the mutual fit, reliable support and connection of the chip 100 and the substrate 200.
In some embodiments, the chip 100 may be a cylinder structure with a small height, and the outer side 116 is a curved surface surrounding the first body 110. Accordingly, the inner side surface 232 of the open groove 230 is a curved surface surrounding the first body 110 for one circle.
In some embodiments, as shown in fig. 5, the first surface 112 and the second surface 114 are polygons with the same shape, and a plurality of edges of the first surface 112 correspond to a plurality of edges of the second surface 114, respectively. In the embodiment shown in fig. 5, the first surface 112 and the second surface 114 are both square, and four edges of the first surface 112 correspond to four edges of the second surface 114 in parallel.
The number of the outer side surfaces 116 is multiple (the number of the outer side surfaces 116 is the same as the number of the sides of the polygon), and the multiple outer side surfaces 116 are connected end to surround the first body 110 for a circle. Accordingly, as shown in fig. 6, the number of the inner side surfaces 232 is plural, and the plural inner side surfaces 232 are connected end to end around the first body 110.
Referring to fig. 5 and 6 together, the outer side surface 116 on which the first weld terminal 120 is provided is a functional outer side surface 116a, and the inner side surface 232 on which the second weld terminal 220 is provided is a supporting inner side surface 232 a.
In some embodiments, as shown in fig. 5, the plurality of outer side surfaces 116 are all functional outer side surfaces 116a, that is, the number of the first welding terminals 120 is greater than or equal to the number of the outer side surfaces 116. In the embodiment shown in fig. 5, the number of the outer side surfaces 116 is four, and four first welding terminals 120 are disposed on each of the four outer side surfaces 116, that is, each of the four outer side surfaces 116 is a functional outer side surface 116a, and the number of the first welding terminals 120 is sixteen. The plurality of outer side surfaces 116 are all functional outer side surfaces 116a, and there may be enough outer side surfaces 116 on which the first solder terminals 120 are provided.
In a miniaturized electronic device such as a camera module of a mobile phone, the thickness of the first body 110 is usually very small, when the outer side surface 116 is a vertical surface, the length of the first welding terminals 120 arranged on the outer side surface 116 and extending in the vertical direction is very small, and at this time, it can be considered that the first welding terminals 120 extend in the horizontal direction, so that the first welding terminals 120 have a long length on the premise of not changing the width, but the number of the first welding terminals 120 on the single outer side surface 116 is reduced. The plurality of outer side surfaces 116 are all functional outer side surfaces 116a, so that the total number of the first welding terminals 120 is not reduced.
Accordingly, as shown in fig. 6, in some embodiments, each of the plurality of medial surfaces 232 is a support medial surface 232 a. In this manner, it is possible to have enough inner side surfaces 232 on which the second solder terminals 220 are provided.
In some embodiments, as shown in fig. 5, the functional outer side 116a is beveled. The inclined functional outer side 116a has a guiding function relative to the vertical functional outer side, which is more favorable for assembling the chip 100 and the substrate 200, and is more favorable for electrically connecting the chip 100 and the substrate 200 and supporting the chip 100 on the substrate 200, and the area of the outer side 116 on which the first bonding terminal 120 is disposed can be increased. Accordingly, as shown in fig. 6, in some embodiments, the support medial surface 232a is beveled.
In some embodiments, as shown in fig. 5, the length of the intersection line of the functional outer side 116a and the first surface 112 is greater than the length of the intersection line of the functional outer side 116a and the second surface 114, that is, the size of the end of the first body 110 located at the first surface 112 is greater than the size of the end of the first body 110 located at the second surface 114. In some embodiments, the chip 110 is a photosensitive chip of the camera module, and the first surface 112 is a photosensitive surface of the photosensitive chip. Therefore, the photosensitive surface with a larger area is convenient to obtain.
In some embodiments, as shown in fig. 4, the included angle between the functional outer side surface 116a and the first surface 112 is a first included angle α, and the first included angle α is greater than or equal to 45 ° and smaller than 90 °. Thus, the chip 100 and the substrate 200 are more easily electrically connected, the chip 100 is supported on the substrate 200, and the second surface 114 has a suitable area.
Accordingly, as shown in fig. 4, in the arrangement direction of the fourth surface 214 to the third surface 212, the support inner side surface 232a is inclined toward the outer side. In some embodiments, the fourth surface 214 is used to carry a bracket for a camera module.
In some embodiments, the angle between the support inner side surface 232a and the third surface 212 is a second included angle β, and the second included angle β is greater than or equal to 45 ° and smaller than 90 °. In some embodiments, the first included angle α is equal to the second included angle β, i.e., the functional outer side 116a is parallel to the support inner side 232 a. In some embodiments, first included angle α and second included angle β are both 45 °.
When assembling the semiconductor package assembly 10, the chip 100 shown in fig. 5 is rotated 180 ° first, so that the second surface 114 of the first body 110 of the chip 100 faces the substrate 200 shown in fig. 6, at this time, in the arrangement direction from the fourth surface 214 to the third surface 212, the functional outer side surface 116a and the supporting inner side surface 232a are both inclined outward, and then the chip 100 is inserted into the opening groove 230 of the substrate 200, so that the first soldering terminal 120 abuts against and is electrically connected to the second soldering terminal 220.
In some embodiments, as shown in fig. 5, when the plurality of outer side surfaces 116 are all the functional outer side surfaces 116a, the plurality of functional outer side surfaces 116a are all inclined surfaces, and the plurality of functional outer side surfaces 116a are all inclined toward the inside in the direction from the second surface 114 to the first surface 112 (after the chip 100 shown in fig. 5 is rotated by 180 °, that is, in the direction from the first surface 112 to the second surface 114, the plurality of functional outer side surfaces 116a are all inclined toward the outside), and the inclination angles are all the same, that is, the included angles between the plurality of functional outer side surfaces 116a and the first surface 112 are all the first included angle α.
Accordingly, as shown in fig. 6, when the plurality of inner side surfaces 232 are supporting inner side surfaces 232a, the plurality of supporting inner side surfaces 232a are inclined surfaces, each inclined toward the outer side in the arrangement direction from the fourth surface 214 to the third surface 212, so that when the open groove 230 is a through hole, that is, when the open groove 230 penetrates through the third surface 212 and the fourth surface 214, the open groove 230 includes a first opening 2122 located on the third surface 212 and a second opening 2142 located on the fourth surface 214, and the size of the second opening 2142 is greater than the size of the first opening 2122. In some embodiments, the open slot 230 may not extend through the third surface 212, in which case the open slot 230 is a blind hole.
In some embodiments, when some of the plurality of outer sides 116 are functional outer sides 116a and the remaining ones are non-functional outer sides, the non-functional outer sides may be inclined planes or vertical planes. Accordingly, some of the inner side surfaces 232 are supporting inner side surfaces 232a, and the remaining inner side surfaces are non-supporting inner side surfaces, which may be inclined surfaces or vertical surfaces. When the first and second weld terminals 120 and 220 are abutted, the non-functional outer side surface is abutted against the corresponding non-supporting inner side surface. In this way, the contact area between the chip 100 and the substrate 200 is increased from the contact area between the first solder terminal 120 and the second solder terminal 220 to the contact area between the non-functional outer side surface and the corresponding non-supporting inner side surface, so that the connection between the chip 100 and the substrate 200 is more secure.
In some embodiments, as shown in fig. 5, the first welding terminal 120 has a first terminal face 122 exposed to the outer side face 116, and the first terminal face 122 is used for abutting and electrically connecting with the second welding terminal 220 on the inner side face 232 of the open slot 230. In some embodiments, the first solder terminal 120 is embedded in the first body 110, and the first terminal surface 122 is coplanar with the outer side surface 116 on which the first solder terminal is located, that is, the first terminal surface 122 is flush with the outer side surface 116 on which the first solder terminal is located, and the first terminal surface 122 can be regarded as a part of the outer side surface 116 as a whole. When the outer side surface 116 is an arc surface, the first terminal surface 122 is an arc surface. When the outer side surface 116 is plural, the first terminal surface 122 is flush with the outer side surface 116 on which it is located.
Accordingly, as shown in fig. 6, the second solder terminal 220 has a second terminal surface 222 exposed on the inner side surface 232, and the second terminal surface 222 is used for the first solder terminal 120 on the outer side surface 116 to abut and electrically connect. In some embodiments, the second welding terminal 220 is embedded in the second body 210, and the second terminal surface 222 is coplanar with the inner side surface 232 where the second terminal surface is located, that is, the second terminal surface 222 is flush with the inner side surface 232 where the second terminal surface is located, and the second terminal surface 222 can be regarded as a part of the inner side surface 232 when viewed as a whole. When the inner side surface 232 is an arc surface, the second terminal surface 222 is an arc surface. And when there are a plurality of inner side surfaces 232, the second terminal surface 222 is flush with the inner side surface 232 on which it is located.
In this way, when the first solder terminal 120 abuts against the second solder terminal 220, the outer side surfaces 116 abut against the inner side surfaces 232, respectively. At this time, the contact area between the chip 100 and the substrate 200 is increased from the contact area between the first solder terminal 120 and the second solder terminal 220 to the contact area between the outer surfaces 116 and the inner surfaces 232, so that the connection between the chip 100 and the substrate 200 is more secure.
In some embodiments, as shown in fig. 5, the chip 100 further includes a solder bump 130 protruding from the first terminal surface 122, and the solder bump 130 is configured to abut and electrically connect with the second solder terminal 220. In this way, the first solder terminal 120 is more easily abutted against and electrically connected to the second solder terminal 220 via the solder bump 130.
In some embodiments, as shown in fig. 4, the chip package assembly 10 further includes an insulating sealant 300, wherein the insulating sealant 300 is disposed at a peripheral edge of at least one of the first surface 112 and the second surface 114 of the chip 100, so that the peripheral edge of at least one of the first surface 112 and the second surface 114 is sealed with the open end of the open slot 230 of the substrate 100. When the two ends of the open slot 230 are open (at this time, the open slot 230 is a through hole), the peripheral edges of the first surface 112 and the second surface 114 are both provided with the insulating sealant 300, and when one end of the open slot 230 is open (at this time, the open slot 230 is a blind hole), the peripheral edges of the first surface 112 or the second surface 114 may only be provided with the insulating sealant 300. The insulating sealant 300 can make the connection between the chip 100 and the substrate 200 more secure, and can prevent moisture and dust from entering between the inner side 232 of the open slot 230 and the outer side 116 of the chip 100.
In some embodiments, as shown in fig. 3 and 4, the first surface 112 and the second surface 114 of the chip 100 are both located in the open slot 230. Thus, the chip 100 can be prevented from protruding from the third surface 212 or the fourth surface 214, which results in an increase in the thickness of the semiconductor package 10.
In some embodiments, the first surface 112 is offset from the fourth surface 214, i.e., the height of the first surface 112 is less than the height of the fourth surface 214. Therefore, the insulating sealant 300 can be located in the opening groove 230, and the insulating sealant 300 can connect the first surface 112 and the inner side surface 232, so that the insulating sealant 300 can be prevented from protruding from the fourth surface 214, and the fourth surface 214 is not flat, which is not beneficial to bearing elements such as a bracket of a camera module. In some embodiments, when the opening groove 230 is open at both ends, the first surface 112 and the fourth surface 214 have a tolerance, and the second surface 114 and the third surface 212 also have a tolerance.
In some embodiments, the first surface 112 is flush with the fourth surface 214. In this manner, the substrate 200 having a smaller thickness can be used, which is more advantageous in obtaining the chip package assembly 10 having a smaller thickness. In some embodiments, when the open slot 230 is open at both ends, the first surface 112 is flush with the fourth surface 214, and the second surface 114 is also flush with the third surface 212. At this time, the thickness of the substrate 200 may be equal to the thickness of the chip 100, so that the thickness of the semiconductor package 10 is determined by the chip 100 with a smaller thickness, and the semiconductor package 10 with a smaller thickness may be obtained.
As shown in fig. 7, a method for packaging a semiconductor package according to an embodiment of the present invention includes the following steps:
in step S410, the chip and the substrate are provided.
Step S420, inserting the chip into a predetermined position of the opening slot, so that the chip and the substrate are supported on the substrate by the mutually matched abutting force in the circumferential direction, and the first and second soldering terminals are mutually abutted and electrically connected.
In some embodiments, the first and second solder terminals have the same shape and size, and the predetermined position is a position where the first and second solder terminals completely overlap.
Step S430, maintaining the chip at the predetermined position for a predetermined time under the action of the external force and the heating, so that the chip is stably maintained at the predetermined position after the external force and the heating are removed. External force can increase the squeezing action between first welding terminal and the second welding terminal to make the butt of first welding terminal and second welding terminal and electricity connect more firmly, after removing external force, stably maintain predetermineeing the position. The heating may facilitate diffusion bonding of the first and second solder terminals, thereby facilitating connection stability between the first and second solder terminals.
In some embodiments, after the chip is inserted into the predetermined position of the open slot, the whole of the chip and the substrate is heated while applying the external force for the predetermined time. Therefore, the connection stability between the first welding terminal and the second welding terminal is better facilitated. In some embodiments, after the chip is inserted into the predetermined position of the open slot, the predetermined position is maintained under the action of the external force in a first time period, and after the external force is removed, the whole body formed by the chip and the substrate is heated in a second time period, and the sum of the first time period and the second time period is the predetermined time. In some embodiments, after the chip is inserted into the predetermined position of the open slot, the whole body formed by the chip and the substrate is heated in a first time period, and after the heating is stopped, the predetermined position is maintained under the action of an external force in a second time period, and the sum of the first time period and the second time period is the predetermined time.
Taking the view shown in fig. 3 as an example, the external force may be a vertical external force acting on the middle portion of the first surface 112. The magnitude of the external force may be determined empirically or by specific experimentation. For example, in a specific experiment, in step S420, an external force may be applied to the chip, and the external force is gradually increased at intervals, where the external force that enables the chip to reach the preset position is a first critical external force; then, the external force is increased at intervals, wherein the external force which can change the position of the chip relative to the position of the substrate is close to the second critical external force; so that the external force in step S430 may be an external force greater than or equal to the first critical external force and less than the second critical external force.
The magnitude of the temperature may be determined empirically or by specific experimentation. For example, in a specific experiment, a plurality of blocks (a block formed by a chip and a substrate after the chip is inserted into a predetermined position of an open groove) are heated for the same time (the block is directly heated first, and the block does not pass through the step of "maintaining the predetermined position under the action of external force"), and the heating temperatures of the plurality of blocks are different and gradually increase. And then sequentially carrying out drop tests on the plurality of the whole bodies (for example, sequentially carrying out the drop tests on the plurality of the whole bodies from the position with the height of 2 meters), wherein the temperature which does not change at the preset position is the critical temperature after the drop tests. The temperature in step S430 may be a temperature greater than the critical temperature and less than a safety temperature, where the safety temperature is a temperature that does not cause the chip and the substrate to deform under the action of an external force (the external force in step S430).
The predetermined time period may be determined empirically or by specific experimentation. For example, in a specific experiment, step 1, only external force is applied without heating; specifically, the external force action time of the plurality of integrated bodies (the integrated body of the chip and the substrate after the chip is inserted to the preset position of the open groove) is different and gradually increased. And then sequentially carrying out a drop test on the plurality of the whole bodies (for example, sequentially carrying out the drop test on the plurality of the whole bodies from the position with the height of 2 meters), wherein after the drop test, the time when the preset position is not changed is the external force maintaining time. Step 2, only heating and not applying external force; specifically, the heating time of the plurality of integrated bodies (the integrated body of the chip and the substrate after the chip is inserted to the preset position of the open groove) is different and gradually increased. And then sequentially carrying out drop tests on the plurality of the whole bodies (for example, sequentially carrying out the drop tests on the plurality of the whole bodies from the position with the height of 2 meters), wherein the time when the preset position is not changed is the temperature maintaining time after the drop tests. When the external force and the heating are performed simultaneously, a predetermined time in the step S430 is greater than or equal to the larger of the external force maintaining time and the temperature maintaining time; when the external force and the heating are sequentially performed, a predetermined time in step S430 is equal to the sum of the external force maintaining time and the temperature maintaining time.
In some embodiments, step S430 further includes performing an ultrasonic vibration step on the chip and the substrate in the predetermined position, wherein at least one of the external force and the heating is performed simultaneously with the ultrasonic vibration, so as to stably maintain the predetermined position after the external force, the heating and the ultrasonic vibration are removed. Wherein, ultrasonic vibration can increase the squeezing action between first welded terminal and the second welded terminal to can make the butt of first welded terminal and second welded terminal and electricity connect more firmly, after removing external force, stably maintain preset position.
In some embodiments, the external force, the heating and the ultrasonic vibration are performed simultaneously.
Step S440, after the external force and the heating are removed, the peripheral edge of the chip and the opening end of the open slot are sealed by adopting an insulating sealant.
Step S450, a signal conduction test is performed to determine whether the first welding terminal and the second welding terminal are normally electrically connected.
In step S460, an appearance check is performed to determine whether the appearance of the chip package assembly is complete.
As shown in fig. 8, in order to make the description of a chip, a substrate, a package assembly of the chip, and a packaging method thereof more clear and facilitate understanding of the application of the invention, the invention also provides a camera module 80. It should be noted that the camera module 80 is a typical application of the chip, the substrate, the chip package assembly and the packaging method thereof, and the invention can also be applied to other specific products, such as LED chip package, mobile phone chip package, etc. Therefore, the camera module in the present application is not to be understood as the limitation of the present invention to the chip, the substrate, the chip package assembly and the packaging method thereof.
The camera module 80 according to an embodiment of the present invention includes the above-mentioned chip package assembly 10, and the support 20, the filter 30, and the lens assembly 40. The chip 100 is a photosensitive chip, and the first surface 112 of the chip 100 is a photosensitive surface. The first surface 112 and the second surface 114 of the chip 100 correspond to the fourth surface 214 and the third surface 212 of the substrate 200, respectively, that is, the first surface 112 and the fourth surface 214 are located on the same side, and the second surface 114 and the third surface 212 are located on the same side. The support 20 is disposed on the fourth surface 214 of the substrate 200. The support 20 is a hollow structure with two open ends, and the chip 100 is located in the support 20. The filter 30 is disposed in the holder 20. The lens assembly 40 is disposed on an end of the frame 20 remote from the substrate 200.
In another embodiment of the present application, the camera module may further include one or more of an adapter circuit board, a copper foil, a metal shielding cover plate, and other accessory components. Since these accessory components are common technology in the field of camera modules, the drawings of the present invention are not shown in detail.
The camera module 80 can be applied to mobile terminals such as mobile phones and tablet computers.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (15)

1. A chip, comprising:
the first body comprises a first surface, a second surface and an outer side surface, wherein the first surface and the second surface are opposite, and the outer side surface is used for connecting the first surface and the second surface; and
the first welding terminal is arranged on the outer side surface;
when the chip is packaged on the substrate provided with the open slot, the outer side face of the chip is matched with the inner side face of the substrate, so that the chip is supported on the substrate through the circumferential matched abutting force, and the first welding terminal is mutually abutted and electrically connected with the second welding terminal arranged on the inner side face of the open slot.
2. The chip according to claim 1, wherein the number of the outer side surfaces is plural, and the plural outer side surfaces are connected end to surround one circle, wherein the outer side surface on which the first bonding terminal is provided is a functional outer side surface, and the functional outer side surface is an inclined surface.
3. The chip of claim 2, wherein the first surface and the second surface are polygons with the same shape, and a plurality of edges of the first surface correspond to a plurality of edges of the second surface, respectively, and a length of an intersection line of the functional outer side surface and the first surface is greater than a length of an intersection line of the functional outer side surface and the second surface;
the included angle between the functional outer side face and the first surface is a first included angle which is more than or equal to 45 degrees and less than 90 degrees; and/or
The chip is a photosensitive chip, and the first surface is a photosensitive surface of the chip; and/or
The plurality of outer side faces are the functional outer side faces.
4. The chip of any one of claims 1 to 3, wherein the first solder terminal is embedded in the first body and has a first terminal face exposed to the outer side face, the first terminal face being coplanar with the outer side face on which it is located, the first terminal face being configured to abut and electrically connect with a second solder terminal on an inner side face of the open slot.
5. The chip of claim 4, further comprising a solder bump protruding from the first terminal surface, the solder bump being adapted to abut and electrically connect to a second solder terminal on an inner side of the open slot.
6. A substrate, comprising:
the second body comprises a third surface and a fourth surface which are opposite, and the fourth surface is provided with an open slot for packaging the chip; and
the second welding terminal is arranged on the inner side surface of the open slot;
when the chip is packaged in the open slot, the outer side surface of the chip is matched with the inner side surface of the substrate, so that the chip is supported on the substrate through the circumferential matched abutting force, and the second welding terminal is abutted and electrically connected with the first welding terminal arranged on the outer side surface of the chip.
7. The substrate according to claim 6, wherein the open groove is a through hole;
or the open slot is a blind hole.
8. The substrate according to claim 6, wherein the number of the inner side surfaces is plural, and the plural inner side surfaces are connected end to end and surround one circle, wherein the inner side surface on which the second solder terminal is provided is a support inner side surface, and the support inner side surface is an inclined surface.
9. The substrate according to claim 8, wherein in the arrangement direction from the fourth surface to the third surface, the support inner side surface is inclined outward, and an angle between the support inner side surface and the third surface is a second angle which is greater than or equal to 45 ° and smaller than 90 °; and/or
A plurality of said medial surfaces are said support medial surfaces; and/or
The second welding terminal is embedded in the second body, the second welding terminal is provided with a second terminal surface exposed out of the inner side surface, the first terminal surface and the outer side surface at the position of the first terminal surface are coplanar, and the second terminal surface is used for being abutted and electrically connected with the first welding terminal arranged on the outer side surface of the chip.
10. A chip package assembly, comprising:
the chip of any one of claims 1-5; and
the substrate of any one of claims 6-9;
the chip is packaged in the open slot, the outer side face of the chip is matched with the inner side face of the substrate, the chip is supported on the substrate through the circumferential matched abutting force, the second welding terminal is abutted to the first welding terminal on the outer side face of the chip and electrically connected with the first welding terminal, the first surface is located on the same side as the fourth surface, and the second surface is located on the same side as the third surface.
11. The semiconductor package assembly as claimed in claim 10, further comprising an insulating sealant disposed at a peripheral edge of at least one of the first surface and the second surface of the first body, so that the peripheral edge of at least one of the first surface and the second surface is sealed with the open end of the open slot, thereby adhering and fixing the semiconductor package to the substrate; and/or
The first surface and the second surface of the chip are both positioned in the open slot.
12. A method for packaging a chip package assembly comprises the following steps:
providing a chip according to any one of claims 1 to 5 and a substrate according to any one of claims 6 to 9;
inserting the chip to a preset position of the open slot so that the first welding terminal and the second welding terminal are mutually abutted and electrically connected; and
and maintaining the chip at the preset position for a preset time under the action of external force and heating, so that the chip is stably maintained at the preset position after the external force and the heating are removed.
13. The method of claim 12, wherein the predetermined position is maintained for a predetermined time by an external force, a heating and an ultrasonic vibration in the step of maintaining the chip at the predetermined position for a predetermined time, at least one of the external force and the heating being performed simultaneously with the ultrasonic vibration, so that the chip is stably maintained at the predetermined position after the external force, the heating and the ultrasonic vibration are removed.
14. The method of claim 12 or 13, wherein after the external force and the heating are removed, the peripheral edge of the chip and the open end of the open slot are sealed by an insulating sealant, so that the chip and the substrate are bonded and fixed.
15. The utility model provides a module of making a video recording which characterized in that includes:
the chip package assembly of claim 10 or 11, wherein the chip is a photosensitive chip, and the first surface is a photosensitive surface of the photosensitive chip;
the bracket is arranged on the fourth surface of the substrate, the bracket is of a hollow structure with two open ends, and the chip is positioned in the bracket; and
the lens assembly is arranged at one end, far away from the substrate, of the support.
CN201910492134.2A 2019-06-06 2019-06-06 Chip, substrate, chip packaging assembly, packaging method of chip packaging assembly and camera module Withdrawn CN112054004A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910492134.2A CN112054004A (en) 2019-06-06 2019-06-06 Chip, substrate, chip packaging assembly, packaging method of chip packaging assembly and camera module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910492134.2A CN112054004A (en) 2019-06-06 2019-06-06 Chip, substrate, chip packaging assembly, packaging method of chip packaging assembly and camera module

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112897451A (en) * 2021-01-19 2021-06-04 潍坊歌尔微电子有限公司 Sensor packaging structure, manufacturing method thereof and electronic equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112897451A (en) * 2021-01-19 2021-06-04 潍坊歌尔微电子有限公司 Sensor packaging structure, manufacturing method thereof and electronic equipment
CN112897451B (en) * 2021-01-19 2023-12-22 潍坊歌尔微电子有限公司 Sensor packaging structure, manufacturing method thereof and electronic equipment

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