CN112052637A - BSIMMG-based FDSOI MOSFET model generation method and device - Google Patents

BSIMMG-based FDSOI MOSFET model generation method and device Download PDF

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CN112052637A
CN112052637A CN202010892877.1A CN202010892877A CN112052637A CN 112052637 A CN112052637 A CN 112052637A CN 202010892877 A CN202010892877 A CN 202010892877A CN 112052637 A CN112052637 A CN 112052637A
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model
channel device
bsimg
bsimimg
device model
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卜建辉
王可为
李多力
李博
李彬鸿
刘海南
罗家俊
韩郑生
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
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Abstract

The invention discloses a method and a device for generating an FDSOI MOSFET model based on BSIMIMG, which are applied to the field of integrated circuit design and comprise the following steps: the BSIMIMG back channel device model is combined to the BSIMG front channel device model in a controlled source mode; the BSIMIMG front channel device model is generated based on a new BSIMIMG standard model and front channel device model parameters extracted from the FDSOI MOSFET device, the BSIMG back channel device model is generated based on the new BSIMG standard model and back channel device model parameters extracted from the FDSOI MOSFET device, and the new BSIMG standard model is obtained by modifying Verilog-a codes of the BSIMG standard model. The invention improves the model precision of the device under the condition of opening the back channel.

Description

BSIMMG-based FDSOI MOSFET model generation method and device
Technical Field
The invention relates to the field of integrated circuit design, in particular to a method and a device for generating an FDSOI MOSFET model based on BSIMIMG.
Background
With the development and the more extensive application of integrated circuit technology, the requirements of high reliability, high performance and low cost of the integrated circuit must be considered during the design of the integrated circuit, and the requirements of people on the functions and the precision of the statistical tolerance analysis, the optimal design, the yield, the cost analysis and the reliability prediction of the IC CAD software are higher and higher. In the IC CAD software, a device model of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a key link that relates IC design and IC product functions and performance. Along with the size of an integrated device is smaller and smaller, the integrated scale is larger and larger, the working procedure of an integrated circuit is more and more complex, and the requirement on the precision of a device model is higher and higher. Today, an accurate MOSFET model is undoubtedly the problem that the IC CAD designer has solved first, and has been the focus and hot spot of international research.
Currently, the FDSOI MOSFET model established in the industry will have a drastically degraded accuracy when the back gate bias is large enough to turn on the back channel.
Disclosure of Invention
In view of the above technical problems in the prior art, embodiments of the present invention provide a method and an apparatus for generating an FDSOI MOSFET model based on bsiimg.
In a first aspect, an embodiment of the present invention provides a method for generating an FDSOI MOSFET model based on bsimm, including:
modifying the Verilog-a code of the BSIMG standard model to obtain a new BSIMG standard model;
extracting a front channel device model parameter and a back channel device model parameter from the FDSOI MOSFET device;
generating a BSIMIMG positive channel device model based on the positive channel device model parameters and the new BSIMG standard model, and generating a BSIMG back channel device model based on the back channel device model parameters and the new BSIMG standard model;
combining the BSIMIMG back channel device model to the BSIMG front channel device model in a controlled source mode to obtain a synthetic model;
and adjusting the model parameters of the synthetic model to obtain a target FDSOI MOSFET model.
Optionally, the extracting the model parameters of the front channel device and the model parameters of the back channel device of the FDSOI MOSFET device includes:
extracting a positive channel device model parameter of the FDSOI MOSFET device when a back channel of the FDSOI MOSFET device is in a non-opening state;
and extracting back channel device model parameters of the FDSOI MOSFET device when a front channel of the FDSOI MOSFET device is in a non-opening state.
Optionally, the extracting back channel device model parameters of the FDSOI MOSFET device includes:
extracting the back gate oxide thickness of the FDSOI MOSFET device as the front gate oxide thickness of the BSIMIMG back channel device model, an
Extracting the front gate oxide thickness of the FDSOI MOSFET device as the back gate oxide thickness of the BSIMIMG back channel device model, an
And extracting the back channel current of the FDSOI MOSFET device as the positive channel current of the BSIMIMG back channel device model.
Optionally, the merging the bsimg back channel device model to the bsimg positive channel device model in a controlled source form to obtain a composite model includes:
applying a positive gate voltage to a back gate of the BSIMIMG back channel device model, applying a back gate voltage to a positive gate of the BSIMIMG back channel device model, and applying a drain voltage to a drain of the BSIMIMG back channel device model;
connecting a controlled source in parallel on the BSIMIMG positive channel device model, wherein the controlled source is a voltage control current source or a current control current source;
introducing the back channel current of the BSIMIMG back channel device model to the controlled source to obtain the total current of the synthetic model, which is the sum of the current of the BSIMG back channel device model and the current of the BSIMG positive channel device model.
Optionally, the introducing the back channel current of the bsiimg back channel device model to the controlled source includes:
arranging a first resistor on a drain electrode of the BSIMIMG back channel device model;
introducing a current across the first resistance or a voltage across the first resistance to the controlled source.
Optionally, the modifying Verilog-a code of the bsimm standard model to obtain a new bsimm standard model includes:
modifying the effective back gate voltage in the Verilog-a code as follows: when the back gate voltage is greater than the back channel threshold voltage, the back gate effective voltage is equal to the back channel threshold voltage, and when the back gate voltage is less than the back channel accumulated voltage, the back gate effective voltage is equal to the back channel accumulated voltage.
Optionally, the adjusting model parameters of the synthesis model to obtain a target FDSOI MOSFET model includes:
and adjusting the positive gate threshold voltage and the back gate threshold voltage of the synthetic model.
In a second aspect, an embodiment of the present invention provides an FDSOI MOSFET model generating apparatus based on bsiimg, including:
the code modification unit is used for modifying the Verilog-a code of the BSIMIMG standard model to obtain a new BSIMG standard model;
the model parameter extraction unit is used for extracting a front channel device model parameter and a back channel device model parameter from the FDSOI MOSFET device;
a model generating unit, configured to generate a bsimg positive channel device model based on the positive channel device model parameters and the new bsimg standard model, and generate a bsimg back channel device model based on the back channel device model parameters and the new bsimg standard model;
the model synthesis unit is used for combining the BSIMIMG back channel device model to the BSIMG positive channel device model in a controlled source mode to obtain a synthesis model;
a model parameter adjusting unit for adjusting the model parameters of the synthesis model to obtain a target FDSOI MOSFET model
In a third aspect, an embodiment of the present invention provides an FDSOI MOSFET model based on bsiimg, including: the BSIMIMG device model comprises a BSIMIMG back channel device model and a BSIMIMG front channel device model, wherein the BSIMG back channel device model is combined to the BSIMG front channel device model in a controlled source mode; the BSIMIMG front channel device model is generated based on a new BSIMIMG standard model and front channel device model parameters extracted from an FDSOI MOSFET device, the BSIMG back channel device model is generated based on the new BSIMG standard model and back channel device model parameters extracted from the FDSOI MOSFET device, and the new BSIMG standard model is obtained by modifying Verilog-a codes of the BSIMG standard model.
According to the technical scheme provided by the embodiment of the invention, on the basis of the BSIMIMG standard SOI device model in the industry, the BSIMG back channel device model is merged to the BSIMIMG front channel device model in a controlled source form to obtain the synthetic model, so that the back channel current is introduced into the BSIMG front channel device model in the controlled source form, the verilog code of the BSIMG standard model is modified and the model parameters are adjusted at the same time, the coupling characteristic change of the back gate bias to the front channel when the back channel is started can be responded, and the device model precision under the back channel starting condition is greatly improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for generating a model of an FDSOI MOSFET device based on bsiimg according to an embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram of an FDSOI MOSFET model in an embodiment of the present invention;
fig. 3 is a comparison of simulation and test data for the FDSOI MOSFET model generated in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The embodiments of the present invention and the technical features in the embodiments may be combined with each other without conflict. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative effort belong to the protection scope of the present invention.
In a first aspect, an embodiment of the present invention provides a method for generating an FDSOI MOSFET Model based on bsimm (Berkeley Short-channel IGFET Model IMG, Berkeley IMG Short-channel insulated gate field effect transistor Model). Referring to fig. 1, a generation method provided in an embodiment of the present invention includes the following steps:
and S1, modifying the Verilog-a code of the BSIMIMG standard model to obtain a new BSIMG standard model.
It should be noted that the bsiimmg standard model is an SOI device model that is standard in the industry. And Verilog-a is an industry standard model language for analog circuits, describing the bsigmg standard model. In the embodiment of the present invention, modifying a Verilog-a code of a bsigmg standard model, specifically modifying an effective back gate voltage in the Verilog-a code, includes: when the back gate voltage is greater than the back channel threshold voltage, the back gate effective voltage is equal to the back channel threshold voltage; and when the back gate voltage is less than the back channel accumulated voltage, the back gate effective voltage is equal to the back channel accumulated voltage.
And S2, extracting the forward channel device model parameters and the back channel device model parameters from the FDSOI MOSFET device.
Specifically, a front channel device model parameter of the FDSOI MOSFET device needs to be extracted when a back channel of the FDSOI MOSFET device is in an unopened state; and extracting back channel device model parameters of the FDSOI MOSFET device when the front channel of the FDSOI MOSFET device is in a non-opening state.
Specifically, the specific parameter types for extracting the model parameters of the front channel device and the model parameters of the back channel device are more, so that the prior art can be referred to for specifically extracting which model parameters. In the following, only some important model parameters are listed: a back channel threshold voltage (VTHINV), a back channel accumulation Voltage (VTHACC), a model flag (LEVEL), a well type (WELLType), a top layer silicon film thickness (Tsi), a back gate oxygen thickness (EOT 2); positive gate oxide thickness (EOT1), inversion layer channel doping concentration (Nbody), and the like.
In a specific implementation process, the thickness of the positive gate oxide is extracted to be used as the thickness of the positive gate oxide of a BSIMIMG positive channel device model and used as the thickness of the back gate oxide of a BSIMG back channel device model; and extracting the back gate oxygen thickness as the back gate oxygen thickness of the BSIMIMG positive channel device model and as the positive gate oxygen thickness of the BSIMG back channel device model. Specific values are referenced below:
the values of the model parameters of each positive channel device obtained by extraction are as follows: VTHINV ═ 7; VTHACC ═ 15; LEVEL 78; 102.6, VERSION ═ 102.6; TYPE ═ 1; WELLTYPE ═ 1; EOT1 ═ 4.5E-9; EOT2 ═ 1.45E-7; TSI-5E-8; NBODY ═ 1E 22.
The extracted values of the model parameters of each back channel device are as follows: VTHINV 0.69244; VTHACC ═ 0.6; LEVEL 78; 102.6, VERSION ═ 102.6; TYPE ═ 1; WELLTYPE ═ 1; EOT2 ═ 4.5E-9; EOT1 ═ 1.45E-7; TSI-5E-8; NBODY ═ 1E 22.
S3, generating a BSIMIMG forward channel device model based on the forward channel device model parameters and the new BSIMIMG standard model, and generating a BSIMIMG back channel device model based on the back channel device model parameters and the new BSIMIMG standard model.
Regarding the BSIMIMG positive channel device model, the extracted back gate oxygen thickness of the FDSOI MOSFET device is used as the back gate oxygen thickness of the BSIMG positive channel device model, the extracted front gate oxygen thickness of the FDSOI MOSFET device is used as the front gate oxygen thickness of the BSIMG positive channel device model, and the extracted back channel current of the FDSOI MOSFET device is used as the back channel current of the BSIMG back channel device model.
Regarding the BSIMIMG back channel device model, the extracted back gate oxide thickness of the FDSOI MOSFET device is used as the gate oxide thickness of the BSIMG back channel device model, the extracted gate oxide thickness of the FDSOI MOSFET device is used as the back gate oxide thickness of the BSIMG back channel device model, and the extracted back channel current of the FDSOI MOSFET device is used as the positive channel current of the BSIMG back channel device model.
And S4, merging the BSIMIMG back channel device model into a BSIMG positive channel device model in a controlled source mode to obtain a synthetic model.
Introducing the back channel current of the BSIMIMG back channel device model into the BSIMG positive channel device model in a controlled source mode to obtain a synthetic model.
In step S4, a back gate voltage is applied to the back gate of the bsimg positive channel device model, a positive gate voltage is applied to the positive gate of the bsimg positive channel device model, and a drain voltage is applied to the drain of the bsimg back channel device model. Adding a positive gate voltage to a back gate of the BSIMIMG back channel device model, adding a back gate voltage to a positive gate of the BSIMIMG back channel device model, and adding a drain voltage to a drain of the BSIMG back channel device model; connecting a controlled source in parallel on a BSIMIMG positive channel device model; introducing the back channel current of the BSIMIMG back channel device model to a controlled source, so that the total current of the synthesized model is the sum of the current of the BSIMG back channel device model and the current of the BSIMG positive channel device model.
Reference is now made to the equivalent circuit diagram of the synthesis model shown in FIG. 2, M in FIG. 21For BSIMIMG positive channel device model, M2The BSIMIMG back channel device model. Referring to fig. 2, controlled sources are connected in parallel on a bsimsg front channel device model, that is, controlled sources are connected in parallel between a source and a drain of M1, a front gate voltage is applied to a back gate of the bsimson back channel device model, a back gate voltage is applied to a front gate of the bsimson back channel device model, and a drain voltage is applied to a drain of the bsimson back channel device model. Next, step S4 is performed in conjunction with FIG. 2Detailed description:
to move towards M1Introducing back channel current into the back channel device model M2Is provided with a first resistor R1Specifically, the first resistor R1Is less than a predetermined threshold, such as: a first resistor R1Is 1 ohm, so that R1The voltage and current on are equal.
At M1On parallel current control current source F1First resistance R1Is connected to M1Current-controlled current sources connected in parallel, such that F1＝iR1Or a first resistance R1Is connected to M1Parallel controlled sources (G)1＝VR1) Rather than direct parallel connection between device models. Wherein the controlled source is a voltage-controlled current source G1Or a current-controlled current source F1The M is realized by a first resistor R1 arranged at the drain D of the back channel device model M2 and a voltage-controlled current source G1 (or a current-controlled current source F1) connected in parallel with the positive channel device model M12Is introduced into M1In the method, the total current of the synthetic model simultaneously comprises the current of the positive channel and the current of the back channel so as to change the coupling characteristic of the back gate bias to the positive channel when the back channel is opened, thereby greatly improving the model accuracy under the condition of opening the back channel.
And S5, adjusting model parameters of the synthesis model to obtain the target FDSOI MOSFET model.
Specifically, the adjusted model parameters include: a positive gate threshold voltage and a back gate threshold voltage. After the two models are combined in the form of a controlled source, the back gate threshold voltage and the back gate threshold voltage both change due to the generation of a superposition effect, so that correction needs to be performed by adjusting the positive gate threshold voltage and the back gate threshold voltage, and more accurate positive gate threshold voltage and back gate threshold voltage are obtained for the combined models.
Referring to the comparison between the simulation and the test data of the FDSOI MOSFET device model shown in fig. 3, it can be seen that, under different vbs (substrate bias voltage), the Id-Vg characteristic data (shown as simulation result a) obtained by the simulation of the FDSOI MOSFET device model obtained by the embodiment of the present invention is close to the Id-Vg curve obtained based on the test data, even when vbs is large to turn on the back channel (see Id-Vg characteristic data when vbs is 10V, vbs V, or 9V shown in fig. 3), the Id-Vg characteristic data is very close to the Id-Vg curve obtained based on the test data. Therefore, the model of the FDSOI MOSFET device established by the embodiment of the invention has higher precision.
Therefore, the BSIMIMG back channel device model and the BSIMG front channel device model are combined into one model in a sub-circuit mode, and the obtained synthetic model simultaneously contains the front channel current and the back channel current. The embodiment of the invention does not simply combine the devices, thereby avoiding the influence on the capacitance of the devices.
In a second aspect, based on the same inventive concept, an embodiment of the present invention provides an FDSOI MOSFET model generating apparatus based on bsiimg, including:
the model code modification unit is used for modifying the Verilog-a code of the BSIMG standard model to obtain a new BSIMG standard model;
the model parameter extraction unit is used for extracting a front channel device model parameter and a back channel device model parameter from the FDSOI MOSFET device;
a model generating unit, configured to generate a bsimg positive channel device model based on the positive channel device model parameters and the new bsimg standard model, and generate a bsimg back channel device model based on the back channel device model parameters and the new bsimg standard model;
the model synthesis unit is used for combining the BSIMIMG back channel device model to the BSIMG positive channel device model in a controlled source mode to obtain a synthesis model;
and the model parameter adjusting unit is used for adjusting the model parameters of the synthetic model to obtain the target FDSOI MOSFET model.
In a specific embodiment, the model parameter extracting unit is specifically configured to:
extracting a positive channel device model parameter of the FDSOI MOSFET device when a back channel of the FDSOI MOSFET device is in a non-opening state;
and extracting back channel device model parameters of the FDSOI MOSFET device when a front channel of the FDSOI MOSFET device is in a non-opening state.
In a specific embodiment, the model parameter extracting unit is specifically configured to extract a back gate oxygen thickness of the FDSOI MOSFET device as a front gate oxygen thickness of the bsimg back channel device model, extract a front gate oxygen thickness of the FDSOI MOSFET device as a back gate oxygen thickness of the bsimg back channel device model, and extract a back channel current of the FDSOI MOSFET device as a front channel current of the bsimg back channel device model.
In a specific embodiment, the model synthesis unit is specifically configured to:
applying a positive gate voltage to a back gate of the BSIMIMG back channel device model, applying a back gate voltage to a positive gate of the BSIMIMG back channel device model, and applying a drain voltage to a drain of the BSIMIMG back channel device model;
connecting a controlled source in parallel on the BSIMIMG positive channel device model, wherein the controlled source is a voltage control current source or a current control current source;
introducing the back channel current of the BSIMIMG back channel device model to the controlled source to obtain the total current of the synthetic model, which is the sum of the current of the BSIMG back channel device model and the current of the BSIMG positive channel device model.
In a specific embodiment, the model synthesis unit is specifically configured to:
arranging a first resistor on a drain electrode of the BSIMIMG back channel device model;
introducing a current across the first resistance or a voltage across the first resistance to the controlled source.
In a specific embodiment, the model code modification unit is specifically configured to:
modifying the effective back gate voltage in the Verilog-a code as follows: when the back gate voltage is greater than the back channel threshold voltage, the back gate effective voltage is equal to the back channel threshold voltage, and when the back gate voltage is less than the back channel accumulated voltage, the back gate effective voltage is equal to the back channel accumulated voltage.
In a specific embodiment, the model parameter adjusting unit is specifically configured to: and adjusting the positive gate threshold voltage and the back gate threshold voltage of the synthetic model.
It should be noted that, for implementation details of the FDSOI MOSFET model generation apparatus based on bsiimg in the embodiment of the present invention, reference may be made to implementation details in the foregoing method embodiment, and details are not repeated for brevity of the description.
In a third aspect, based on the same inventive concept, an embodiment of the present invention provides a bsiimmg-based FDSOI MOSFET model, including: the BSIMIMG device model comprises a BSIMIMG back channel device model and a BSIMIMG front channel device model, wherein the BSIMG back channel device model is combined to the BSIMG front channel device model in a controlled source mode; the BSIMIMG front channel device model is generated based on a new BSIMIMG standard model and front channel device model parameters extracted from an FDSOI MOSFET device, the BSIMG back channel device model is generated based on the new BSIMG standard model and back channel device model parameters extracted from the FDSOI MOSFET device, and the new BSIMG standard model is obtained by modifying Verilog-a codes of the BSIMG standard model.
It should be noted that, for details of the implementation of the FDSOI MOSFET model generation apparatus based on bsiimg in the embodiment of the present invention, reference may be made to the details of the foregoing method embodiment, and for brevity of the description, no further description is given here.
In the embodiment of the invention, based on the BSIMIMG FDSOI MOSFET model, on the basis of the BSIMIMG standard SOI device model BSIMG in the industry, the BSIMG back channel device model is combined to the BSIMG front channel device model in a controlled source form to obtain the synthetic model, so that back channel current is introduced into the BSIMG front channel device model in the controlled source form, the change of the coupling characteristic of back gate bias to a front channel when the back channel is opened can be responded, and the device model precision under the condition of opening the back channel is greatly improved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (9)

1. A method for generating an FDSOIMOSFET model based on BSIMIMG is characterized by comprising the following steps:
modifying the Verilog-a code of the BSIMG standard model to obtain a new BSIMG standard model;
extracting a front channel device model parameter and a back channel device model parameter from the FDSOI MOSFET device;
generating a BSIMIMG positive channel device model based on the positive channel device model parameters and the new BSIMG standard model, and generating a BSIMG back channel device model based on the back channel device model parameters and the new BSIMG standard model;
combining the BSIMIMG back channel device model to the BSIMG front channel device model in a controlled source mode to obtain a synthetic model;
and adjusting the model parameters of the synthetic model to obtain a target FDSOIMOSFET model.
2. The method of claim 1, wherein said extracting the forward channel device model parameters and the back channel device model parameters of the fdsoi imosfet device comprises:
extracting a positive channel device model parameter of the FDSOI MOSFET device when a back channel of the FDSOI MOSFET device is in an unopened state;
and extracting back channel device model parameters of the FDSOI MOSFET device when the front channel of the FDSOI MOSFET device is in a non-opening state.
3. The method of claim 2, wherein said extracting back channel device model parameters for said fdsoi imosfet device comprises:
extracting the back gate oxide thickness of the FDSOI MOSFET device as the front gate oxide thickness of the BSIMIMG back channel device model, an
Extracting the front gate oxide thickness of the FDSOI MOSFET device as the back gate oxide thickness of the BSIMIMG back channel device model, an
And extracting the back channel current of the FDSOI MOSFET device as the positive channel current of the BSIMIMG back channel device model.
4. The method of claim 1, in which the merging the BSIMG back channel device model to the BSIMG positive channel device model in controlled source form to obtain a composite model comprises:
applying a positive gate voltage to a back gate of the BSIMIMG back channel device model, applying a back gate voltage to a positive gate of the BSIMIMG back channel device model, and applying a drain voltage to a drain of the BSIMIMG back channel device model;
connecting a controlled source in parallel on the BSIMIMG positive channel device model, wherein the controlled source is a voltage control current source or a current control current source;
introducing the back channel current of the BSIMIMG back channel device model to the controlled source to obtain the total current of the synthetic model, which is the sum of the current of the BSIMG back channel device model and the current of the BSIMG positive channel device model.
5. The method of claim 4, in which the introducing back channel current of the BSIMIMG back channel device model to the controlled source comprises:
arranging a first resistor on a drain electrode of the BSIMIMG back channel device model;
introducing a current across the first resistance or a voltage across the first resistance to the controlled source.
6. The method of claim 1, wherein modifying Verilog-a code of the bsiimg standard model to obtain a new bsiimg standard model comprises:
modifying the effective back gate voltage in the Verilog-a code as follows: when the back gate voltage is greater than the back channel threshold voltage, the back gate effective voltage is equal to the back channel threshold voltage, and when the back gate voltage is less than the back channel accumulated voltage, the back gate effective voltage is equal to the back channel accumulated voltage.
7. The method of claim 1, wherein said adjusting model parameters of said synthesis model to obtain a target fdsoimfet model comprises:
and adjusting the positive gate threshold voltage and the back gate threshold voltage of the synthetic model.
8. The device for generating the FDSOIMOSFET model based on the BSIMIMG is characterized by comprising the following steps of:
the code modification unit is used for modifying the Verilog-a code of the BSIMIMG standard model to obtain a new BSIMG standard model;
the model parameter extraction unit is used for extracting a front channel device model parameter and a back channel device model parameter from the FDSOI MOSFET device;
a model generating unit, configured to generate a bsimg positive channel device model based on the positive channel device model parameters and the new bsimg standard model, and generate a bsimg back channel device model based on the back channel device model parameters and the new bsimg standard model;
the model synthesis unit is used for combining the BSIMIMG back channel device model to the BSIMG positive channel device model in a controlled source mode to obtain a synthesis model;
and the model parameter adjusting unit is used for adjusting the model parameters of the synthetic model to obtain a target FDSOIMOSFET model.
9. A BSIMIMG-based FDSOIMOSFET model, comprising:
the BSIMIMG device model comprises a BSIMIMG back channel device model and a BSIMIMG front channel device model, wherein the BSIMG back channel device model is combined to the BSIMG front channel device model in a controlled source mode;
the BSIMIMG front channel device model is generated based on a new BSIMIMG standard model and front channel device model parameters extracted from an FDSOI MOSFET device, the BSIMG back channel device model is generated based on the new BSIMG standard model and back channel device model parameters extracted from the FDSOI MOSFET device, and the new BSIMG standard model is obtained by modifying Verilog-a codes of the BSIMG standard model.
CN202010892877.1A 2020-08-31 2020-08-31 BSIMMG-based FDSOI MOSFET model generation method and device Pending CN112052637A (en)

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