CN112035386A

CN112035386A - Shared memory expansion device based on RapidIO

Info

Publication number: CN112035386A
Application number: CN202010787765.XA
Authority: CN
Inventors: 霍炳秀; 刘炳坤; 刘海玲; 朱恒飞
Original assignee: Tianjin Embedtec Co Ltd
Current assignee: Tianjin Embedtec Co Ltd
Priority date: 2020-08-07
Filing date: 2020-08-07
Publication date: 2020-12-04

Abstract

The invention discloses a device for realizing shared memory expansion based on RapidIO, which comprises a VPX connector physical connection circuit, a high-speed clock homologous circuit, a RapidIO enumeration exchange circuit and a main control and memory sharing circuit, wherein the VPX connector physical connection circuit is connected with equipment needing to expand a memory, the VPX connector physical connection circuit, the RapidIO enumeration exchange circuit and the main control and memory sharing circuit are sequentially connected, the high-speed clock homologous circuit is respectively connected with the VPX connector physical connection circuit, the RapidIO enumeration exchange circuit, the main control and memory sharing circuit, and the main control and memory sharing circuit carries the memory. The invention realizes the physical connection of the RapidIO bus through the VPX connector, shares abundant memory resources to external equipment through the RapidIO exchange chip and the programmable logic device, and has the characteristics of high integration level, strong operability, high stability and the like.

Description

Shared memory expansion device based on RapidIO

Technical Field

The invention belongs to the field of computer communication devices, and particularly relates to a device for realizing shared memory expansion based on RapidIO.

Background

With the increase of information data transmission quantity, the advantages of high-speed serial bus transmission among boards are larger and larger than those of a traditional pinhole type connector, the anti-interference capacity is strong, the connection is tight, the error rate is low, and the high-speed serial bus transmission method is widely applied to the fields of industrial control, aerospace and the like.

RapidIO is an interconnection architecture with high performance, low pin count and based on data packet exchange, is an open interconnection technical standard designed for meeting the requirements of future high-performance embedded systems, provides a high-speed and advanced communication technology for developers, and becomes a mainstream high-speed serial bus.

Due to the limitations of board card size, the limitations of central processing unit performance, memory granules and application upgrading and the like, the increasing complexity of application programs and the increasing promotion of data volume, the onboard memory cannot meet the increasing application requirements, and the realization of data processing by realizing memory expansion through external equipment becomes an effective method. However, no device capable of realizing memory expansion and data sharing between devices based on the RapidIO bus exists in the market at present.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a device for realizing shared memory expansion based on RapidIO.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a device for realizing shared memory expansion based on RapidIO comprises a VPX connector physical connection circuit, a high-speed clock homologous circuit, a RapidIO enumeration exchange circuit and a main control and memory sharing circuit, wherein the VPX connector physical connection circuit is connected with devices needing to expand a memory, an Rpad IO bus and a clock circuit of each device are connected through a VPX connector, the VPX connector physical connection circuit, the RapidIO enumeration exchange circuit, the main control and memory sharing circuit are sequentially connected, the high-speed clock homologous circuit is respectively connected with the VPX connector physical connection circuit, the RapidIO enumeration exchange circuit, the main control and memory sharing circuit, and the main control and memory sharing circuit carries the memory.

The invention realizes the physical connection of the RapidIO bus through the VPX connector, shares abundant memory resources to external equipment through the RapidIO exchange chip and the programmable logic device, and has the characteristics of high integration level, strong operability, high stability and the like.

Drawings

Fig. 1 is a circuit block diagram of an apparatus for implementing shared memory expansion based on RapidIO according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the figures and the detailed description.

As shown in fig. 1, a device for implementing shared memory expansion based on RapidIO includes a VPX connector physical connection circuit 1, a high-speed clock homologous circuit 2, a RapidIO enumeration exchange circuit 3, and a main control and memory sharing circuit 4, where the VPX connector physical connection circuit 1 is connected to a device 5 requiring memory expansion, the RpaidIO bus and the clock circuit of each device are connected through a VPX connector, the VPX connector physical connection circuit 1, the RapidIO enumeration exchange circuit 3, and the main control and memory sharing circuit 4 are sequentially connected, the high-speed clock homologous circuit 2 is respectively connected to the VPX connector physical connection circuit 1, the RapidIO enumeration exchange circuit 3, the main control and memory sharing circuit 4, and the main control and memory sharing circuit 4 mounts a memory 6.

The high-speed clock homologous circuit 2 comprises a crystal oscillator 22 and a clock chip 21, the high-speed clock homologous circuit provides a 25M clock through a 7050 crystal oscillator 22 of a Tang and Shang core, generates a multi-path homologous 125M HSCL level clock through an ICS9FG108 chip 21 of an IDT and transmits the multi-path homologous clock to each RapidIO device, and through the circuit, each level of device obtains a high-speed homologous differential clock, so that each device is maintained at the same vibration frequency, and the error rate caused by data errors and clock oscillation differences is reduced.

The RapidIO enumeration exchange circuit 3 is a circuit for realizing that each stage of equipment is scanned and data connection is realized, the RapidIO enumeration exchange circuit adopts an 80HCPS1848CRMI SRIO exchange chip of an IDT, and each stage of equipment obtains respective ID number after being electrified through the circuit, determines the channel number of the equipment, ensures high-speed stable transmission of data sharing, and realizes data connection of external equipment.

The main control and memory sharing circuit 4 is a circuit for realizing data control and memory expansion, adopts a sailing Z7FPGA as a main controller to control an SRIO switch chip, dynamically enumerates after being powered on, allocates resources to each device, mounts a memory on the Z7FPGA through a DDR3 interface, and is used by each level of devices, and through the circuit, device management, data flow control, memory expansion and data sharing are realized.

The invention realizes the physical connection of RapidIO bus through the VPX connector, shares abundant memory resources to external equipment through a RapidIO exchange chip and a programmable logic device, and the device is electrified and enumerated with each VPX device, the VPX device transmits the cached memory information or the information needing to be read to a control circuit through RapidIO, and the control circuit controls the memory to read and write.

The above examples are merely for illustrative clarity and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims

1. A device for realizing shared memory expansion based on RapidIO is characterized by comprising a VPX connector physical connection circuit, a high-speed clock homologous circuit, a RapidIO enumeration exchange circuit and a main control and memory sharing circuit, wherein the VPX connector physical connection circuit is connected with equipment needing to expand a memory, the VPX connector physical connection circuit, the RapidIO enumeration exchange circuit and the main control and memory sharing circuit are sequentially connected, the high-speed clock homologous circuit is respectively connected with the VPX connector physical connection circuit, the RapidIO enumeration exchange circuit, the main control and memory sharing circuit, and the main control and memory sharing circuit carries the memory.

2. The apparatus of claim 1, wherein the high-speed clock homologous circuit comprises a crystal oscillator and a clock chip, the high-speed clock homologous circuit provides 25M clocks through a 7050 crystal oscillator of a Thangshan core, and an ICS9FG108 chip passing through the IDT generates a multi-channel homologous 125M HSCL level clock to be transmitted to each RapidIO device.

3. The apparatus of claim 1, wherein the RapidIO enumeration switch circuit employs an IDT 80HCPS1848CRMI SRIO switch chip.

4. The apparatus for implementing shared memory expansion based on RapidIO of claim 1, wherein the main control and memory sharing circuit uses a sailingsi Z7FPGA as a main controller to control an SRIO switch chip, after power-on, dynamic enumeration is performed to allocate resources to each device, and a Z7FPGA mounts a memory through a DDR3 interface for use by each level of devices.