CN112018097A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN112018097A
CN112018097A CN202010914374.XA CN202010914374A CN112018097A CN 112018097 A CN112018097 A CN 112018097A CN 202010914374 A CN202010914374 A CN 202010914374A CN 112018097 A CN112018097 A CN 112018097A
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dies
die
logic die
wafer
gas
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CN112018097B (en
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刘峻
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: a first structure comprising a number of first dies extending in a first direction, the first dies having first sidewalls extending in a thickness direction of the first dies; a second structure located on one side of the first structure in the first direction, the second structure comprising a number of second dies; and the first structure and the second structure are in electrical contact at the first side wall. The invention avoids the problem caused by pure stacking along the vertical direction by electrically contacting the side wall of the tube core with the tube core stacking structure formed by one tube core or a plurality of tube cores, balances the stress of the semiconductor device, ensures the bonding strength between wafers, shortens the distance between the devices, improves the interconnection performance of the devices and reduces the consumption of silicon wafer materials.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure bonded through sidewalls and a method for fabricating the same.
Background
As the feature size of semiconductor devices continues to decrease and the storage capacity continues to increase, planar processes and manufacturing techniques have failed to meet the increasing and changing demands of semiconductor devices. Three-dimensional (3D) device architectures may address density limitations in some planar semiconductor devices. In order to obtain the three-dimensional device, a three-dimensional stacked wafer structure can be obtained through a bonding technology between wafers, and then the three-dimensional stacked wafer is cut and packaged to form the three-dimensional semiconductor device. During the wafer bonding process, the alignment between devices on the wafer, wafer deformation caused by wafer stress, and other problems all have important influence on the packaging result.
Disclosure of Invention
The present invention is directed to a semiconductor structure and a method for fabricating the same that avoid the problems of the vertical stack structure.
The present invention is directed to a semiconductor structure, which solves the above problems, and includes: a first structure comprising a number of first dies extending in a first direction, the first dies having first sidewalls extending in a thickness direction of the first dies; a second structure located on one side of the first structure in the first direction, the second structure comprising a number of second dies; and the first structure and the second structure are in electrical contact at the first side wall.
In an embodiment of the invention, the second structure includes a second sidewall adjacent to the first structure, a first microbump is included between the second sidewall and the first sidewall, and the first structure and the second structure are electrically contacted through the first microbump.
In an embodiment of the present invention, the first structure includes a plurality of the first dies stacked in a second direction perpendicular to the first direction; and/or the second structure comprises a plurality of the second dies, and the second dies are stacked along a second direction perpendicular to the first direction.
In an embodiment of the present invention, the first structure includes a plurality of the first dies stacked in a second direction perpendicular to the first direction; and/or the second structure comprises one or more second dies extending along a second direction perpendicular to the first direction, and a plurality of the second dies are stacked along the first direction.
In an embodiment of the present invention, the method further includes: a logic die, the first structure and the second structure being located above the logic die; the logic die is electrically connected with the first die of the first structure; and/or the logic die is electrically connected with the second die of the second structure.
In an embodiment of the invention, each of the plurality of first dies comprises a first bonding layer, the first bonding layer comprises a plurality of conductive contacts and a dielectric layer, and the plurality of first dies are hybrid bonded through the first bonding layer; and/or each of the plurality of second dies comprises a second bonding layer, the second bonding layer comprises a plurality of conductive contacts and a dielectric layer, and the plurality of second dies are mixed and bonded through the second bonding layer.
In an embodiment of the present invention, the semiconductor device further includes a first interconnect structure penetrating through the stacked plurality of first dies, and a fourth micro bump located between adjacent first dies, where the fourth micro bump corresponds to a position of the first interconnect structure, and the plurality of first dies are electrically connected to each other through the first interconnect structure and the fourth micro bump; and/or the second interconnection structure penetrates through a plurality of stacked second dies, and a fifth micro bump is positioned between the adjacent second dies, the position of the fifth micro bump corresponds to that of the second interconnection structure, and the plurality of second dies are electrically connected with each other through the second interconnection structure and the fifth micro bump.
In one embodiment of the invention, the first structure comprises a first bottom surface adjacent to the logic die, a second micro bump is arranged between the first bottom surface and the top surface of the logic die, and the logic die and the first structure are electrically contacted through the second micro bump; and/or the second structure comprises a second bottom surface adjacent to the logic die, a third micro bump is arranged between the second bottom surface and the top surface of the logic die, and the logic die and the second structure are electrically contacted through the third micro bump.
In an embodiment of the present invention, the logic die further includes a plurality of third interconnect structures extending through the logic die, a portion of the second micro-bumps corresponding to a portion of the plurality of third interconnect structures, and a portion of the third micro-bumps corresponding to a portion of the third interconnect structures.
In an embodiment of the invention, further comprising a contact area extending through the number of first dies, the contact area comprising a trench and/or a via.
In order to solve the above technical problem, the present invention further provides a method for manufacturing a semiconductor structure, including: providing a first wafer comprising a first structure comprising a number of first dies extending along a first direction, the first dies having first sidewalls extending along a thickness direction of the first dies; providing a second wafer comprising a second structure, wherein the second structure comprises a plurality of second dies; and bonding the first wafer and the second wafer to enable the second structure to be located on one side of the first structure in the first direction, and enabling the first structure and the second structure to be in electrical contact at the first side wall.
In an embodiment of the present invention, the method further includes: the second structure comprises a second side wall adjacent to the first structure, a first micro bump is formed between the second side wall and the first side wall, and the first structure is electrically contacted with the second structure through the first micro bump.
In an embodiment of the invention, the first structure comprises a plurality of first dies stacked in a second direction perpendicular to the first direction; and/or the second structure comprises a plurality of second dies, and a plurality of the second dies are stacked along a second direction perpendicular to the first direction.
In an embodiment of the invention, the first structure comprises a plurality of first dies stacked in a second direction perpendicular to the first direction; and/or the second structure comprises one or more second dies extending along a second direction perpendicular to the first direction, and a plurality of the second dies are stacked along the first direction.
In an embodiment of the present invention, the method further includes: providing a third wafer comprising logic dies; bonding the third wafer and the first wafer to electrically connect the logic die with the first die of the first structure; and/or bonding the third wafer and the second wafer to electrically connect the logic die with the second die of the second structure.
In an embodiment of the present invention, the method further includes: each of the plurality of first dies comprises a first bonding layer, the first bonding layer comprises a plurality of conductive contacts and a dielectric layer, and the plurality of first dies are mixedly bonded through the first bonding layer; and/or each of the plurality of second dies comprises a second bonding layer, the second bonding layer comprises a plurality of conductive contacts and a dielectric layer, and the plurality of second dies are mixed and bonded through the second bonding layer.
In an embodiment of the present invention, the method further includes: forming a first interconnection structure penetrating through a plurality of stacked first dies and forming a fourth micro bump between the adjacent first dies, wherein the position of the fourth micro bump corresponds to the position of the first interconnection structure, and the plurality of first dies are electrically connected with each other through the first interconnection structure and the fourth micro bump; and/or forming a second interconnection structure penetrating through the stacked second dies and forming a fifth micro bump between the adjacent second dies, wherein the fifth micro bump corresponds to the position of the second interconnection structure, and the second dies are electrically connected with each other through the second interconnection structure and the fifth micro bump.
In an embodiment of the present invention, the method further includes: the first structure comprises a first bottom surface adjacent to the logic die, a second micro bump is formed between the first bottom surface and the top surface of the logic die, and the logic die and the first structure are electrically contacted through the second micro bump; and/or the second structure comprises a second bottom surface adjacent to the logic die, a third micro bump is formed between the second bottom surface and the top surface of the logic die, and the logic die and the second structure are electrically contacted through the third micro bump.
In an embodiment of the present invention, the method further includes: forming a plurality of third interconnect structures through the logic die, portions of the second micro-bumps corresponding to portions of the plurality of third interconnect structures, and portions of the third micro-bumps corresponding to portions of the third interconnect structures.
In an embodiment of the present invention, the method further includes: forming contact regions through the number of first dies, the contact regions including trenches and/or vias.
The invention avoids the problem caused by pure stacking along the vertical direction by electrically contacting the side wall of the tube core with the tube core stacking structure formed by one tube core or a plurality of tube cores, balances the stress of the semiconductor device, ensures the bonding strength between wafers, shortens the distance between the devices, improves the interconnection performance of the devices and reduces the consumption of silicon wafer materials.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIGS. 1A-1E are process diagrams of a wafer bonding method;
FIG. 2 is a schematic diagram of a wafer bonding structure;
FIGS. 3A-3C are process diagrams of a wafer bonding method;
FIG. 4 is a schematic diagram of a semiconductor structure in accordance with one embodiment of the present invention;
FIG. 5 is a schematic diagram of a semiconductor structure in accordance with one embodiment of the present invention;
FIG. 6 is a schematic diagram of a semiconductor structure in accordance with one embodiment of the present invention;
FIG. 7 is a schematic diagram of a semiconductor structure in accordance with one embodiment of the present invention;
FIG. 8 is a schematic diagram of a semiconductor structure in accordance with one embodiment of the present invention;
FIG. 9 is a schematic diagram of a semiconductor structure in accordance with one embodiment of the present invention;
fig. 10 is an exemplary flow chart of a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
As used herein, the term "three-dimensional (3D) memory" refers to a semiconductor device having memory cells that: the memory cells are arranged vertically on a laterally oriented substrate such that the number of memory cells increases in the vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of a substrate.
Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.
The Chip in the invention refers to a Chip (Chip) capable of being packaged. The Die in the invention refers to a Die (Die) to be packaged contained in a chip, and one chip can contain a plurality of dies.
Fig. 1A-1E are process diagrams of a wafer bonding method. Referring to fig. 1A, first, a first wafer 110 and a second wafer 120 are provided, and surface plasma activation is performed on the first wafer 110 and the second wafer 120, respectively. As shown in fig. 1A, a first wafer 110 and a second wafer 120 are respectively placed in a container 101, a large number of electrons are generated in the container 101 by a high-frequency alternating electric field, the electrons are accelerated and collide with gas molecules to form plasma, and the surfaces of the first wafer 110 and the second wafer 120 are activated by bombardment of the accelerated plasma.
Referring to fig. 1B, a cleaning process is performed on the wafer surface at this step. In this step, deionized Water (DI Water) may be sprayed from the showers 111, 112 onto the first wafer 110 and the second wafer 120, respectively, to remove particles on the surfaces of the first wafer 110 and the second wafer 120. The steps may include loading the wafer, cleaning using ultrasonic oscillations, spin drying at high speed, unloading the wafer, and the like.
Referring to fig. 1C, wafer alignment is performed at this step. This step may include instrument calibration, loading wafers, error compensation, position alignment, etc. Fig. 1C is merely illustrative and is not intended to cover all wafer alignment steps. As shown in fig. 1C, the first wafer 110 may be moved in a horizontal direction to align with the second wafer 120.
Referring to fig. 1D, wafer bonding is performed at this step. The wafer bonding structure is formed by performing a bonding operation on the first wafer 110 and the second wafer 120 by using the bonding apparatus 130 shown in fig. 1D.
Wafer Bonding technology (Wafer Bonding) for three-dimensional stacking is the chemical and physical Bonding of two mirror-polished, clean, homogeneous or heterogeneous wafers. After the wafers are bonded, atoms of the bonding interface are acted by external force to react to form covalent bonds to be combined into a whole, and the bonding interface achieves certain bonding strength.
Referring to fig. 1E, the wafer bond structure after bonding is annealed at this step. The annealing process can make the bonding interface stronger.
The bonding method shown in fig. 1A-1E is performed through a whole wafer, also referred to as wafer-to-wafer bonding.
Fig. 2 is a schematic diagram of a wafer bonding structure. Referring to fig. 2, a plurality of repeated chip units 211 are bonded to a wafer 210, and after one chip unit 211 is enlarged, the chip unit 211 includes a plurality of dies having different shapes, sizes, and functions. As shown in fig. 2, the plurality of dies include MEMS, Passive components (Passive components), RF chips (RF chips), processors (processors), memories (memories), Logic LSI, IF chips, and the like. The wafer bonding structure is a structure for bonding a chip and a wafer, and can be realized by a method for bonding the chip and the wafer.
It is understood that the illustration in fig. 2 is merely illustrative and is not intended to limit the size, functionality, and components of the chip units 211 on the wafer 210.
Fig. 3A-3C are process diagrams of a wafer bonding method. Referring to fig. 3A, a first wafer 310 and a second wafer 320 are provided. The first wafer 310 and the second wafer 320 are both diced wafers. Although the first wafer 310 and the second wafer 320 still appear to be complete wafers, the first wafer 310 and the second wafer 320 have a plurality of individual dies to be packaged formed thereon. The plurality of dies to be packaged are connected together through the film layer at the bottom respectively. A first wafer 310 is mounted on a Multi-chip mounting-up Holder 330.
Referring to fig. 3B, the multi-chip mounting bracket 330 may release the first wafer 310 after optical self-alignment, such that the plurality of dies on the first wafer 310 are aligned and bonded with the plurality of dies on the second wafer 320. Fig. 3B shows an intermediate state after the first wafer 310 is released from the multi-chip mounting bracket 330.
Fig. 3C shows a bonded structure 340 formed after the first wafer 310 and the second wafer 320 are bonded.
The chip-to-chip bond is formed through the bonding steps of fig. 3A-3C. The present invention does not limit the number of chips to be bonded to each other in the present embodiment. The chips in the entire first wafer and the second wafer may be bonded together, or only a part of the chips in the first wafer and the second wafer may be bonded together.
In order to continue bonding more wafers, the wafer backs of the wafers at the outermost layers among the already bonded wafer layers are thinned. And after the wafers are bonded, coating photoresist on the wafer back of the outermost layer of wafer for protecting, and then pasting a film for protecting. The applied film is for example a 10-200 micron blue or UV film.
In some embodiments, the method further comprises the step of performing wet removal on the wafer by cleaning, spin-drying and other methods to remove the photoresist and silicon dust and silicon slag used for protection on the back surface of the wafer.
Fig. 1A to 1E show a wafer-to-wafer bonding method, fig. 2 shows a chip-to-wafer bonding structure, and fig. 3A to 3C show a chip-to-chip bonding method. If the extending plane of the wafer is taken as the horizontal direction (X-Y plane), the three wafer bonding methods are all stacked bonding in the vertical direction (Z axis). As the number of stacked layers increases, the lower devices are more affected by the subsequent processing of the upper devices, and the devices are increasingly exhibiting performance degradation and non-uniformity. In addition, as the number of stacked layers in the vertical direction increases, the stress in the wafer and the stress between the stacked layers, as well as alignment problems, become increasingly difficult to follow in the stacking and bonding process. Furthermore, various stacking processes in 2.5D and 3D IC packaging technologies have some drawbacks, including but not limited to: wafer breakage due to stress, Through Silicon Via (TSV) stress affecting device performance, back-of-the-wafer metal contamination, etc.
Fig. 4 is a schematic diagram of a semiconductor structure according to an embodiment of the invention. Referring to fig. 4, the semiconductor structure includes a first structure 410 and a second structure 420. Wherein the first structure 410 comprises a number of first dies 411 extending along the first direction D1 and the second structure 420 comprises a number of second dies 421. Several of these means one or more. In the embodiment shown in fig. 4, the first structure 410 comprises only one first die 411 and the second structure 420 comprises only one second die 421. The second structure 420 is located at one side of the first structure 410 in the first direction D1.
In the embodiment shown in fig. 4, the first die 411 has a first sidewall 412, the first sidewall 412 extending in a thickness direction of the first die 411. Fig. 4 is a side cross-sectional view of the semiconductor structure in a normal-placement state in which the first direction D1 is a horizontal direction and the second direction D2 is a vertical direction. As shown in fig. 4, the first die 411 has a rectangular cross-sectional side view. Preferably, the first die 411 is a rectangular parallelepiped structure having a thickness, and the height of the rectangle of the cross-sectional side view structure shown in fig. 4 along the second direction D2 is the thickness of the first die 411. Those skilled in the art will appreciate that the first die 411 may include four first sidewalls 412, first sidewalls 412a and 412b labeled as being in opposing positions in fig. 4.
Fig. 4 is not intended to limit the specific shape, size, and shape and number of sidewalls of the first die 411.
In the embodiment shown in fig. 4, the second structure 420 includes one second die 421. Preferably, the second die 421 is a rectangular structure having a thickness, and the height of the rectangle of the cross-sectional side view structure shown in fig. 4 along the second direction D2 is the thickness of the second die 421. The first structure 410 and the second structure 420 are in electrical contact at the first sidewall 412.
The shape and function of the second die 421 are not limited by the present invention. The portion of the second die 421 that contacts the first sidewall 412 is not limited. The contact position of the second die 421 and the first sidewall 412 will be described separately below.
The present invention is not limited to the specific embodiment in which the first structure 410 and the second structure 420 are in electrical contact. The electrical contact may be made by metal wire bonding between the dies, bonding, etc.
In some embodiments, the second die of the present invention includes a second sidewall adjacent to the first structure, a first microbump is included between the second sidewall and the first sidewall, and the first structure 410 and the second structure 420 are in electrical contact via the first microbump.
Referring to fig. 4, the second die 421 includes a second sidewall 422 extending along the second direction D2, and the first micro bump 430 is located between the first sidewall 412a and the second sidewall 422.
It is understood that the first microbumps 430 are located between the first structure 410 and the second structure 420, and thus the first sidewall 412a and the second sidewall 422 are adjacent to each other, and the second sidewall 422 refers to a sidewall of the second die 421 in a direction close to the first die 411. As shown in fig. 4, the second structure 420 is located on the left side of the first structure 410, and accordingly the second sidewall 422 refers to the right sidewall of the second die 421. In other embodiments, if the second structure 420 is located on the right side of the first structure 410, the first microbumps 430 are located between the first sidewall 412b and the second sidewall 422, where the second sidewall 422 refers to the sidewall of the second die 421 in the direction close to the first die 411.
It is understood that if the first die of the rectangular parallelepiped structure has four sidewalls when viewed from the top, all four sidewalls may be in electrical contact with one second die respectively, that is, four second dies are surrounded on the periphery of the first die, and the first micro bumps are included between the four sidewalls of the first die and the second sidewalls of the four second dies.
Two first microbumps 430 are shown in fig. 4, and fig. 4 is not intended to limit the number of first microbumps 430.
Referring to fig. 4, in some embodiments, the semiconductor structure of the present invention further includes a logic die 440, wherein the logic die 440 is located under the first structure 410 and the second structure 420 along the second direction D2 and is electrically connected to the first die 411 of the first structure 410 and/or electrically connected to the second die 421 of the second structure 420.
As shown in fig. 4, the length of the logic die 440 along the first direction D1 is greater than the sum of the lengths of the first structure 410 and the second structure 420 along the first direction D1 so that the logic die 440 can carry both the first structure 410 and the second structure 420. In the embodiment shown in fig. 4, the logic die 440 is electrically connected to both the first structure 410 and the second structure 420. In other embodiments, the logic die 440 may be electrically connected to only one of the first structure 410 and the second structure 420.
The present invention is not limited as to the manner in which the logic die 440 is electrically connected to the first structure 410 and/or the second structure 420.
For example, in the embodiment shown in fig. 4, the first structure 410 includes a first bottom surface 413 adjacent to the logic die 440, a plurality of second micro bumps 414 are included between the first bottom surface 413 and the top surface of the logic die 440, the logic die 440 and the first structure 410 are in electrical contact via the second micro bumps 414, and the second structure 420 includes a second bottom surface 423 adjacent to the logic die 440, a plurality of third micro bumps 424 are included between the second bottom surface 423 and the top surface of the logic die 440, and the logic die 440 and the second structure 420 are in electrical contact via the third micro bumps 424.
As shown in fig. 4, in some embodiments, an interconnect structure 415 is included in the first die 411, and the interconnect structure 415 corresponds to the second microbumps 414 one to one, thereby electrically connecting the logic die 440 to the first die 411. A plurality of second microbumps 414 and a plurality of interconnect structures 415 are shown in fig. 4, and the number of second microbumps 414 and interconnect structures 415 is not limited by the present invention.
As shown in fig. 4, in some embodiments, an interconnect structure 425 is included in the second die 421, and the interconnect structure 425 corresponds to the third microbumps 424 one-to-one, thereby electrically connecting the logic die 440 to the second die 421. A plurality of third microbumps 424 and interconnect structures 425 are shown in fig. 4, and the number of third microbumps 424 and interconnect structures 425 is not a limitation of the present invention. The interconnect structures 415, 425 may be holes or trenches.
Referring to fig. 4, a substrate 450 may also be included under the logic die 440. The substrate 450 is in electrical contact with the logic die 440 via a plurality of microbumps 441, 443.
In some embodiments, a plurality of third interconnect structures 442, 444 may be included in the logic die 440, and the plurality of third interconnect structures 442, 444 may be connected to the second microbumps 414, the third microbumps 424 on the top surface of the logic die 440, and to a portion of the plurality of microbumps 441, 443 on the bottom surface of the logic die 440.
In some embodiments, a portion of the second microbumps 414 corresponds to a portion of the third interconnect structure 442 and a portion of the third microbumps 424 corresponds to a portion of the third interconnect structure 444.
The third interconnect structures 442, 444 may be through-silicon vias through the logic die 440, with the substrate 450 electrically connected to the first structure 410 over the logic die 440 via the microbumps 441 and the third interconnect structure 442, and the substrate 450 electrically connected to the second structure 420 over the logic die 440 via the microbumps 443 and the third interconnect structure 444. The present invention is not limited to the specific embodiment of the substrate 450, and a PCB substrate, a flexible substrate, or the like may be used.
According to the semiconductor structure shown in fig. 4, the first sidewall 412 and the second sidewall 422 are used to establish electrical connection between the first structure 410 and the second structure 420, so that the distance between the first structure 410 and the second structure 420 is shortened, the interconnection performance of the device is improved, and the consumption of silicon wafer material is reduced.
Fig. 5 is a schematic diagram of a semiconductor structure according to an embodiment of the invention. Referring to fig. 5, a first structure 510 of the semiconductor structure includes a plurality of first dies 511 therein. The first die 511 is similar to the first die 411 shown in fig. 4, a plurality of first dies 511 are stacked along a second direction D2 perpendicular to the first direction D1 to form a die stack structure, and each of the first dies 511 has a first sidewall 512 extending along the second direction D2.
In some embodiments, each of the plurality of first dies 511 includes a first bonding layer including a plurality of conductive contacts and a dielectric layer, through which the plurality of first dies 511 are hybrid bonded. Hybrid bonding is a direct bonding technique, for example, where a bond is formed between surfaces without the use of an intermediate layer (e.g., solder or adhesive), and both metal-to-metal and dielectric-to-dielectric bonds can be achieved. It is to be understood that the plurality of first dies 511 are stacked along the second direction D2, and therefore, the first bonding layers of two adjacent first dies 511 should be located at the interface where the two first dies 511 are bonded to each other. For the first die 511 located at the top layer, the first bonding layer is located at the bottom surface of the first die 511; for the first die 511 located at the bottom layer, the first bonding layer is located at the top surface of the first die 511; for the first die 511 in the middle, there is one first bonding layer on its bottom and top surfaces, respectively, i.e. there are a total of two first bonding layers.
In some embodiments, the first interconnect structures 516 of the plurality of first dies 511 penetrating the stack and the fourth micro bumps positioned between the adjacent first dies 511 are further included, the fourth micro bumps correspond to the positions of the first interconnect structures 516, and the plurality of first dies 511 are in electrical contact with each other through the first interconnect structures 516 and the fourth micro bumps. As shown in fig. 5, four first dies 511 are stacked along the second direction D2, wherein, taking the second first die 511 from the top as an example, the first die 511 includes a first interconnect structure 516 penetrating through the first die 511, and the first interconnect structure 516 may be a through-silicon via. The upper and lower surfaces of the first die 511 further include fourth micro bumps 515 and 517 corresponding to the first interconnect structures 516, and the fourth micro bumps 515 and 517 are in one-to-one correspondence with the first interconnect structures 516, so that the first die 511 is electrically connected to other first dies 511 located above and below the first die 511. In some embodiments, the semiconductor structure further includes a contact region extending through the plurality of first dies, the contact region including a trench and/or a via. This embodiment is not shown in fig. 5, it being conceivable that a plurality of first dies 511 are bonded to each other, including therein contact areas extending through the die stack for establishing connections with external elements. The trench and the via hole as the contact region may be plural.
As shown in fig. 5, an interconnect structure 518 may be included in the first die 511 located at the topmost layer in the die stack structure. The interconnect structure 518 may not extend through the first die 511.
In the embodiment shown in fig. 5, the first structure 510 includes a second die 521 therein, and the second die 521 includes a second sidewall 522 extending along a second direction D2. The first die 511 located at the lowermost layer in the die stack structure includes a first sidewall 512 extending in the second direction D2. The first micro bump 530 is located between the first sidewall 512 and the second sidewall 522, and the first structure 510 and the second structure 520 are electrically contacted through the first micro bump 530.
Similar to the embodiment shown in fig. 4, for the embodiment shown in fig. 5, a second die is electrically connected to the first die at the lowest level in the die stack structure. If viewed from a top view, the first die having a rectangular parallelepiped structure may have four sidewalls, and all of the four sidewalls may be in electrical contact with one second die respectively, that is, a total of four second dies are surrounded around the first die, and the four sidewalls of the first die and the second sidewalls of the four second dies all include the first micro bumps therebetween.
Referring to fig. 5, in some embodiments, the semiconductor structure of the present invention further comprises a logic die 540, wherein the logic die 540 is located under the first structure 510 and the second structure 520 along the second direction D2, and is in electrical contact with the first structure 510. As shown in fig. 5, the length of the logic die 540 along the first direction D1 is greater than the sum of the lengths of the first structure 510 and the second structure 520 along the first direction D1 so that the logic die 540 can carry both the first structure 510 and the second structure 520.
The present invention is not limited as to the manner in which the logic die 540 is in electrical contact with the first structure 510. In some embodiments, a plurality of second microbumps 514 are included on the first bottom surface 513 of the first structure 510 adjacent to the logic die 540, and a first interconnect structure 519 is included in the first die 511 at the bottom of the die stack structure, the first interconnect structure 519 being in one-to-one correspondence with the microbumps 514 such that the logic die 540 is in electrical contact with the first die 511. A plurality of second microbumps 514 and first interconnect structures 519 are shown in fig. 5, and the invention is not limited by the number of second microbumps 514 and first interconnect structures 519.
In these embodiments, the second die 521 includes a second bottom surface 523 extending along the first direction D1. A third microbump 524 is included between the second bottom surface 523 and the logic die 540, and the second structure 520 and the logic die 540 are in electrical contact through the third microbump 524. An interconnect structure 525 is included in the second die 521, and the interconnect structure 525 corresponds to the third micro bumps 524 one by one, so that the logic die 540 is electrically contacted with the second die 521. A plurality of third microbumps 524 and interconnect structures 525 are shown in fig. 5, and the number of third microbumps 524 and interconnect structures 525 is not a limitation of the present invention. The interconnect structures 518, 525 may be holes or trenches.
Referring to fig. 5, a substrate 550 may also be included under the logic die 540. The substrate 550 and the logic die 540 are in electrical contact via a plurality of micro-bumps 541 and 543. A plurality of third interconnect structures 542, 544 may be included in the logic die 540, the plurality of third interconnect structures 542, 544 may be connected to the second microbumps 514, the third microbumps 524 on a top surface of the logic die 540 and to a portion of the plurality of microbumps 541, 543 on a bottom surface of the logic die 540.
In some embodiments, a portion of the second microbumps 514 corresponds to a portion of the third interconnect structure 542 and a portion of the third microbumps 524 corresponds to a portion of the third interconnect structure 544.
The third interconnect structures 542, 544 may be through-silicon vias that extend through the logic die 540, and the substrate 550 and the first structure 510 above the logic die 540 are electrically connected by the microbumps 541 and the third interconnect structure 542, and the substrate 450 and the second structure 520 above the logic die 540 are electrically connected by the microbumps 543 and the third interconnect structure 544. The present invention is not limited to the specific embodiment of the substrate 550, and a PCB substrate, a flexible substrate, or the like may be used.
According to the semiconductor structure shown in fig. 5, the first structure 510 and the second structure 520 are electrically connected through the first sidewall 512 and the second sidewall 522, so that the distance between the first structure 510 and the second structure 520 is shortened, the interconnection performance of the device is improved, and the consumption of silicon wafer materials is reduced.
Fig. 6 is a schematic diagram of a semiconductor structure according to an embodiment of the invention. Referring to fig. 6, the semiconductor structure includes a plurality of first dies 611 in a first structure 610 and a plurality of second dies 621 in a second structure 620. Wherein a plurality of first die 611 are stacked along the second direction D2 to form a die stack structure, each first die 611 having a first sidewall 612 extending along the second direction D2. A plurality of second dies 621 are stacked along the second direction D2 to form a die stack structure, each second die 621 having a second sidewall 622 extending along the second direction D2.
Similar to the embodiment shown in fig. 5, hybrid bonding may be used between the first dies 611, or through microbumps and through-silicon vias.
In some embodiments, each of the plurality of first dies 611 includes a first bonding layer including a plurality of conductive contacts and a dielectric layer, the plurality of first dies 611 being hybrid bonded therebetween by the first bonding layer. It is to be understood that the plurality of first dies 611 are stacked along the second direction D2, and therefore, the first bonding layers of two adjacent first dies 611 should be located at the face where the two first dies 611 are bonded to each other. For the first die 611 located at the top layer, the first bonding layer is located at the bottom surface of the first die 611; for the first die 611 located at the bottom layer, the first bonding layer is located at the top surface of the first die 611; for the first die 611 in the middle, there is one first bonding layer on each of its bottom and top surfaces, i.e. a total of two first bonding layers.
In some embodiments, the first interconnect structures 616 of the plurality of first dies 611 penetrating the stack and the fourth micro bumps between the adjacent first dies 611 are further included, the fourth micro bumps correspond to the positions of the first interconnect structures 616, and the plurality of first dies 611 are in electrical contact with each other through the first interconnect structures 616 and the fourth micro bumps. As shown in fig. 6, four first dies 611 are stacked along the second direction D2, wherein, taking the second first die 611 from the top as an example, the first die 611 includes a first interconnect structure 616 penetrating the first die 611, and the first interconnect structure 616 may be a through-silicon via. The first die 611 further includes fourth micro bumps 615 and 617 on the upper and lower surfaces thereof corresponding to the first interconnect structures 616, and the fourth micro bumps 615 and 617 are in one-to-one correspondence with the first interconnect structures 616, so as to electrically connect the first die 611 to other first dies 611 located above and below the first die 611.
As shown in fig. 6, an interconnect structure 618 may be included in the first die 611 that is positioned at the topmost level in the die stack structure. The interconnect structure 618 may not extend through the first die 611.
Similar to the die stack structure formed by the plurality of first dies 611, in the die stack structure formed by the plurality of second dies 621, hybrid bonding may be adopted between the plurality of second dies 621, and bonding may also be realized through micro bumps and through silicon vias.
In some embodiments, each of the plurality of second dies 621 includes a second bonding layer including a plurality of conductive contacts and a dielectric layer, and the plurality of second dies 621 are hybrid bonded therebetween by the second bonding layer. It is to be understood that the plurality of second dies 611 are stacked along the second direction D2, and therefore, the second bonding layers of two adjacent second dies 621 should be located at the interface where the two second dies 621 are bonded to each other. For the second die 621 located on the top layer, the second bonding layer is located on the bottom surface of the second die 621; for the second die 621 located at the bottom layer, the second bonding layer is located at the top surface of the second die 621; for the second die 621 in the middle, there is one second bonding layer on each of its bottom and top surfaces, i.e., there are two second bonding layers in total.
In some embodiments, the second interconnect structure 626 penetrating the stacked plurality of second dies 621 and a fifth micro bump located between the adjacent second dies 621 are further included, the fifth micro bump corresponds to the position of the second interconnect structure 626, and the plurality of second dies 621 are in electrical contact with each other through the second interconnect structure 626 and the fifth micro bump. . As shown in fig. 6, four second dies 621 are stacked along the second direction D2, wherein, taking the second die 621 from top to bottom as an example, the second die 6211 includes a second interconnect structure 626 penetrating through the second die 621, and the second interconnect structure 626 may be a through-silicon via. The second die 621 further includes fifth micro bumps 625 and 627 corresponding to the second interconnect structure 626 on the upper and lower surfaces thereof, wherein the fifth micro bumps 625 and 627 correspond to the second interconnect structure 626 in a one-to-one manner, so that the second die 621 is electrically connected to other second dies 621 located above and below the second die 621.
As shown in fig. 6, an interconnect structure 628 may be included in the second die 621 that is positioned at the topmost layer in the die stack structure. The interconnect structure 628 may not extend through the second die 621. The interconnect structures 618, 628 may be holes or trenches.
Referring to fig. 6, a first micro bump 630 is formed between the first sidewall 612 of each first die 611 and the second sidewall 622 of each second die 621, and the first structure 610 and the second structure 620 are in electrical contact via the first micro bumps 630.
Referring to fig. 6, in some embodiments, the semiconductor structure of the present invention further includes a logic die 640, wherein the logic die 640 is located under the first structure 610 and the second structure 620 along the second direction D2 and is in electrical contact with the first structure 610. As shown in fig. 6, the length of the logic die 640 in the first direction D1 is greater than the sum of the lengths of the first structure 610 and the second structure 620 in the first direction D1 so that the logic die 640 can carry both the first structure 610 and the second structure 620.
The present invention is not limited as to the manner in which the logic die 640 is in electrical contact with the first structure 610. In some embodiments, a plurality of second microbumps 614 are included on the first bottom surface 613 of the first structure 610 adjacent to the logic die 640, and a first interconnect structure 619 is included in the first die 611 at the bottom of the die stack structure, the first interconnect structure 619 corresponding to the second microbumps 614 one-to-one, such that the logic die 640 is in electrical contact with the first die 611. While a plurality of second microbumps 614 and first interconnect structures 619 are shown in FIG. 6, the invention is not limited by the number of second microbumps 614 and first interconnect structures 619.
In these embodiments, the second die 621 of the plurality of second dies 621 that is adjacent to the logic die 640 includes a second bottom surface 623 that extends along the first direction D1. A third microbump 624 is included between the second bottom surface 623 and the logic die 640, and the second structure 520 and the logic die 540 are in electrical contact via the third microbump 624. A second interconnect structure 629 is included in the second die 621, the second interconnect structure 629 is in one-to-one correspondence with the third microbumps 624, thereby electrically contacting the logic die 640 with the second die 621. A plurality of third microbumps 624 and second interconnect structures 629 are shown in fig. 6, and the number of third microbumps 624 and second interconnect structures 629 is not a limitation of the present invention.
As shown with reference to fig. 6, a substrate 650 may also be included below the logic die 640. The substrate 650 is in electrical contact with the logic die 640 via a plurality of microbumps 641, 643. A plurality of third interconnect structures 642, 644 may be included in the logic die 640, and the plurality of third interconnect structures 642, 644 may be connected to the second microbumps 614, 624 on a top surface of the logic die 640 and to a portion of the plurality of microbumps 641, 643 on a bottom surface of the logic die 640.
In some embodiments, a portion of the second microbumps 614 corresponds to a portion of the third interconnect structure 642 and a portion of the third microbumps 624 corresponds to a portion of the third interconnect structure 644.
The third interconnect structures 642, 644 may be through-silicon vias that extend through the logic die 640, and the substrate 650 and the first structure 610 above the logic die 640 may be electrically connected by the microbumps 641 and the third interconnect structure 642, and the substrate 650 and the second structure 620 above the logic die 640 may be electrically connected by the microbumps 643 and the third interconnect structure 644. The present invention is not limited to the specific embodiment of the substrate 650, and a PCB substrate, a flexible substrate, or the like may be used.
Referring to fig. 6, the height of the die stack structure formed by the plurality of first dies 611 along the second direction D2 is equal to the height of the die stack structure formed by the plurality of second dies 621 along the second direction D2.
According to the semiconductor structure shown in fig. 6, the first structure 610 with the die stack structure and the second structure 620 with the die stack structure are electrically connected through the first side wall 612 and the second side wall 622, so that the distance between the first structure 610 and the second structure 620 is shortened, the interconnection performance of the device is improved, and the consumption of silicon wafer materials is reduced.
Fig. 7 is a schematic diagram of a semiconductor structure according to an embodiment of the invention. Referring to fig. 7, the semiconductor structure includes a first structure 710 and a second structure 720. The first structure 710 includes a first die 711 having a first sidewall 712 extending along a second direction D2. The second structure 720 includes two second dies 721. The first structure 710 and the second structure 720 are in electrical contact at the first sidewall 712.
The present invention is not limited to the specific embodiment in which the first structure 710 and the second structure 720 are electrically contacted. The electrical contact may be made by metal wire bonding between the dies, bonding, etc.
In some embodiments, the second structure includes one or more second die extending along the second direction D2.
In the embodiment shown in fig. 7, the second structure 720 includes at least one second die 721 extending along the second direction D2. In contrast to the embodiment of fig. 4-6, the second die 721 in the embodiment of fig. 7 is in a vertically positioned state, the second die 721 comprising second sidewalls 722 extending in a second direction D2. A first microbump 730 is included between the first sidewall 712 and the second sidewall 722, and the first structure 710 and the second structure 720 are electrically contacted via the first microbump 730.
Referring to fig. 7, the second structure 720 includes two second dies 721, where the two second dies 721 are respectively located on two opposite sides of the first die 711, and are electrically contacted with the first sidewall 712 of the first die 711 through the first micro bumps 730. In other embodiments, the second structure 720 may include only one second die 721, electrically contacting one first sidewall 712 of the first die 711 via the second microbumps 730.
It is understood that the first die 711 in a rectangular parallelepiped structure includes four sidewalls, and all of the four sidewalls are in electrical contact with one second die respectively, that is, there are four second dies all around the first die, and the first micro bumps are included between the four sidewalls of the first die and the second sidewalls of the four second dies. Fig. 7 is not intended to limit the number of first microbumps 730.
Referring to fig. 7, in some embodiments, the semiconductor structure of the present invention further includes a logic die 740, the logic die 740 being located under the first structure 710 and the second structure 720 along the second direction D2 and being in electrical contact with the first structure 710. As shown in fig. 7, the length of the logic die 740 in the first direction D1 is greater than the sum of the lengths of the first structure 710 and the second structure 720 in the first direction D1, so that the logic die 740 can carry both the first structure 710 and the second structure 720.
The present invention is not limited as to the manner in which the logic die 740 is in electrical contact with the first structure 710. In some embodiments, a plurality of second micro bumps 714 are included on the first bottom surface 713 of the first structure 710 adjacent to the logic die 740, and a first interconnect structure 715 is included in the first die 711, the first interconnect structure 715 and the second micro bumps 714 corresponding in a one-to-one manner, such that the logic die 740 is in electrical contact with the first die 711. A plurality of second microbumps 714 and first interconnect structures 715 are shown in fig. 7, and the number of second microbumps 714 and first interconnect structures 715 is not a limitation of the present invention.
In the embodiment shown in fig. 7, the second die 721 includes a second bottom surface 723 that abuts the logic die 740. A third microbump 760 is included between the second bottom surface 723 and the logic die 740, and the second structure 720 and the logic die 740 are in electrical contact via the third microbump 760. Some interconnect structures may also be included in the second die 721 corresponding to the first microbumps 730 and/or the third microbumps 760, not shown.
Referring to fig. 7, a substrate 750 may also be included under the logic die 740. The substrate 750 is electrically connected to the logic die 740 by a plurality of microbumps 741, 743. A plurality of third interconnect structures 742, 744 may be included in the logic die 740, and the plurality of third interconnect structures 742, 744 may be connected to the second microbumps 714, the third microbumps 760 on a top surface of the logic die 740, and to a portion of the plurality of microbumps 741, 743 on a bottom surface of the logic die 740.
In some embodiments, a portion of the second microbumps 714 correspond to a portion of the third interconnect structure 742, and a portion of the third microbumps 760 correspond to a portion of the third interconnect structure 744.
The third interconnect structures 742, 744 may be through-silicon vias that extend through the logic die 740, and the substrate 750 and the first structure 710 above the logic die 740 may be electrically connected by the microbumps 741 and the third interconnect structure 742, and the substrate 750 and the second structure 720 above the logic die 740 may be electrically connected by the microbumps 743 and the third interconnect structure 744. The embodiment of the substrate 750 is not limited in the present invention, and a PCB substrate, a flexible substrate, or the like may be used.
Fig. 8 is a schematic diagram of a semiconductor structure according to an embodiment of the invention. Referring to fig. 8, the first structure 810 in the semiconductor structure of this embodiment includes a plurality of first dies 811 therein, the plurality of first dies 811 being stacked along the second direction D2 to form a die stack structure, each of the first dies 811 having a first sidewall 812 extending along the second direction D2.
Similar to the embodiments shown in fig. 5 and 6, hybrid bonding may be used between the first dies 811, or through microbumps and through-silicon vias.
In some embodiments, each of the plurality of first dies 811 includes a first bonding layer including a plurality of conductive contacts and a dielectric layer, and the plurality of first dies 811 are hybrid bonded together by the first bonding layer. It is to be understood that the plurality of first dies 811 are stacked along the second direction D2, and therefore, the first bonding layers of two adjacent first dies 811 should be located at the face where the two first dies 811 are bonded to each other. For the first die 811 located at the top level, the first bonding layer is located at the bottom surface of the first die 811; for the first die 811 located at the bottom layer, the first bonding layer is located at the top surface of the first die 811; for the first die 811 located in the middle, there is one first bonding layer on each of its bottom and top surfaces, i.e. there are two first bonding layers in total.
In some embodiments, the first interconnect structure 816 is further included throughout the stacked plurality of first dies 811, and the fourth micro bump is located between adjacent first dies 811, the fourth micro bump corresponding to the position of the first interconnect structure 816, and the plurality of first dies 811 are in electrical contact with each other through the first interconnect structure 816 and the fourth micro bump. As shown in fig. 8, four first dies 811 are stacked along the second direction D2, wherein, taking the second first die 811 from top to bottom as an example, the first die 811 includes a first interconnect structure 816 penetrating through the first die 811, and the first interconnect structure 816 can be a through-silicon via. The upper and lower surfaces of the first die 811 further include fourth micro bumps 815, 817 corresponding to the first interconnect structures 816, and the fourth micro bumps 815, 817 are in one-to-one correspondence with the first interconnect structures 816, so that the first die 811 is electrically connected to other first dies 811 located above and below the first die 811.
As shown in fig. 8, an interconnect structure 818 may be included in the first die 811 that is positioned at the topmost layer in the die stack structure. The interconnect structure 818 may not extend through the first die 811.
In the embodiment shown in fig. 8, a first micro bump 830 is provided between the second sidewall 822 of the two second dies 821 and the first sidewall 812 of each first die 811, and the second dies 821 are electrically contacted with the plurality of first dies 811 through the first micro bumps 830. For embodiments including one or more second dies 821, there is a first microbump 830 between the second sidewall 822 of the one or more second dies 821 and the first sidewall 812 of each first die 811. In an embodiment, four second dies 821 surround the die stack structure formed by the plurality of first dies 811 to form a fence shape.
Referring to fig. 8, in some embodiments, the semiconductor structure of the present invention further includes a logic die 840, the logic die 840 being located below the first structure 810 and the second structure 820 along the second direction D2 and being in electrical contact with the first structure 810. As shown in fig. 8, the length of the logic die 840 in the first direction D1 is greater than the sum of the lengths of the first structure 810 and the second structure 820 in the first direction D1 so that the logic die 840 can carry both the first structure 810 and the second structure 820.
The present invention is not limited as to the manner in which the logic die 840 is in electrical contact with the first structure 810. In some embodiments, a plurality of second micro bumps 814 are included on the first bottom surface 813 of the first structure 810 adjacent to the logic die 840, and a first interconnect structure 819 is included in the first die 811, the first interconnect structure 819 corresponding one-to-one to the second micro bumps 814, thereby electrically contacting the logic die 840 to the first die 811. A plurality of second microbumps 814 and first interconnect structures 819 are shown in fig. 8, and the number of second microbumps 814 and first interconnect structures 819 is not limited by the invention.
In the embodiment shown in fig. 8, the second die 821 includes a second bottom surface 823 that abuts the logic die 840. A third microbump 860 is included between second bottom surface 823 and logic die 840, and second structure 820 and logic die 840 are in electrical contact via third microbump 860. Some interconnect structures may also be included in the second die 821 corresponding to the first and/or third microbumps 830 and 860, not shown in the figure.
Referring to fig. 8, a substrate 850 may also be included under the logic die 840. The substrate 850 is electrically connected to the logic die 840 by a plurality of microbumps 841, 843. A plurality of third interconnect structures 842, 844 may be included in the logic die 840, and the plurality of third interconnect structures 842, 844 may be coupled to the second microbumps 814, the third microbumps 860 on a top surface of the logic die 840 and to a portion of the plurality of microbumps 841, 843 on a bottom surface of the logic die 840.
In some embodiments, a portion of the second microbumps 814 corresponds to a portion of the third interconnect structure 842, and a portion of the third microbumps 860 corresponds to a portion of the third interconnect structure 844.
The third interconnect structures 842, 844 may be through-silicon vias that extend through the logic die 840, and the substrate 850 may be electrically connected to the first structure 810 above the logic die 840 by the microbumps 841 and the third interconnect structures 842, and the substrate 850 may be electrically connected to the second structure 820 above the logic die 840 by the microbumps 843 and the third interconnect structures 844. The embodiment of the substrate 850 is not limited in the present invention, and a PCB substrate, a flexible substrate, or the like may be used.
Referring to fig. 8, the height of the second die 821 in the second direction D2 is equal to the height of a die stack structure formed by the plurality of first dies 811 in the second direction D2.
Fig. 9 is a schematic diagram of a semiconductor structure according to an embodiment of the invention. Referring to fig. 9, this embodiment is based on the embodiment shown in fig. 8, and the second structure 920 includes a plurality of second dies 921 stacked along the first direction D1. The first structure 910 in the embodiment shown in fig. 9 is the same as the first structure 810 in the embodiment shown in fig. 8 and is not expanded here. The description of the first structure 810 in fig. 8 can be used to describe the first structure 910 in fig. 9.
Referring to fig. 9, the second structure 920 includes second structures 920a and 920b respectively disposed on two sides of the first structure 910, and the two-part structure is symmetrical, and the second structure 920a is taken as an example for illustration.
Referring to fig. 9, two second dies 921 are stacked in the first direction D1. Fig. 9 is not intended to limit the specific number of second dies 921.
In some embodiments, each of the plurality of second dies 921 includes a second bonding layer including a plurality of conductive contacts and a dielectric layer, the plurality of second dies 921 being hybrid bonded therebetween by the second bonding layer.
In some embodiments, the second interconnect structures 924 are further included, which extend through the stacked plurality of second dies 921, and fifth micro bumps are disposed between the adjacent second dies 921, the fifth micro bumps corresponding to the positions of the second interconnect structures 924, and the plurality of second dies 921 are in electrical contact with each other through the second interconnect structures 924 and the fifth micro bumps. As shown in fig. 9, two second dies 921 are stacked along the first direction D1, wherein the second sidewall 922 of the second die 921 near the first structure 910 is electrically contacted with the first sidewall 912 of each first die 911 in the first structures 910 through the first micro bumps 930. The second die 921 includes a second interconnect structure 924 extending through the second die 921, the second interconnect structure 924 can be a through silicon via. The second die 921 and the adjacent second die 921 further include a fifth micro bump 925 corresponding to the second interconnect structure 924, and the two adjacent second dies 921 are electrically connected by the second interconnect structure 924 and the fifth micro bump 925. An interconnect structure 926 may be included in the leftmost second die 921 in the second structure 920a, and the interconnect structure 926 may not extend through the second die 921.
Referring to fig. 9, a logic die 940 and a substrate 950 are also included in this embodiment. The first bottom surface 913 of the first structure 910 is electrically connected to the logic die 940 via the second microbumps 914; the second bottom surface 923 of the second structure 920 is electrically connected to the logic die 940 via the third microbumps 960. A plurality of third interconnect structures 942, 944 may be included in logic die 940, and the plurality of third interconnect structures 942, 944 may be connected to the second microbumps 914, the third microbumps 960 on a top surface of logic die 640 and to a portion of the plurality of microbumps 641, 643 on a bottom surface of logic die 640.
In some embodiments, a portion of the second microbumps 914 corresponds to a portion of the third interconnect structure 942, and a portion of the third microbumps 960 corresponds to a portion of the third interconnect structure 944.
The third interconnect structures 942, 944 may be through-silicon vias that extend through the logic die 940, and the substrate 950 and the first structure 910 above the logic die 940 may be electrically connected by the microbumps 941 and the third interconnect structure 942, and the substrate 950 and the second structure 920 above the logic die 940 may be electrically connected by the microbumps 943 and the third interconnect structure 944.
The logic die 940 and the substrate 950 are similar to the logic die 840 and the substrate 850 shown in fig. 8, and the related descriptions are also applicable to the embodiment shown in fig. 9 and will not be further expanded.
In some embodiments, the second structures 920 may not be symmetrically distributed around the first structure 910. One or more second dies may optionally be disposed around the first structure 910 in an electrical contact relationship with the first sidewall of the first die.
Referring to fig. 9, the heights of the plurality of second dies 921 along the second direction D2 are all equal, and overall, the height of the second structure 920 along the second direction D2 is equal to the height of the die stack structure formed by the plurality of first dies 911 along the second direction D2.
In the embodiments shown in fig. 7-9, the first die may be a core die and the second die may be a core die, a buffer die, or external test circuitry, etc. The logic die may include a buffer die, a controller die, and the like.
The interconnect structure described hereinabove may be a through silicon via, which may be filled with a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, silicide, or any combination thereof. The microbumps and conductive contacts described above may comprise conductive materials including, but not limited to, tungsten, cobalt, copper, aluminum, silicide, or any combination thereof. The materials of the dielectric layers described above may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.
According to the embodiments shown in fig. 7-9, the die stack structure formed by one or more vertically placed second dies and one or more first dies is electrically connected through the second micro bumps, which is beneficial to the stress balance of the whole device, ensures the bonding strength, shortens the distance between the dies, and reduces the consumption of wafer materials.
Fig. 10 is an exemplary flow chart of a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention. This manufacturing method can be used to manufacture the semiconductor structure described above, and therefore, the method for manufacturing the semiconductor structure of this embodiment can be described with reference to fig. 4 to 9. Referring to fig. 10, the manufacturing method of this embodiment includes the steps of:
step 1010: a first wafer is provided, including a first structure including a number of first dies extending along a first direction, the first dies having first sidewalls extending along a thickness direction of the first dies.
The first direction and the second direction in this step are the same as the first direction D1 and the second direction D2 in fig. 4-9, respectively. The first die may be any of the first die in the embodiments shown in fig. 4-9.
In some embodiments, the first structure includes a plurality of first dies stacked in a second direction perpendicular to the first direction. In these embodiments, the manufacturing method further comprises: forming a first bonding layer in each of the plurality of first dies, the first bonding layer including a plurality of first conductive contacts and a first dielectric layer; the plurality of first dies are hybrid bonded by a first bonding layer.
In some embodiments, the plurality of first dies are bonded to each other through microbumps and through silicon vias. In these embodiments, the steps further comprise: the method comprises the steps of forming a first interconnection structure penetrating through a plurality of stacked first dies and forming a fourth micro bump between the adjacent first dies, wherein the fourth micro bump corresponds to the position of the first interconnection structure, and the plurality of first dies are electrically connected with each other through the first interconnection structure and the fourth micro bump.
In some embodiments, further comprising forming contact regions through the number of first dies, the contact regions comprising trenches and/or vias.
Step 1020: a second wafer is provided that includes a second structure that includes a number of second dies.
The second die in this step may be any of the second die in the embodiments shown in fig. 4-9.
In some embodiments, a plurality of second dies is included in the second structure, and a plurality of first dies is stacked in a second direction perpendicular to the first direction.
In some embodiments, a plurality of second dies is included in the second structure, and a plurality of first dies is stacked along the first direction.
In these embodiments, the manufacturing method further comprises: forming a second bonding layer in each of the plurality of second dies, the second bonding layer including a plurality of second conductive contacts and a second dielectric layer; the plurality of second dies are hybrid bonded by a second bonding layer.
In some embodiments, the plurality of second dies are bonded between each other by microbumps and through-silicon vias. In these embodiments, the steps further comprise: and forming a second interconnection structure penetrating through the plurality of second dies and forming a fifth micro bump between the adjacent second dies, wherein the fifth micro bump corresponds to the position of the second interconnection structure, and the plurality of second dies are electrically connected with each other through the second interconnection structure and the fifth micro bump.
In some embodiments, forming contact regions through the plurality of second dies, the contact regions including trenches and/or vias, is also included.
Step 1030: and bonding the first wafer and the second wafer to enable the second structure to be located on one side of the first structure in the first direction, and enabling the first structure and the second structure to be in electrical contact at the first side wall.
Various bonding methods known in the art may be used to bond the first wafer and the second wafer.
In some embodiments, the second structure includes a second sidewall adjacent to the first structure, a first microbump is formed between the second sidewall and the first sidewall, and the first structure and the second structure are electrically contacted through the first microbump.
According to the semiconductor structure, the semiconductor structure can be formed by forming the micro bumps on the first sidewall and the second sidewall respectively, and fusing the two micro bumps into one after bonding.
In some embodiments, in conjunction with the embodiments illustrated in fig. 4-9, the step of bonding the first sidewall and the second die comprises:
forming a first sub-micro bump on the first side wall;
forming a second sub-micro bump on the second side wall;
and bonding the first sub-micro-bump and the second sub-micro-bump to enable the first side wall to be electrically contacted with the second side wall, and forming the first micro-bump after the first sub-micro-bump and the second sub-micro-bump are bonded.
In some embodiments, the manufacturing method of the present invention may further include the steps of:
providing a third wafer comprising logic dies extending along a first direction;
and bonding the third wafer and the first wafer to electrically connect the logic die with the first die of the first structure.
In some embodiments, the manufacturing method of the present invention may further include:
and bonding the third wafer and the second wafer to electrically connect the logic die with the second die of the second structure.
In some embodiments, the third wafer is bonded to both the first wafer and the second wafer, thereby electrically connecting the logic die to both the first structure and the second structure. For embodiments of forming a semiconductor structure including a logic die, the method of manufacturing may further include:
the first structure comprises a first bottom surface adjacent to the logic die, a second micro bump is formed between the first bottom surface and the top surface of the logic die, and the logic die is electrically contacted with the first structure through the second micro bump; and/or the second structure comprises a second bottom surface adjacent to the logic die, a third micro bump is formed between the second bottom surface and the top surface of the logic die, and the logic die and the second structure are electrically contacted through the third micro bump.
In these embodiments, the manufacturing method may further include: a plurality of third interconnect structures are formed through the logic die, portions of the second micro-bumps corresponding to portions of the plurality of third interconnect structures, and portions of the third micro-bumps corresponding to portions of the third interconnect structures.
The method for manufacturing a semiconductor structure according to the present invention may form the semiconductor structure described above, and the semiconductor structure may form a stacked structure not only in the second direction D2 but also in the first direction D1. Therefore, the problem caused by excessive stacking layers in the second direction D2(Z axis) can be relieved, the stress of the semiconductor device is balanced, the bonding strength between wafers is ensured, the distance between the devices is shortened, the interconnection performance of the devices is improved, and the consumption of silicon wafer materials is reduced.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims (20)

1. A semiconductor structure, comprising:
a first structure comprising a number of first dies extending in a first direction, the first dies having first sidewalls extending in a thickness direction of the first dies;
a second structure located on one side of the first structure in the first direction, the second structure comprising a number of second dies; and
the first structure and the second structure are in electrical contact at the first sidewall.
2. The semiconductor structure of claim 1, wherein the second structure comprises a second sidewall adjacent to the first structure, a first microbump between the second sidewall and the first sidewall, the first structure and the second structure being in electrical contact through the first microbump.
3. The semiconductor structure of claim 1, wherein the first structure comprises a plurality of the first dies stacked in a second direction perpendicular to the first direction; and/or the presence of a gas in the gas,
the second structure includes a plurality of the second dies stacked in a second direction perpendicular to the first direction.
4. The semiconductor structure of claim 1, wherein the first structure comprises a plurality of the first dies stacked in a second direction perpendicular to the first direction; and/or the presence of a gas in the gas,
the second structure includes one or more second dies extending in a second direction perpendicular to the first direction, a plurality of the second dies being stacked in the first direction.
5. The semiconductor structure of any one of claims 1-4, further comprising: a logic die, the first structure and the second structure being located above the logic die;
the logic die is electrically connected with the first die of the first structure; and/or the presence of a gas in the gas,
the logic die is electrically connected to the second die of the second structure.
6. The semiconductor structure of claim 3 or 4, wherein each of the plurality of first dies comprises a first bonding layer comprising a plurality of conductive contacts and a dielectric layer, the plurality of first dies being hybrid bonded therebetween by the first bonding layer; and/or the presence of a gas in the gas,
each of the plurality of second dies comprises a second bonding layer, the second bonding layer comprises a plurality of conductive contacts and a dielectric layer, and the plurality of second dies are mixed and bonded through the second bonding layer.
7. The semiconductor structure of claim 3 or 4, further comprising a first interconnect structure extending through a stacked plurality of the first dies and a fourth microbump located between adjacent ones of the first dies, the fourth microbump corresponding to a location of the first interconnect structure, the plurality of first dies being electrically connected to each other through the first interconnect structure and the fourth microbump; and/or
The second die further comprises a plurality of second interconnection structures penetrating through the stacked second dies and fifth micro bumps positioned between the adjacent second dies, the positions of the fifth micro bumps correspond to those of the second interconnection structures, and the plurality of second dies are electrically connected with each other through the second interconnection structures and the fifth micro bumps.
8. The semiconductor structure of claim 5, wherein the first structure includes a first bottom surface adjacent the logic die, including a second microbump between the first bottom surface and a top surface of the logic die, the logic die and the first structure being in electrical contact through the second microbump; and/or the presence of a gas in the gas,
the second structure comprises a second bottom surface adjacent to the logic die, a third micro bump is arranged between the second bottom surface and the top surface of the logic die, and the logic die and the second structure are electrically contacted through the third micro bump.
9. The semiconductor structure of claim 8, further comprising a plurality of third interconnect structures extending through the logic die, portions of the second micro-bumps corresponding to portions of the plurality of third interconnect structures, and portions of the third micro-bumps corresponding to portions of the third interconnect structures.
10. The semiconductor structure of claim 1, further comprising contact regions extending through the number of first dies, the contact regions comprising trenches and/or vias.
11. A method of fabricating a semiconductor structure, comprising:
providing a first wafer comprising a first structure comprising a number of first dies extending along a first direction, the first dies having first sidewalls extending along a thickness direction of the first dies;
providing a second wafer comprising a second structure, wherein the second structure comprises a plurality of second dies; and
and bonding the first wafer and the second wafer to enable the second structure to be located on one side of the first structure in the first direction, and enabling the first structure and the second structure to be in electrical contact at the first side wall.
12. The method of manufacturing of claim 11, further comprising: the second structure comprises a second side wall adjacent to the first structure, a first micro bump is formed between the second side wall and the first side wall, and the first structure is electrically contacted with the second structure through the first micro bump.
13. The method of manufacturing of claim 11, wherein the first structure comprises a plurality of first dies stacked in a second direction perpendicular to the first direction; and/or the presence of a gas in the gas,
the second structure includes a plurality of second dies stacked in a second direction perpendicular to the first direction.
14. The method of manufacturing of claim 11, wherein the first structure comprises a plurality of first dies stacked in a second direction perpendicular to the first direction; and/or the presence of a gas in the gas,
the second structure includes one or more second dies extending in a second direction perpendicular to the first direction, a plurality of the second dies being stacked in the first direction.
15. The manufacturing method according to any one of claims 11 to 14, further comprising:
providing a third wafer comprising logic dies;
bonding the third wafer and the first wafer to electrically connect the logic die with the first die of the first structure; and/or the presence of a gas in the gas,
and bonding the third wafer and the second wafer to electrically connect the logic die with the second die of the second structure.
16. The manufacturing method according to claim 13 or 14, further comprising:
each of the plurality of first dies comprises a first bonding layer, the first bonding layer comprises a plurality of conductive contacts and a dielectric layer, and the plurality of first dies are mixedly bonded through the first bonding layer; and/or the presence of a gas in the gas,
each of the plurality of second dies includes a second bonding layer including a plurality of conductive contacts and a dielectric layer, the plurality of second dies being hybrid bonded by the second bonding layer.
17. The manufacturing method according to claim 13 or 14, further comprising:
forming a first interconnection structure penetrating through a plurality of stacked first dies and forming a fourth micro bump between the adjacent first dies, wherein the position of the fourth micro bump corresponds to the position of the first interconnection structure, and the plurality of first dies are electrically connected with each other through the first interconnection structure and the fourth micro bump; and/or
Forming a second interconnection structure penetrating through the stacked second dies and forming a fifth micro bump between the adjacent second dies, wherein the fifth micro bump corresponds to the position of the second interconnection structure, and the second dies are electrically connected with each other through the second interconnection structure and the fifth micro bump.
18. The method of manufacturing of claim 15, further comprising:
the first structure comprises a first bottom surface adjacent to the logic die, a second micro bump is formed between the first bottom surface and the top surface of the logic die, and the logic die and the first structure are electrically contacted through the second micro bump; and/or the presence of a gas in the gas,
the second structure comprises a second bottom surface adjacent to the logic die, a third micro bump is formed between the second bottom surface and the top surface of the logic die, and the logic die is electrically contacted with the second structure through the third micro bump.
19. The method of manufacturing of claim 18, further comprising: forming a plurality of third interconnect structures through the logic die, portions of the second micro-bumps corresponding to portions of the plurality of third interconnect structures, and portions of the third micro-bumps corresponding to portions of the third interconnect structures.
20. The method of manufacturing of claim 11, further comprising: forming contact regions through the number of first dies, the contact regions including trenches and/or vias.
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