CN112005499A

CN112005499A - Decoding method and device of LDPC code

Info

Publication number: CN112005499A
Application number: CN201880092688.7A
Authority: CN
Inventors: 唐成君; 郑晨; 马亮; 魏岳军
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-10-18
Filing date: 2018-10-18
Publication date: 2020-11-27
Anticipated expiration: 2038-10-18
Also published as: WO2020077596A1; CN112005499B

Abstract

A decoding method and device of LDPC code, the receiving end is in the course of iterative decoding to soft value sequence by check matrix of LDPC code, aim at variable node (v)₀，v₁，v₂，v₃，v₄，v₅，v₆，v₇，v₈，v₉) If and only if the variable nodes (v) obtained by two adjacent iterations are updated₀，v₁，v₂，v₃，v₄，v₅，v₆，v₇，v₈，v₉) To check node (c)₀，c₁，c₂，c₃，c₄) When the sign bit of the output information is different, the current variable node (v) is processed by a method of weighting or annealing₀，v₁，v₂，v₃，v₄，v₅，v₆，v₇，v₈，v₉) Sending to check node (c)₀，c₁，c₂，c₃，c₄) The information of the decoder is corrected to reduce the complexity of the decoding process, improve the decoding performance and improve the throughput of the decoder.

Description

Decoding method and device of LDPC code

Technical Field

The embodiment of the invention relates to the field of decoding, in particular to a decoding method and a decoding device of an LDPC code.

Background

A low-density parity-check (LDPC) code is a linear block code with a sparse check matrix proposed by Gallager, i.e., only a few elements in the check matrix are "1" and most elements are "0". By utilizing the sparsity of the check matrix, the decoding complexity is only in linear relation with the code length, and the decoding process is not too complex under the condition of longer code length. Research shows that the LDPC code has the coding performance approaching the Shannon limit.

In the third generation partnership project (3)^rdgeneration partnership project, 3GPP) at Radio Access Network (RAN) conference, LDPC codes have been formally used as fifth generation communication systems (5)^thgeneration mobile communication system, 5G) coding scheme, for example, may be used to enhance the uplink and downlink data channels of a mobile broadband scenario. However, how to decode the LDPC code is an urgent problem to be solved.

Disclosure of Invention

In view of the above, a main objective of the present application is to provide a method and an apparatus for decoding an LDPC code, which are used to solve the problem of poor decoding performance of the LDPC code.

In a first aspect, the present application discloses a decoding method of an LDPC code, comprising: receiving a sequence of soft values; wherein, the soft value sequence carries the information of the information bit sequence; carrying out iterative decoding on the soft value sequence by using a check matrix to obtain an information bit sequence;

wherein the iterative decoding comprises: during the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q'_ji[k]When the sign bits of (a) are different, according to Q_ji[k-1]And Q'_ji[k]Q obtained by weighted summation_ji[k](ii) a At Q_ji[k-1]And Q'_ji[k]In the case of the same sign bit, Q_ji[k]＝Q' _ji[k]. i is the serial number of the check node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is the first information, Q ', sent by the variable node j to the check node i in the k-1 iteration process'_ji[k]The second information is sent to the check node i by the variable node j in the kth iteration process based on the combined normalized deviation minimum sum CNOMS algorithm; and stopping iterative decoding when all check equations corresponding to the check matrix pass the check or the iteration times reach the maximum iteration times.

In summary, during the kth iteration, if and only if Q_ji[k-1]And Q'_ji[k]When the sign bit of the Q is inverted, Q is just inverted_ji[k-1]And Q'_ji[k]The weighted sum is used as the first information sent to the check node i by the variable node j for k times, and the weighting and correction are not required to be carried out every time, so that compared with the traditional decoding method, the method has the advantages that the increased operation complexity is limited, but the performance is obviously improved.

In one possible design, Q is pre-stored prior to the kth iteration_ji[k-1]。

In one possible design, according to Q_ji[k-1]And Q'_ji[k]Q obtained by weighted summation_ji[k]Comprises that：

Q is obtained according to the following formula_ji[k]：

Q _ji[k]＝γ·Q _ji[k-1]+(1-γ)·Q' _ji[k](ii) a Wherein gamma is more than 0 and less than 1.

In a second aspect, the present application provides a decoding method of LDPC, including:

receiving a sequence of soft values; wherein, the soft value sequence carries the information of the information bit sequence;

performing iterative decoding on the soft value sequence according to the check matrix to obtain an information bit sequence;

wherein the iterative decoding comprises: during the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q'_ji[k]According to the normalized correction factor, the offset value correction factor and Q 'when the sign bits are different'_ji[k]Obtained Q_ji[k](ii) a At Q_ji[k-1]And Q'_ji[k]Is in the same sign phase, Q_ji[k]＝Q' _ji[k](ii) a i is the serial number of the check node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is the first information, Q ', sent by the variable node j to the check node i in the k-1 iteration process'_ji[k]The second information is sent to the check node i by the variable node j in the kth iteration process based on the combined normalized deviation minimum sum CNOMS algorithm; and stopping iterative decoding when all check equations corresponding to the check matrix pass the check or the iteration times reach the maximum iteration times. The normalized correction factor is a constant greater than or equal to 1 and the offset correction factor is a constant greater than 0.

During the kth iteration, when Q is_ji[k-1]And Q'_ji[k]Is turned over to Q'_ji[k]Annealing is carried out to serve as the first information sent to the check node i by the variable node j for k times, and the first information does not need to be sent to the check node i every timeAnd the line annealing correction is performed, so that the operation complexity of iterative decoding is reduced. At the same time, only Q needs to be stored_jiThe sign bit of (c). Therefore, compared with the traditional decoding method, the method has the advantages of increased operation complexity and storage space requirement, but obvious performance improvement.

In one possible design, Q is pre-stored prior to the kth iteration_ji[k-1]The sign bit of (c).

In one possible design, the iterative decoding further includes:

q is obtained according to the following formula_ji[k]：

α·sgn(Q' _ji[k])·max{|Q' _ji[k]|-β,0}；

Wherein alpha is a normalization correction factor, beta is an offset value correction factor, sgn is a sign bit operation, max is a maximum value operation, alpha is less than or equal to 1, and beta is more than 0.

In one possible embodiment, the comparison Q is characterized by_ji[k-1]And Q'_ji[k]The sign bit of (a) includes:

at Q_ji[k-1]And Q'_ji[k]When the product of (A) is greater than or equal to 0, Q is determined_ji[k-1]And Q'_ji[k]The sign bits of (a) are the same; or

At Q_ji[k-1]And Q'_ji[k]When the product of (A) is less than 0, Q is determined_ji[k-1]And Q'_ji[k]Are not the same.

In one possible design, the iterative process further includes: q 'is calculated according to the formula'_ji[k]：

Wherein alpha 'is a normalized correction factor, beta' is an offset value correction factor, alpha 'is less than or equal to 1, beta' is more than 0, min is a minimum value solving operation, max is a maximum value solving operation, and V (i) \ j represents the variable nodes connected with the check node i except the variable node j; lambda [ alpha ]_jIs the jth soft value in the sequence of soft values; c (j) \\ i represents a set of the remaining check nodes connected to variable node j except check node i.

In one possible design, a layered decoding algorithm is used for iterative decoding. The convergence rate of iterative decoding can be improved by adopting a layered decoding method.

In another aspect, an embodiment of the present invention provides an apparatus (abbreviated as an apparatus) for decoding an LDPC code, where the apparatus is used for the functions of the methods in the first aspect. The functions may be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions.

In one possible design, the apparatus may be a terminal device or a network device, and the apparatus includes a processor and a transmitter, where the processor is configured to perform iterative decoding on the soft value sequence by using a check matrix to obtain an information bit sequence;

wherein the iterative decoding comprises: during the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q'_ji[k]When the sign bits of (a) are different, according to Q_ji[k-1]And Q'_ji[k]Q obtained by weighted summation_ji[k](ii) a At Q_ji[k-1]And Q'_ji[k]In the case of the same sign bit, Q_ji[k]＝Q _ji[k]. i is the serial number of the check node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is the first information, Q ', sent by the variable node j to the check node i in the k-1 iteration process'_ji[k]Based on the joint normalized offset minimum sum CNOMS algorithmObtaining second information which is sent to a check node i by the variable node j in the kth iteration process; and stopping iterative decoding when all check equations corresponding to the check matrix pass the check or the iteration times reach the maximum iteration times. The transmitter is used for receiving the soft value sequence; wherein the soft value sequence carries information of the information bit sequence. The apparatus may also include a memory for coupling with the processor that holds the necessary program instructions and data.

In still another aspect, an embodiment of the present invention provides an apparatus for decoding an LDPC code, where the apparatus has functions of implementing the methods in the second aspect. The functions may be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions. The modules may be software and/or hardware.

In one possible design, the apparatus may be a terminal device or a network device, and the apparatus includes a receiver configured to receive a soft value sequence and a processor; wherein the soft value sequence carries information of the information bit sequence. The processor is configured to perform iterative decoding on the soft value sequence according to the check matrix to obtain an information bit sequence;

wherein the iterative decoding comprises: during the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q'_ji[k]According to the normalized correction factor, the offset value correction factor and Q 'when the sign bits are different'_ji[k]Obtained Q_ji[k](ii) a At Q_ji[k-1]And Q'_ji[k]Is in the same sign phase, Q_ji[k]＝Q' _ji[k](ii) a i is the serial number of the check node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is the first information, Q ', sent by the variable node j to the check node i in the k-1 iteration process'_ji[k]Is a variable obtained based on a combined normalized deviation minimum sum CNOMS algorithm in the k iteration processThe node j sends second information to the check node i; and stopping iterative decoding when all check equations corresponding to the check matrix pass the check or the iteration times reach the maximum iteration times.

A further aspect of the present application provides a computer storage medium comprising instructions which, when executed on a computer, cause the computer to perform the method as set forth in any one of the various possible implementations of the first aspect to the first aspect.

A further aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method according to any of the various possible embodiments of the first aspect to the first aspect.

A further aspect of the present application provides a computer storage medium comprising instructions which, when run on a computer, cause the computer to perform a method as set forth in any one of the various possible embodiments of the second aspect to the second aspect.

A further aspect of the present application is a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method according to any one of the various possible embodiments of the second aspect to the second aspect.

Drawings

FIG. 1 is a network architecture diagram of an embodiment of the present invention;

FIG. 2 is a schematic diagram of a check matrix of an LDPC code according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a Tanner graph corresponding to the check matrix of FIG. 2;

FIG. 4 is a schematic diagram of a base graph matrix provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of another base map matrix provided by an embodiment of the present invention;

FIG. 6 is a partial diagram of an offset matrix according to an embodiment of the present invention;

fig. 7 is a diagram illustrating a correspondence relationship between a type of a base map matrix and a code rate and a length of a transport block according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a layered decoding algorithm provided by an embodiment of the present invention;

FIG. 9 is a flowchart illustrating a decoding method of an LDPC code according to an embodiment of the present invention;

FIG. 10 is a graph of decoding performance of various decoding algorithms provided by embodiments of the present invention;

FIG. 11 is a schematic structural diagram of an apparatus provided by an embodiment of the present invention;

fig. 12 is another schematic structural diagram of the apparatus according to the embodiment of the present invention.

Detailed Description

Specific embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The embodiment of the present application may be applied to a wireless communication system, as shown in fig. 1, the wireless communication system generally includes cells, each cell includes a Base Station (BS), the base station provides a communication service to a User Equipment (UE), and the base station is connected to a core network device. The number and form of each device in the communication system of fig. 1 are only for illustration and are not intended to limit the present application.

It should be noted that, the wireless communication system related to the embodiment of the present application includes but is not limited to: a global system for mobile communication (GSM), a Code Division Multiple Access (CDMA) system, a Wideband Code Division Multiple Access (WCDMA) system, a Worldwide Interoperability for Microwave Access (WiMAX) system, a Long Term Evolution (LTE) system, a 5G communication system (e.g., a New Radio (NR)) system, a communication system in which multiple communication technologies are combined (e.g., a communication system in which LTE technology and NR technology are combined), or a communication system in which subsequent evolution progresses.

The UE designed in the embodiments of the present application is a device with a wireless communication function, and may be a handheld device with a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem. The terminal devices in different networks may be called different names, for example: user equipment, access terminal, subscriber unit, subscriber station, mobile station, remote terminal, mobile device, user terminal, Wireless communication device, user agent or user equipment, cellular telephone, cordless telephone, Session Initiation Protocol (SIP) telephone, Wireless Local Loop (WLL) station, Personal Digital Assistant (PDA), terminal equipment in a 5G network or future evolution network, and the like. For convenience of description, in all embodiments of the present application, the above-mentioned devices are collectively referred to as terminal devices.

The base station in the embodiment of the present application may also be referred to as a base station device, and is a device deployed in a radio access network to provide a wireless communication function, including but not limited to: a Base Station (e.g., BTS (Base Transceiver Station, BTS), a Node B (NodeB, NB), an evolved Node B (eNB or eNodeB), a transmission Node or a transmission reception point (TRP or TP) or a next generation Node B (gNB) in an NR system, a Base Station or a network device in a future communication network), a relay Station, an access point, a vehicle-mounted device, a wearable device, a Wireless Fidelity (Wi-Fi) Station, a Wireless backhaul Node, a small Station, a micro Station, and so on. For convenience of description, in all embodiments of the present application, the above-mentioned apparatus for providing a UE with a wireless communication function is collectively referred to as a network device.

The properties of the LDPC code are briefly described below:

the LDPC code is a (n, k) linear block code, n is the code length, k is the information sequence length, the check matrix of the LDPC code is a sparse matrix, only a few elements '1' exist in the check matrix, and most elements '0' exist in the check matrix. The check matrix corresponds to a Tanner graph, check nodes in the Tanner graph correspond to one row in the check matrix, the variable nodes correspond to one column in the check matrix, and each edge connecting the check nodes and the variable nodes represents that a non-zero element exists at the intersection position of the row and the column corresponding to the two nodes. For example: the check matrix H shown in fig. 2, and the corresponding check equation. Check matrix

Wherein, weaveThe bit sequence after the code is v ═ v (v)₁,v ₂,...,v ₉) The constraint condition is that Hv is 0, c₀～c ₄Is the 5 check equations of the check matrix H.

Fig. 3 shows a Tanner graph corresponding to the check matrix in fig. 2, where the circular nodes in fig. 3 are variable nodes, and 9 variable nodes respectively correspond to one column in the check matrix H; the square nodes are check nodes, 5 check nodes respectively correspond to one row in the check matrix H, and each edge connecting the check node and the variable node indicates that a non-zero element exists at the intersection of the row and the column corresponding to the two nodes, for example: the check node 0 is connected to the variable nodes 0 to 3, respectively, and indicates that the elements in the 0 th to 4 th columns of the 0 th row are "1".

In an actual use process, the check matrix is formed by m × n block matrixes, each block matrix includes z × z elements, each block matrix is obtained by circularly shifting a z × z identity matrix, and an LDPC code corresponding to the check matrix is also called a quasi-cyclic (quasi-cyclic) LDPC code.

For example: in a 5G communication system, data is encoded using an LDPC code, a check matrix of the LDPC code is obtained from a base map (BG) matrix and an offset matrix, where the number of elements in the base map matrix is m × n, and when an element in the base map matrix is "0", the LDPC code corresponds to a z × z all-zero matrix. When the element in the basic diagram matrix is "1", the element corresponds to a matrix obtained by circularly shifting a unit matrix of z × z, which is also called a cyclic permutation matrix (cyclic permutation matrix), that is, each element in the basic diagram matrix represents an all-zero matrix or a cyclic permutation matrix. BG1 shown in fig. 4, BG1 has a size of 46 rows and 68 columns, BG2 shown in fig. 5, BG2 has a size of 42 rows and 52 columns, in the base diagram matrix of fig. 4 and 5, row numbers are marked in the leftmost column, column numbers are marked in the uppermost row, only non-zero element "1" is shown in the base diagram matrix, and blank parts are zero elements. Wherein, the 1 st column and the 2 nd column of the base map matrix are built-in perforated columns, and the corresponding bits after coding do not enter the circular buffer.

Referring to fig. 6, a partial schematic diagram of an offset matrix corresponding to BG1 is shown, where elements in the offset matrix are integers, and when an element in the offset matrix is "-1", it represents an all-zero matrix corresponding to z × z; when the element in the offset matrix is "0", it represents the identity matrix corresponding to z × z; and when the elements in the offset value matrix are integers larger than 0, performing integral-time right cyclic shift on the unit matrix of the z multiplied by z correspondingly.

If the element in BG1 at row i and column j is "1", the offset value for the element is P_ij，P _ijIs an integer greater than 0, the element representing the ith row and jth column in BG1 may be represented by P_ijReplacing a corresponding zxz cyclic permutation matrix by performing P on the zxz identity matrix_ijThe minor loop is obtained by shifting to the right. In summary, each element with a value of "0" in BG1 is replaced by an all-zero matrix of z × z, each element with a value of "1" is replaced by a cyclic permutation matrix of z × z corresponding to its offset value, and finally, a check matrix of the LDPC code can be obtained. z is a positive integer, which may also be referred to as a spreading factor, and the value of z is related to the code block size supported by the system and the size of the information data, and it can be seen that the size of the check matrix is (m × z) × (n × z).

For example: the spreading factor z is 4, and the elements in the offset matrix take the cyclic permutation matrices corresponding to-1, 0,1, 2 and 3 respectively as follows:

when the value of an element in the base graph matrix is greater than the expansion factor z, a modulo operation needs to be performed on the element, and the formula is as follows:

P _ij＝mod(V _ij,Z)；

wherein, V_ijIs the value of the element in the ith row and jth column of the base map matrix, z is the spreading factor, P_ijFor the actual offset value, mod (x, y) represents the modulo operation, returning the remainder of x divided by y.

The LDPC coding scheme of two base map matrixes is supported in a 5G communication system, the two base map matrixes are respectively called BG1 and BG2, and different base map matrixes are selected for coding according to different block lengths and code rates. For example: the correspondence between the block length and the code rate and the base map matrix is shown in fig. 7. And when the size of the transmission block to be coded is smaller than or equal to 308, or the size of the transmission block to be coded is smaller than or equal to 3840 and the coding rate is smaller than or equal to 0.67, or the coding rate is smaller than or equal to 0.25, the BG2 is adopted for coding, otherwise, the BG1 is adopted for coding.

Several decoding methods for LDPC codes are briefly described below:

1. a min-sum (MS) decoding algorithm.

Parameter definition: lambda [ alpha ]_jThe jth soft value, also called the likelihood ratio (LLR), representing a sequence of soft values,

P(b _j1) denotes the probability that the bit corresponding to the jth soft value is 1, P (b)_j0) represents the probability that the bit corresponding to the jth soft value is 0, ln represents the base e logarithm operation; each soft value in the sequence of soft values corresponds to a bit and the sequence of soft values corresponds to a sequence of coded bits.

R _ij[k]Information sent from the check node i to the variable node j during the kth iteration is represented;

Q _ji[k]information sent from the variable node j to the check node i when the kth iteration is represented;

Q _j[k]the posterior probability of the variable node j used for hard decision after the kth iteration is finished is shown;

c (j) represents a set of check nodes connected to variable node j;

v (i) represents a set of variable nodes connected to check node i;

i is the serial number of the check node, and the value range of i is 0,1, … and m-1; j is the serial number of the variable node, the value range of j is 0,1, …, n-1, namely the check matrix of the LDPC code has m rows and n columns, a total of m × n elements, and the Tanner graph corresponding to the check matrix has m check nodes and n variable nodes.

First, an initialization step is performed. For i being 0,1, … and m-1, the check node i sends the information R of the variable node j_ij[0]Initialization is 0, where j ∈ V (i).

For j being 0,1, … and n-1, the variable node j sends the information Q of the check node i_ji[0]Initialized to λ_jWherein i ∈ C (j).

Then, iteration steps are carried out, and the check nodes and the variable nodes are alternately updated:

in the k iteration process, the check node i sends the information R of the variable node j_ij[k]The calculation process of (a) is shown in equation 1:

wherein sgn () is a sign bit operation, and the returned result is the positive and negative of a parameter; min () is the minimum operation; v (i) \\ j represents a set of the remaining variable nodes connected to check node i except variable node j. The above update process may also be referred to as an update process of the check node.

In the k iteration process, the variable node j sends information Q of the check node i_ji[k]The calculation process of (2) is shown in equation 2:

where c (j) \\ i represents a set of the remaining check nodes connected to variable node j except check node i.

After the kth iteration is completed, in order to perform hard decision detection, the posterior probability of the variable node needs to be calculated, and the calculation formula is as follows:

and carrying out hard decision decoding according to the obtained posterior probability, wherein the decision rule is as follows:

the bit to be verified corresponding to the jth soft value in the soft value sequence forms a decoding result by a plurality of bits to be verified

And then, checking the decoding result according to a check matrix H: if it is

Indicating that the decoding result is correct, successfully decoding, terminating the current iteration process and outputting the decoding result of hard decision

If it is

And if the iteration number k is less than the maximum iteration number, returning to the iteration step to continue the iteration, otherwise, failing to decode.

2. And (4) a layered decoding algorithm.

Wherein, the layered decoding algorithm is different from the traditional MS algorithm only in that: updating rows of the check matrix in sequence according to a certain sequence; after updating of one row or one group of rows, all columns corresponding to the rows are updated immediately, and then the next row or the next group of rows are updated. The order of row updates and the order of column updates are not limiting. Layered decoding may be combined with other decoding algorithms to increase the convergence speed of the iterations. Fig. 8 is a schematic flow chart of a layered decoding algorithm, where a check matrix is 5 rows and 9 columns, and a layered iterative decoding method includes: 1. updating the

row

1, and 2, updating all columns of which the elements in the row 1 are 1; 3. updating the

row

2, and 4, updating all columns of which the elements in the row 2 are 1; 5. updating the row 3, and then updating all columns of which the elements in the row 3 are 1; 7. updating the row 4, and then 8, updating all columns of which the elements in the row 4 are 1; 9. the update is done for

row

5, 10, and then all columns in row 5 with an element of "1".

3. A combined normalized offset min-sum (CNOMS) algorithm.

Among them, the CNOMS algorithm is called a combined normalized offset min-sum (lcoms) algorithm when combined with layered decoding. CNOMS is an improvement of formula 1 in the MS algorithm, and a normalization correction factor and an offset value correction factor are added on the basis of formula 1.

Wherein, in the k iteration process, the check node i sends the information R of the variable node j_ij[k]As shown in equation 3:

wherein α 'is a normalized correction factor, β' is an offset value correction factor, min () is a minimum value operation, and max () is a maximum value operation.

Where β' is 0, the algorithm may also be referred to as normalized min-sum (NMS) algorithm.

The description of other parameters in equation 3 can refer to the MS algorithm, and is not repeated here.

The information sent by the variable node j to the ith variable node is the same as the MS algorithm.

The description of each parameter in the CNOMS algorithm and the description in the MS algorithm are not repeated here.

In conclusion, the CNOMS algorithm only considers correcting the check node updating process, and does not consider correcting other links, so that the decoding performance of the CNOMS algorithm has a further improved space.

4. Weighted Sum (WS) algorithm.

The WS algorithm is obtained by conversion on the basis of a CNOMS algorithm, and is also called CNOMS-WS algorithm. Also called joint normalized offset-minimum sum-weighting (lconoms-WS) algorithm when WS algorithm and layered coding algorithm are integrated.

In the process of the kth iteration, the variable node j sends information Q of the check node i_jiThe calculation is made according to the following formula:

Q _ji[k]＝γ·Q _ji[k-1]+(1-γ)·Q' _ji[k]；

wherein, gamma is equal to (0, 1). The definition of other parameters in the WS algorithm can refer to the description of equation 1, and is not described herein.

In conclusion, the WS algorithm needs to introduce a large number of multiplication operations and addition operations in the iterative process, the computation workload is large, and at the same time, information of the previous iteration needs to be stored, and the required amount of the storage space is also large.

5. Flip zero (FR) algorithm. The FR algorithm is obtained by conversion based on a CNOMS algorithm, and is also called CNOMS-FS algorithm. When the FR algorithm is combined with the layered coding algorithm, it is also called the joint normalized offset min-sum-inverse zero (LCNOMS-FR) algorithm.

In the process of the kth iteration, the information sent by the variable node j to the check node i is calculated according to the following formula:

the definition of each parameter in the FR algorithm can refer to the description in the WS algorithm, and is not described herein.

In summary, the FR algorithm corrects the information of the current iteration to 0 when the sign of the information of two adjacent iterations is reversed, which may reduce the speed of iteration convergence, and when the number of iterations is reduced, the decoding performance is not good.

6. The Flip Sum (FS) algorithm. The FS is obtained by conversion on the basis of a CNOMS algorithm, and the FS algorithm is also called CNOMO-FS algorithm. When combined with a hierarchical coding algorithm, the FS algorithm is also referred to as a joint normalized offset-minimum-sum-inverse-sum (LCNOMS-FS) algorithm.

the definition of each parameter in the FS algorithm may refer to the description of the MS algorithm, and is not described herein again.

In summary, when the sign of the information of the adjacent iteration is reversed, the FS algorithm corrects the information of the current iteration to the sum of the information of the adjacent iteration, which has the problems that the information of the iteration needs to be stored, the requirement on the storage space is large, and the improvement of the decoding performance relative to the CNOMS algorithm is limited.

Referring to fig. 9, a flowchart of a decoding method of an LDPC code at a receiving end according to an embodiment of the present invention is shown, where in the embodiment of the present invention, the method includes:

and S901, receiving a soft value sequence.

Specifically, the sending end performs LDPC encoding on the information bit sequence, performs constellation modulation on the encoded bit sequence, maps symbols after constellation modulation to resources, where the resources are Resource Blocks (RBs) or Resource Elements (REs), obtains wireless signals by performing carrier modulation on the resources, and sends the wireless signals to the sending end. The receiving end receives a wireless signal from the transmitting end, analyzes the wireless signal to obtain a resource block, demodulates the resource block to obtain a soft value sequence, and the soft value sequence comprises a plurality of soft values, each soft value corresponds to one bit, the soft value sequence corresponds to a coding bit sequence, and the coding bit sequence is generated by adopting LDPC coding. The receiving end may be a network device or a terminal device.

And S902, carrying out iterative decoding on the soft value sequence by using the check matrix to obtain an information bit sequence.

Specifically, the check matrix may be obtained according to the spreading factor, the base map matrix, and the offset value matrix, which may be specifically described with reference to the embodiments of fig. 4 to 6. The receiving end decodes the coding sequence by using an iterative decoding mode, the decoding result obtained after each iteration is checked according to all check equations corresponding to the check matrix, and if the check is passed, the decoding result is correct, and the decoding is successful; if the check is not passed, the decoding result is wrong, if the iteration number is smaller than the maximum iteration number, the next iteration is continued, otherwise, the decoding fails.

Embodiment one, a Flip Weighted Sum (FWS) algorithm.

During the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q_ji[k]When the sign bits of (a) are different, according to Q_ji[k-1]And Q'_ji[k]Q obtained by weighted summation_ji[k](ii) a i is the serial number of the check node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is the first information, Q ', sent by the variable node j to the check node i in the k-1 iteration process'_ji[k]And the second information is the second information which is obtained based on the combined normalized deviation minimum sum CNOMS algorithm and is sent to the check node i by the variable node j in the k iteration process.

Specifically, the sign bit represents the positive or negative of the parameter value, for example: q_ji[k-1]Has a value of-5, Q'_ji[k]Is 1, then Q_ji[k-1]And Q'_ji[k]Are not the same; another example is: q_ji[k-1]Has a value of-3, Q'_ji[k]A value of-1, then Q_ji[k-1]And Q'_ji[k]The sign bit of (a) is the same. Wherein, when k is 1, Q_ji[0]＝λ _j，λ _jIs the jth soft value in the sequence of soft values.

In summary, the embodiment of the present invention only has Q in two adjacent iterations_ji[k-1]And Q'_ji[k]When sign bit changes, weighting and correction are carried out, and compared with WS algorithm, weighting and correction are not required each time, so that the calculation amount can be saved.

In one possible implementation, the iterative decoding further includes:

at Q_ji[k-1]And Q'_ji[k]In the case of the same sign bit, Q _ji[k]＝Q' _ji[k]。

In one possible embodiment, Q is pre-stored prior to the kth iteration_ji[k-1]。

In one possible embodiment, the method is according to Q_ji[k-1]And Q'_ji[k]Q obtained by weighted summation_ji[k]The method comprises the following steps:

q is obtained according to the following formula_ji[k]：

Specifically, during k iterations, Q_ji[k]Can be expressed by the following formula:

in one possible embodiment, the comparison Q_ji[k-1]And Q'_ji[k]The sign bit of (a) includes:

In one possible embodiment, Q 'is calculated according to the formula'_ji[k]：

Wherein alpha 'is the normalization correction factor, beta' is the offset value correction factor, alpha 'is less than or equal to 1, beta' is greater than 0, min is the minimum value solving operation, max is the maximum value solving operation, and V (i) \\ j represents the variable nodes connected with the check node i except the variable node j; lambda [ alpha ]_jIs the maximum likelihood ratio information of the jth soft value in the soft value sequence; c (j) \\ i represents a set of the remaining check nodes connected to variable node j except check node i. When k is 0, R_i' _j[0]＝0，Q' _ji[0]＝λ _j，λ _jIs the jth soft value in the sequence of soft values.

In one possible embodiment, the iterative decoding is performed in a hierarchical manner.

The process of iterative decoding in a layered manner may refer to the description in fig. 8, which is not described herein again, and the convergence rate can be further increased by using a layered decoding method. When the layered coding algorithm is combined with the FWS algorithm, the algorithm is also called as lconoms + FWS algorithm.

Example two, Flip Annealing (FA) algorithm.

During the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q'_ji[k]According to the normalized correction factor, the offset value correction factor and Q 'when the sign bits are different'_ji[k]Obtained Q_ji[k](ii) a i is the serial number of the check node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is the first information, Q ', sent by the variable node j to the check node i in the k-1 iteration process'_ji[k]The second information is obtained based on a CNOMS algorithm, and the variable node j sends the second information to the check node i in the kth iteration process; stopping iterative translation when all check equations corresponding to the check matrix pass the check or the iteration times reach the maximum iteration timesAnd (4) code.

In summary, the embodiment of the present invention only has Q in two adjacent iterations_ji[k-1]And Q'_ji[k]When the sign bit is inverted, the weighting and the correction are carried out, and compared with the WS algorithm, the weighting and the correction are not required to be carried out every time, so that the calculation amount can be saved.

In one possible implementation, the iterative decoding further includes:

at Q_ji[k-1]And Q'_ji[k]Is in the same sign phase, Q_ji[k]＝Q' _ji[k]。

In one possible embodiment, Q is pre-stored prior to the kth iteration_ji[k-1]The sign bit of (c).

Specifically, sign bits of information of the last iteration are stored in advance, for example: the sign bit can be represented by only one bit without storing the information of the last iteration, thereby reducing the requirement of storage space.

In one possible embodiment, the correction factor is based on a normalized correction factor, an offset value and Q'_ji[k]Obtained Q_ji[k]The method comprises the following steps:

q is obtained according to the following formula_ji[k]：

α·sgn(Q' _ji[k])·max{|Q' _ji[k]|-β,0}；

Specifically, Q is determined_ji[k]Can be expressed by the following formula:

In one possible implementation, the iterative process further includes: q 'is calculated according to the formula'_ji[k]：

Wherein alpha 'is a normalized correction factor, beta' is an offset value correction factor, alpha 'is less than or equal to 1, beta' is more than 0, min is a minimum value solving operation, max is a maximum value solving operation, and V (i) \ j represents the variable nodes connected with the check node i except the variable node j; lambda [ alpha ]_jIs the jth soft value in the sequence of soft values; c (j) \\ i represents a set of the remaining check nodes except the check node i connected to the variable node j; when k is 0, R'_ij[0]＝0，Q' _ji[0]＝λ _j，λ _jIs the jth soft value in the sequence of soft values.

Specifically, when the layered coding algorithm and the FA algorithm are combined, the algorithm is also called as an lconoms + FA algorithm.

Referring to fig. 10, a performance graph of various decoding algorithms is provided for an embodiment of the present invention.

Parameters adopted in the decoding process: the information block length is 3840, the coding rate is 1/5, the used base map matrix is BG2, the abscissa is the maximum iteration number T _ "max" of the decoder, and the ordinate is the required signal-to-noise ratio value when the block error rate (BLER) is 10%.

The decoding algorithms in fig. 10 use layered decoding by default, and the 6 curves in the drawing are respectively the lcoams algorithm, the lcoams + WS algorithm, the lcoams + FR algorithm, the lcoams + FS algorithm, the lcoams + FWS algorithm in the embodiment of the present invention, and the lcoams + FA algorithm in the embodiment of the present invention.

As can be seen from fig. 10, the performance of the LCNOMS + FWS algorithm and the LCNOMS + FA algorithm proposed in this embodiment is significantly better than that of the LCNOMS + FR algorithm and the LCNOMS + FS algorithm, and is equivalent to that of the LCNOMS + WS algorithm, but the operation complexity of the LCNOMS + FWS algorithm of the embodiment of the present invention is significantly lower than that of the LCNOMS + WS algorithm. The LCNOMS + FA algorithm of the embodiment of the invention has the advantages that the operation complexity is obviously lower than that of the LCNOMS + WS algorithm, and the requirement of the storage space is also obviously lower than that of the LCNOMS + WS algorithm. In addition, under the condition of ensuring the same block error rate performance, the number of iterations required by the LCNOMS + FWS algorithm and the LCNOMS + FA algorithm provided by the embodiment is obviously less than that required by the LCNOMS algorithm, the LCNOMS + FR algorithm and the LCNOMS + FS algorithm, so that the throughput rate of the LDPC decoder can be significantly improved by the LCNOMS + FWS algorithm and the LCNOMS + FA algorithm provided by the embodiment.

The method of the embodiment of the present invention is explained in detail above, and a schematic structural diagram of an apparatus of the embodiment of the present invention is provided below, which is hereinafter referred to as an apparatus 11, where the apparatus 11 includes a processing unit 1101 and a transceiving unit 1102, and the apparatus 8 is configured to execute a behavior function of a receiving end in the embodiment of fig. 9.

The first embodiment is as follows:

a receiving unit 1102, configured to receive a soft value sequence; wherein the soft value sequence carries information of an information bit sequence.

A processing unit 1101, configured to perform iterative decoding on the soft value sequence by using a check matrix to obtain an information bit sequence;

wherein the iterative coding comprises: during the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q'_ji[k]Sign bit of not being in phaseAt the same time, according to Q_ji[k-1]And Q'_ji[k]Q obtained by weighted summation_ji[k](ii) a At Q_ji[k-1]And Q'_ji[k]In the case of the same sign bit, Q_ji[k]＝Q' _ji[k]. i is the serial number of the check node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is the first information, Q ', sent by the variable node j to the check node i in the k-1 iteration process'_ji[k]The second information is sent to the check node i by the variable node j in the kth iteration process based on the combined normalized deviation minimum sum CNOMS algorithm; and stopping iterative decoding when all check equations corresponding to the check matrix pass the check or the iteration times reach the maximum iteration times.

In one possible design, the apparatus 11 further comprises: a memory cell (not shown in fig. 11).

The storage unit is used for storing Q in advance before the k-th iteration_ji[k-1]。

In one possible design, the processing unit 1101 is according to Q_ji[k-1]And Q'_ji[k]Q obtained by weighted summation_ji[k]The method comprises the following steps:

q is obtained according to the following formula_ji[k]：

In one possible design, the processing unit compares Q_ji[k-1]And Q'_ji[k]The sign bit of (a) includes:

In one possible design, the processing unit 1101 is further configured to:

q 'is calculated according to the formula'_ji[k]：

Wherein, alpha 'is a normalization correction factor, beta' is an offset value correction factor, min is a minimum value solving operation, alpha 'is less than or equal to 1, beta' is more than 0, max is a maximum value solving operation, and V (i) \\ j represents the variable nodes connected with the check node i except the variable node j; lambda [ alpha ]_jIs the jth soft value in the sequence of soft values; c (j) \\ i represents a set of the remaining check nodes connected to variable node j except check node i.

In one possible design, the iterative decoding is performed using a layered decoding algorithm.

Example two:

a transceiving unit 1102, configured to receive a soft value sequence; wherein the soft value sequence carries information of an information bit sequence.

A processing unit 1101, configured to perform iterative decoding on the soft value sequence according to the check matrix to obtain an information bit sequence;

wherein the iterative coding comprises: during the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q'_ji[k]According to the normalized correction factor, the offset value correction factor and Q 'when the sign bits are different'_ji[k]Obtained Q_ji[k](ii) a At Q_ji[k-1]And Q'_ji[k]Is in the same sign phase, Q_ji[k]＝Q' _ji[k](ii) a i is the serial number of the check node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is the first information, Q ', sent by the variable node j to the check node i in the k-1 iteration process'_ji[k]The second information is sent to the check node i by the variable node j in the kth iteration process based on the combined normalized deviation minimum sum CNOMS algorithm; and stopping iterative decoding when all check equations corresponding to the check matrix pass the check or the iteration times reach the maximum iteration times.

In one possible design, the apparatus 11 further comprises:

a storage unit (not shown in FIG. 11) for pre-storing Q before the k-th iteration_ji[k-1]The sign bit of (c).

In one possible design, the processing unit is further configured to:

q is obtained according to the following formula_ji[k]：

α·sgn(Q' _ji[k])·max{|Q' _ji[k]|-β,0}；

Wherein alpha is a normalized correction factor, beta is an offset value correction factor, alpha is less than or equal to 1, beta is more than 0, sgn is a sign bit operation, and max is a maximum value operation.

In one possible design, processing unit 1101 compares Q_ji[k-1]And Q'_ji[k]The sign bit of (a) includes:

In one possible design, the processing unit 1101 is further configured to:

q 'is calculated according to the formula'_ji[k]：

The above device embodiments only list logic functions between modules, and please refer to their corresponding method embodiments for specific execution processes and beneficial effects.

The device 11 may be a terminal device or a network device, or may be a decoder, a field-programmable gate array (FPGA), an application-specific integrated chip, a system on chip (SoC), a Central Processing Unit (CPU), a Network Processor (NP), a digital signal processing circuit, a Micro Controller Unit (MCU), or a Programmable Logic Device (PLD) or other integrated chips, which implement related functions.

The embodiment of the present invention and the embodiment of the method of fig. 9 are based on the same concept, and the technical effects brought by the embodiment of the present invention are also the same, and the specific process can refer to the description of the embodiment of the method of fig. 9, and will not be described herein again.

Fig. 12 is a schematic structural diagram of an apparatus according to an embodiment of the present invention, which is hereinafter referred to as an apparatus 12 for short, where the apparatus 12 may be integrated in the foregoing network device or terminal device, as shown in fig. 12, the apparatus includes: memory 1202, processor 1201, transceiver 1203.

The memory 1202 may be a separate physical unit, which may be connected to the processor 1201 and the transceiver 1203 by a bus. The memory 1202, the processor 1201, the transceiver 1203 may also be integrated together, implemented by hardware, etc.

The memory 1202 is used for storing a program for implementing the above method embodiment, or various modules of the apparatus embodiment, and the processor 1201 calls the program to execute the operations of the above method embodiment.

Alternatively, when part or all of the decoding method of the LDPC code of the above embodiments is implemented by software, the apparatus may also include only a processor. The memory for storing the program is located outside the device and the processor is connected to the memory by means of circuits/wires for reading and executing the program stored in the memory.

The processor may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP.

The processor may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.

The memory may include volatile memory (volatile memory), such as random-access memory (RAM); the memory may also include a non-volatile memory (non-volatile memory), such as a flash memory (flash memory), a Hard Disk Drive (HDD) or a solid-state drive (SSD); the memory may also comprise a combination of memories of the kind described above.

In the above embodiments, the sending module or the transmitter performs the sending steps of the above various method embodiments, the receiving module or the receiver performs the receiving steps of the above various method embodiments, and other steps are performed by other modules or processors. The transmitting module and the receiving module may constitute a transceiver module, and the receiver and the transmitter may constitute a transceiver.

The embodiment of the application also provides a computer storage medium, which stores a computer program, and the computer program is used for executing the decoding method of the LDPC code provided by the embodiment.

The embodiment of the present application further provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the decoding method of the LDPC code provided in the above embodiments.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Claims

A decoding method of a Low Density Parity Check (LDPC) code is characterized by comprising the following steps:

receiving a sequence of soft values; wherein the soft value sequence carries information of an information bit sequence;

carrying out iterative decoding on the soft value sequence by using a check matrix to obtain an information bit sequence;

wherein the iterative coding comprises: during the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q'_ji[k]When the sign bits of (a) are different, according to Q_ji[k-1]And Q'_ji[k]Q obtained by weighted summation_ji[k](ii) a At Q_ji[k-1]And Q'_ji[k]In the case of the same sign bit, Q_ji[k]＝Q' _ji[k](ii) a i is the serial number of the check node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is the first information that the variable node j sends to the check node i in the k-1 iteration process, Q' ji [ k [)]Is the kth variable node j sent to the check node i in the kth iteration process obtained based on the combined normalized deviation minimum sum CNOMS algorithmInformation II; and stopping iterative decoding when all check equations corresponding to the check matrix pass the check or the iteration times reach the maximum iteration times.
The method of claim 1, wherein Q is pre-stored prior to the kth iteration_ji[k-1]。
Method according to claim 1 or 2, characterized in that said method is according to Q_ji[k-1]And Q'_ji[k]Q obtained by weighted summation_ji[k]The method comprises the following steps:

q is obtained according to the following formula_ji[k]：

Q _ji[k]＝γ·Q _ji[k-1]+(1-γ)·Q′ _ji[k](ii) a Wherein gamma is more than 0 and less than 1.
An LDPC decoding method, comprising:

receiving a sequence of soft values; wherein the soft value sequence carries information of an information bit sequence;

performing iterative decoding on the soft value sequence according to the check matrix to obtain an information bit sequence;

wherein the iterative coding comprises: during the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q'_ji[k]According to the normalized correction factor, the offset value correction factor and Q 'when the sign bits are different'_ji[k]Obtained Q_ji[k](ii) a At Q_ji[k-1]And Q'_ji[k]Is in the same sign phase, Q_ji[k]＝Q' _ji[k](ii) a i is the serial number of the check node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is a variable node in the k-1 iteration processThe point j sends first information Q 'to a check node i'_ji[k]The second information is sent to the check node i by the variable node j in the kth iteration process based on the combined normalized deviation minimum sum CNOMS algorithm; and stopping iterative decoding when all check equations corresponding to the check matrix pass the check or the iteration times reach the maximum iteration times.
The method of claim 4, wherein Q is pre-stored prior to the kth iteration_ji[k-1]The sign bit of (c).
The method of claim 4 or 5, wherein the iterative decoding further comprises:

q is obtained according to the following formula_ji[k]：

α·sgn(Q′ _ji[k])·max{|Q′ _ji[k]|-β，0}；

Wherein alpha is a normalization correction factor, beta is an offset value correction factor, sgn is a sign bit operation, max is a maximum value operation, alpha is less than or equal to 1, and beta is more than 0.
The method of any of claims 1 to 6, wherein the comparison Q is performed_ji[k-1]And Q'_ji[k]The sign bit of (a) includes:

at Q_ji[k-1]And Q'_ji[k]When the product of (A) is greater than or equal to 0, Q is determined_ji[k-1]And Q'_ji[k]The sign bits of (a) are the same; or

At Q_ji[k-1]And Q'_ji[k]When the product of (A) is less than 0, Q is determined_ji[k-1]And Q'_ji[k]Are not the same.
The method of any of claims 1 to 7, wherein the iterative process further comprises: q 'is calculated according to the formula'_ji[k]：

Wherein alpha 'is a normalized correction factor, beta' is an offset value correction factor, alpha 'is less than or equal to 1, beta' is more than 0, min is a minimum value solving operation, max is a maximum value solving operation, and V (i) \ j represents the variable nodes connected with the check node i except the variable node j; lambda [ alpha ]_jIs the jth soft value in the sequence of soft values; c (j) \\ i represents a set of the remaining check nodes connected to variable node j except check node i.
The method according to any of claims 1 to 8, characterized in that said iterative decoding is performed using a layered decoding algorithm.
An apparatus for decoding an LDPC code, comprising:

a receiving unit, configured to receive a soft value sequence; wherein the soft value sequence carries information of an information bit sequence;

the processing unit is used for carrying out iterative decoding on the soft value sequence by using a check matrix to obtain an information bit sequence;

wherein the iterative coding comprises: during the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q'_ji[k]When the sign bits of (a) are different, according to Q_ji[k-1]And Q'_ji[k]Q obtained by weighted summation_ji[k](ii) a At Q_ji[k-1]And Q'_ji[k]In the case of the same sign bit, Q_ji[k]＝Q' _ji[k](ii) a i is a checkThe serial number of the node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is the first information, Q ', sent by the variable node j to the check node i in the k-1 iteration process'_ji[k]The second information is sent to the check node i by the variable node j in the kth iteration process based on the combined normalized deviation minimum sum CNOMS algorithm; and stopping iterative decoding when all check equations corresponding to the check matrix pass the check or the iteration times reach the maximum iteration times.
The apparatus of claim 10, further comprising: a storage unit:

the storage unit is used for storing Q in advance before the k-th iteration_ji[k-1]。
The apparatus according to claim 10 or 11, wherein the processing unit is based on Q_ji[k-1]And Q'_ji[k]Q obtained by weighted summation_ji[k]The method comprises the following steps:

q is obtained according to the following formula_ji[k]：

Q _ji[k]＝γ·Q _ji[k-1]+(1-γ)·Q′ _ji[k](ii) a Wherein gamma is more than 0 and less than 1.
An apparatus for decoding an LDPC code, comprising:

a receiving and sending unit, which is used for receiving the soft value sequence; wherein the soft value sequence carries information of an information bit sequence;

the processing unit is used for carrying out iterative decoding on the soft value sequence according to the check matrix to obtain an information bit sequence;

wherein the iterative coding comprises: during the kth iteration, Q is compared_ji[k-1]And Q'_ji[k]Sign bit of in Q_ji[k-1]And Q'_ji[k]Is different, based on the normalized correction factor, the offset value correction factor, and
obtained Q_ji[k](ii) a At Q_ji[k-1]And Q'_ji[k]Is in the same sign phase, Q_ji[k]＝Q' _ji[k](ii) a i is the serial number of the check node, j is the serial number of the variable node, k is an integer greater than or equal to 1, Q_ji[k]Is the first information Q sent by the variable node j to the check node i in the k iteration process_ji[k-1]Is the first information, Q ', sent by the variable node j to the check node i in the k-1 iteration process'_ji[k]The second information is sent to the check node i by the variable node j in the kth iteration process based on the combined normalized deviation minimum sum CNOMS algorithm; and stopping iterative decoding when all check equations corresponding to the check matrix pass the check or the iteration times reach the maximum iteration times.
The apparatus of claim 4, further comprising:

a storage unit for storing Q in advance before the k-th iteration_ji[k-1]The sign bit of (c).
The method of claim 13 or 14, wherein the processing unit is further configured to:

q is obtained according to the following formula_ji[k]：

α·sgn(Q′ _ji[k])·max{|Q′ _ji[k]|-β，0}；

Wherein alpha is a normalization correction factor, beta is an offset value correction factor, sgn is a sign bit operation, max is a maximum value operation, alpha is less than or equal to 1, and beta is more than 0.
According to any of claims 10 to 15An apparatus as in, wherein the processing unit compares Q_ji[k-1]And Q'_ji[k]The sign bit of (a) includes:

at Q_ji[k-1]And Q'_ji[k]When the product of (A) is greater than or equal to 0, Q is determined_ji[k-1]And Q'_ji[k]The sign bits of (a) are the same; or

At Q_ji[k-1]And Q'_ji[k]When the product of (A) is less than 0, Q is determined_ji[k-1]And Q'_ji[k]Are not the same.
The apparatus according to any one of claims 10 to 16, wherein the processing unit is further configured to:

q 'is calculated according to the formula'_ji[k]：

Wherein alpha 'is a normalized correction factor, beta' is an offset value correction factor, alpha 'is less than or equal to 1, beta' is more than 0, min is a minimum value solving operation, max is a maximum value solving operation, and V (i) \ j represents the variable nodes connected with the check node i except the variable node j; lambda [ alpha ]_jIs the jth soft value in the sequence of soft values; c (j) \\ i represents a set of the remaining check nodes connected to variable node j except check node i.
The apparatus according to any one of claims 10 to 17, wherein said iterative decoding is performed using a layered decoding algorithm.
Decoding device of LDPC codes for carrying out the method of any one of claims 1 to 9.
An apparatus for decoding an LDPC code, comprising: a memory and a processor; the processor is configured to support the apparatus to perform the functions of the method of any of claims 1 to 9, and the memory is configured to store programs and data necessary for the apparatus.
A computer storage medium comprising instructions which, when run on a computer, cause the computer to perform the method of any one of claims 1 to 9.
A computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of any one of claims 1 to 9.