CN108183713B - LDPC decoder based on improved minimum sum algorithm and decoding method thereof - Google Patents
LDPC decoder based on improved minimum sum algorithm and decoding method thereof Download PDFInfo
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- H03M13/1148—Structural properties of the code parity-check or generator matrix
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- H03M13/112—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule with correction functions for the min-sum rule, e.g. using an offset or a scaling factor
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Abstract
The invention discloses an LDPC decoder based on an improved minimum sum algorithm and a decoding method thereof, which mainly aim at that under the condition of high-order modulation, bits in each Symbol are not independent, while the existing binary LDPC decoding algorithm decodes based on the initial likelihood ratio of each Bit and does not utilize the correlation between the bits. The algorithm provided by the invention is used for decoding based on the initial likelihood ratio of Symbol, and channel information is more effectively utilized, so that better error correction performance and lower error rate are obtained under the condition of high-order modulation. In the decoding process, the initial likelihood ratio of each Symbol is calculated by utilizing the channel information, each message is initialized by utilizing the initial likelihood ratio, then the likelihood ratios of the messages and the symbols are updated in an iterative mode, and finally the likelihood ratios of the symbols are subjected to hard decision to obtain a decoding result.
Description
Technical Field
The invention belongs to a communication system and a digital storage system, and particularly relates to an LDPC decoder based on an improved minimum sum algorithm and a decoding method thereof.
Background
LDPC codes (Low Density Parity Check Code) were originally proposed by Calleger in 1961 and were redeveloped by Makey and New et al in 1996. Research shows that the LDPC code not only has decoding performance approaching Shannon, but also enables decoding to have low linear decoding complexity and flexible structure. At present, the LDPC code correlation technique has been widely applied to the fields of optical fiber communication, satellite communication, nonvolatile memory, and the like. Meanwhile, LDPC codes have become the WiFi and DVB-S2 standards. In 2016, LDPC was accepted by 3GPP as a long-code block coding scheme for 5G system eMBB traffic data information.
The LDPC code decoding algorithm plays a crucial role in the error correction of a decoder and is mainly divided into the following two directions: (1) and a hard decision decoding algorithm (2) and a soft decision decoding algorithm. The latter has a better performance but is too complex. Belief Propagation (BP) algorithms were developed, and approximate improvements such as min-sum decoding, normalized min-sum decoding, etc. were made on the basis of the Belief Propagation algorithms, with a compromise in complexity and performance. For the soft decision decoding algorithm, the C2V information (Check to Variable Messages) and the V2C information (Variable to Check Messages) are continuously updated in an iterative decoding manner, the posterior information calculated by the C2V information is used for decision, and the iterative decoding is completed if the decision codeword satisfies the Check. The core of the method is an information calculation mode and an information scheduling mode. The information calculation method determines how the C2V information and the V2C information are converted, and the information scheduling method determines the order of updating the C2V information and the V2C information. Information calculation methods include SP (Sum-Product), MS (Min-Sum), and information Scheduling methods include TPMP (two Phase Message publishing), VSS (VN-central Sequence Scheduling).
Disclosure of Invention
The purpose of the invention is as follows: the invention provides an LDPC decoder based on an improved min-sum algorithm and a decoding method thereof aiming at the defects of the existing min-sum decoding algorithm.
The technical scheme is as follows: the invention provides an LDPC decoder based on an improved minimum sum decoding algorithm and a decoding method thereof. For the LDPC decoder based on the improved minimum sum algorithm, the decoder adopts the improved minimum sum decoding algorithm grouped by columns, and comprises a Symbol data memory, a Bit likelihood ratio calculation unit, a Bit data memory, a Symbol processing unit, a check node processing unit, a selector, a register, an output data memory and a Symbol memory, wherein the decoding process of the decoder comprises the following steps:
(1) initialization processing: firstly, storing initial likelihood ratio data of Symbol input into a decoder in a Symbol data memory, calculating a Bit likelihood ratio corresponding to the initial likelihood ratio data, and then storing the Bit initial likelihood ratio data in a Bit data memory;
(2) after decoding, the Symbol processing unit receives the Symbol initial log-likelihood ratio in the Symbol data memory, the corresponding Bit initial log-likelihood ratio in the Bit data memory, and the C2V related information in the register, and calculates V2C information; meanwhile, the Symbol processing unit also carries out hard judgment on whether the check node connected with the current variable node meets the check, and determines whether to finish decoding in advance according to the hard judgment result; in order to carry out C2V information of the next iteration, the sign of the updated V2C information needs to be input into a sign memory for storage;
(3) the check node processing unit receives the V2C information from the Symbol processing unit and the sign of the V2C information of the last iteration to update and calculate the C2V information; and inputs the updated C2V information into registers and memory;
(4) when the information of all columns is updated, the iteration is finished, and the iteration count is added by 1;
(5) if the decoder completes decoding before the preset maximum iteration times, the decoder terminates iteration in advance, outputs the decoding result to the output data memory and declares the decoding success; otherwise, if the decoding is not successful after reaching the maximum number of iterations, the decoder will terminate the iterations and declare the decoding failure.
Further, the decoder adopts a minimum sum decoding algorithm grouped according to columns, the width of the grouped according to columns is the dimension of the submatrix, and the variable node processing unit is updated according to the bit column width of Symbol.
Further, the parallel computing number NUM of each group of SVNU units of the min-sum decoding algorithm is
Furthermore, each check node processing unit of the decoder comprises one or more sub check node units, the number of the sub check node units is at most column-repeated, the sub check node units calculate and update the C2V information in parallel, and the parallelism is the dimension of the sub matrix.
The invention also provides an LDPC decoding method based on the improved minimum sum algorithm, which comprises the following steps:
(a) an initialization process: firstly, according to the initial log likelihood ratio of each received Symbol
To calculate the log likelihood ratio of Bit
I.e., initialized V2C (variable node passed to check node) information, the expression is as follows:
wherein each Symbol may take a value of
So that the value range of x is
An integer of (d); k represents a Bit mark in Symbol, and the value range is an integer between 0 and SymWid-1; j represents Symbol, j is 0 to (N/SymWid) -1, and N is a code length.
(b) Setting a maximum iteration time MAX, wherein the iteration time k is 1;
(c) and (3) information processing of the check nodes: firstly, finding a first minimum value min1, a second minimum value min2, an index min1_ idx of the first minimum value, a global sign and a current V2C information sign V2C _ sign of each row according to V2C information to update C2V information;
(d) each variable node collects log-likelihood ratio information of the check node connected with the variable node to perform hard decision to obtain an output codeword out, and the expression is as follows:
(e) and (3) information processing of variable nodes: when all variable nodes and the adjacent check nodes are subjected to iterative computation, messages transmitted to the variable nodes by the check nodes are updated by taking Symbol as a unit, and the expression is as follows:
x1＝x0＝outj (4)
wherein the content of the first and second substances,
representing a set of check nodes connected to the current position variable node;
representing a posteriori information of each variable node;
(f) stopping iteration: judging whether the decoding result meets the check, if so, stopping iteration and outputting the decoding result; otherwise, returning to the step (c) to continue the iteration, and adding 1 to the iteration number k until the maximum iteration number MAX is reached, and simultaneously giving a decoding failure mark.
Further, the step (a) comprises preprocessing the obtained initial log likelihood ratio of Symbol;
the C2V information update in step (C) comprises the following steps:
if V2C _ idx is min1_ idx, abs (C2V) is min2, otherwise abs (C2V) is min 1;
sign(C2V)＝sign(V2C_idx)·global sign；
where V2C _ idx denotes the index of the current V2C information, and sign (V2C _ idx) denotes the sign of the current V2C information.
Further, the C2V information of step (C) is the first minimum value min1, the second minimum value min2, the index of the first minimum value min1_ idx, and the global symbol in each row; wherein the index of the first minimum value indicates its position in the current row.
After decoding, the decoder first reads the log-likelihood ratio of the first Symbol of the current frame and stores the read information in the Symbol data memory. Then, the log-likelihood ratio of the Bit is calculated according to the log-likelihood ratio of Symbol and stored in a Bit data memory. And after all Symbol log-likelihood ratios of the frame are processed, starting iterative decoding. The specific working process is as follows: the Bit log likelihood ratio and Symbol log likelihood ratio taken out from the data memory, and the C2V information are input to a Symbol processing unit (SVNU), and the summed V2C information is input to a VC barrel shifter while their signs are stored; VC barrel shifter shifts the received data to align the shifted data according to the check nodes in the check matrix H; the check node processing unit CNU updates the minimum value and the index, and finally stores the C2V information into a register or a memory through a selector, thereby completing the information update of the column. Until all columns are updated according to the above process, we call that one iteration is completed, and the number of iterations is increased by 1. Judging whether the iteration meets the check through a hard judgment result in the SVNU, if so, indicating that the decoding is successful, and inputting the judgment result into a data memory; if the check is not satisfied and the iteration number does not reach the maximum iteration number, continuing to perform iteration; if the check is not satisfied and the maximum iteration number is reached, the decoding is failed.
Has the advantages that: compared with the prior art, the LDPC decoder and the decoding method thereof based on the improved min-sum decoding algorithm have the obvious effect that the channel information is more effectively utilized, so that the decoding performance is improved.
Drawings
FIG. 1 is a flow chart of an improved min-sum decoding algorithm;
FIG. 2 is a diagram of the hardware architecture of a quasi-cyclic LDPC decoder based on a modified min-sum decoding algorithm;
FIG. 3a is an architecture diagram of a variable node processing unit of the present decoder;
fig. 3b is an architecture diagram of a check node processing unit of the present decoder.
Detailed Description
In order to explain the technical scheme disclosed by the invention in detail, the following description is further made by combining the drawings of the specification, algorithm pseudo codes and specific embodiments.
The flow chart of the improved min-sum decoding algorithm proposed by the present invention is shown in fig. 1. The method specifically comprises the following steps:
step 1: obtaining log likelihood ratio information of each Symbol
The log likelihood ratio information of the Bit is obtained by the following pretreatment
I.e. the initial V2C information;
wherein each Symbol may take a value of
So that the value range of x is
An integer of (d); k represents a Bit mark in Symbol, and the value range is an integer between 0 and SymWid-1; j represents Symbol, j is 0 to (N/SymWid) -1, and N is a code length.
Step 2: setting a maximum iteration time MAX, wherein the iteration time k is 1;
and step 3: finding a first minimum value min1, a second minimum value min2, a first minimum value index min1_ idx and a global symbol according to the V2C information, and updating and calculating the C2V information according to the information;
step 4: summing the C2V information to obtain a code word out through hard decision, checking according to the code word, stopping iteration if the code word is met, and outputting a decoding result; otherwise, continuing iteration (specifically, see algorithm pseudo codes 1,2 and 3);
and 5: the a posteriori information app is calculated and the V2C information is updated with the number of iterations plus 1. Steps 3, 4, 5 are repeated (see algorithm pseudocode 4 in particular).
The algorithm pseudo-code is as follows:
algorithm 1:
and 2, algorithm:
algorithm 3:
and algorithm 4:
the check matrix m.qxn.q of the quasi-cyclic LDPC code is constructed based on cyclic sub-matrices and uses an offset parameter Pi,jTo indicate. Each cyclic sub-matrix is circularly right shifted by P from q × q unit matrixi,jAnd obtaining the product. Here, q is the dimension of the submatrix. In particular, Pi,j0 is a unit matrix of qxq, Pi,jThe zero matrix is represented by-1, and the check matrix expression of the quasi-cyclic LDPC code is as follows:
the basic matrix H isparamIs the offset parameter Pi,jPerforming a cyclic right shift, Pi,jThe range is an integer between-1 and q-1, and the specific expression is as follows:
in order to conveniently explain the structure of the decoder after the minimum sum decoding algorithm is improved, a quasi-cyclic LDPC code with the sub-matrix dimension of 96, the code length of 2304, the check bit of 1152 and the code rate of 0.5 in the IEEE802.16c standard is adopted. The basic matrix of the check matrix is as follows, and the column weight (the number of 1 check matrix H per column) is 6 at most.
| -1 | 94 | 73 | -1 | -1 | -1 | -1 | -1 | 55 | 83 | -1 | -1 | 7 | 0 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 |
| -1 | 27 | -1 | -1 | -1 | 22 | 79 | 9 | -1 | -1 | -1 | 12 | -1 | 0 | 0 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 |
| -1 | -1 | -1 | 24 | 22 | 81 | -1 | 33 | -1 | -1 | -1 | 0 | -1 | -1 | 0 | 0 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 |
| 61 | -1 | 47 | -1 | -1 | -1 | -1 | -1 | 65 | 25 | -1 | -1 | -1 | -1 | -1 | 0 | 0 | -1 | -1 | -1 | -1 | -1 | -1 | -1 |
| -1 | -1 | 39 | -1 | -1 | -1 | 84 | -1 | -1 | 41 | 72 | -1 | -1 | -1 | -1 | -1 | 0 | 0 | -1 | -1 | -1 | -1 | -1 | -1 |
| -1 | -1 | -1 | -1 | 46 | 40 | -1 | 82 | -1 | -1 | -1 | 79 | 0 | -1 | -1 | -1 | -1 | 0 | 0 | -1 | -1 | -1 | -1 | -1 |
| -1 | -1 | 95 | 53 | -1 | -1 | -1 | -1 | -1 | 14 | 18 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 0 | 0 | -1 | -1 | -1 | -1 |
| -1 | 11 | 73 | -1 | -1 | -1 | -2 | -1 | -1 | 47 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 0 | 0 | -1 | -1 | -1 |
| 12 | -1 | -1 | -1 | 83 | 24 | -1 | 43 | -1 | -1 | -1 | 51 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 0 | 0 | -1 | -1 |
| -1 | -1 | -1 | -1 | -1 | 94 | -1 | 59 | -1 | -1 | 70 | 72 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 0 | 0 | -1 |
| -1 | -1 | 7 | 65 | -1 | -1 | -1 | -1 | 39 | 49 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 0 | 0 |
| 43 | -1 | -1 | -1 | -1 | 66 | -1 | 41 | -1 | -1 | -1 | 26 | 7 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 0 |
In this example, a quasi-cyclic LDPC hardware architecture based on a modified min-sum decoding algorithm is shown in fig. 2. The log-likelihood ratios of Symbol input to the decoder are first stored in Symbol data memory 201. Before decoding, the log-likelihood ratio of the corresponding Symbol is taken out from the Symbol data memory 201, sent to the Bit information calculation unit 202, calculated and sent to the Bit data memory 203. After decoding is started, Symbol processing unit (SVNU)204 receives Bit log likelihood ratio in Bit data memory 203, log likelihood ratio of Symbol in data memory 201, and C2V information in register 206, and calculates updated V2C information. Inputting V2C information into VC barrel shifter (variable node barrel shifter) 213-214, and storing the signs into VBLK MEM 209; VC barrel shifter shifts the received data, and aligns the shifted data according to check nodes in an H matrix; CNU unit 208 receives the new minimum value and index to update the minimum value and index.
The improved minimum sum decoding algorithm provided by the invention is different from the traditional minimum sum decoding algorithm, the algorithm considers the non-independence between bits under high-order modulation, and the likelihood ratio of Symbol is used instead of the likelihood ratio of Bit when updating the message. Meanwhile, the Symbol processing unit updates the V2C information in units of Symbol length. Thus, here 4 VNUs constitute one SVNU unit.
Furthermore, the LDPC decoder based on the improved minimum sum algorithm and the decoding method thereof comprise the following steps:
(1) before the iteration starts, Symbol log-likelihood ratios input to the decoder are first stored in a Symbol data memory 201, and simultaneously, Bit log-likelihood ratios corresponding to the Symbol log-likelihood ratios are calculated by a Bit calculation unit 201, and the calculation results are stored in a Bit log-likelihood ratio memory 203.
(2) The SVNU unit 204 receives Symbol log likelihood ratios in the Symbol data memory, Bit log likelihood ratios in the Bit data memory, and the C2V information stored in the register 206, and calculates updated V2C information. Only one SVNU unit is needed and one column of the base matrix is calculated.
(3) The SVNU unit 204 is configured to update the V2C information, and calculate a sum of check nodes connected to the current variable node, and if the sum is zero, satisfy the check that iteration can be terminated in advance, declare that decoding is successful, and output a codeword; otherwise, the next iteration is continued without the requirement of checking, and the iteration times are added by 1.
(4) SVNU unit 204 stores the sign of the updated V2C information in sign memory 209 for the purpose of calculating the C2V information for the next iteration.
(5) After the variable node is updated, the check node processing unit CNU 208 receives the updated V2C information and the sign of the V2C information of the last iteration stored in the sign memory 209 to calculate the updated C2V information. In this example, the maximum column weight of the check matrix is 6, so there are 6 CNU units corresponding to the 6 check nodes connected to the current position variable node.
It should be noted that, in the case of the improved min-sum decoding algorithm grouped by columns in this example, the C2V information refers to the first minimum value min1, the second minimum value min2, the index min1_ idx of the first minimum value, and the global symbol global sign of each row. The index of the first minimum value represents its position on the current row.
(6) The C2V storage unit 205 aligns the 6 pieces of min & index information to be processed at the current time among the 6 regs 206; the Selector sub-module 211 receives the min & index information and selects the first minimum value min1 or the second minimum value min2 as the absolute value of the C2V information according to the current index. The CV barrel shifter 212 shifts the received data so that the shifted data are aligned with the variable nodes in the H matrix, and then sends the data to the Symbol processing unit 204. Meanwhile, the global symbol global sign is taken out from the storage unit 205 and the symbol of the last iteration V2C in the symbol memory 209 are subjected to exclusive OR, and the updated symbol of the C2V information can be obtained.
(7) When the variable information and the check information of all the columns are updated, the iteration is called to be completed, the iteration times are increased by 1, and the next iteration process is continued. If the decoder meets the check before the maximum iteration number is not reached, the decoding is successful, and the decoding result is input into the storage unit 210; if the maximum number of iterations has been reached and all checks are not satisfied, a decoding failure is declared.
It should be noted that since this example employs the column-wise block decoding, the dimension of the column is the dimension of the submatrix, so that 24 SVNU units are required for updating a set of V2C information, and each SVNU unit requires 4 VNUs to process 4 column variable nodes at the same time.
Details of the calculation processing of the variable node processing unit and the check node unit are specifically described below with reference to fig. 3a and 3 b.
As shown in fig. 3a, the VNU unit 300 receives the information of q bit V2C, and updates the first minimum value min1, the second minimum value min2, and the first minimum value index update flag. The specific treatment process comprises the following steps: firstly, subtracting the absolute value of the input V2C information from min1 in the register 301, selectively outputting a new min1 according to the subtracted sign, and sending the new min1 into the register 301; similarly, find new min2 and send it to register 302; while updating the index of the first minimum value. And performing XOR between the sign of the input V2C information and the sign of the register 303 to obtain an updated global sign.
It will be appreciated that the sign of the subtraction result, taken as the selection terminal of the selector, is essentially the smaller number of two data inputs to the output subtractor.
As shown in fig. 3b, the check node processing units 311, 312 to 316 convert the original code of each row of received q Bit C2V information (all check nodes connected to the current variable node) into a complementary code, then add the complementary code to the Bit log-likelihood ratio obtained by the Symbol processing unit 323, and perform a hard decision 342 on the summed result to obtain a hard decision result and output the hard decision result; the summed result is correlated with Symbol 324, 325 to obtain information, and is added 321 and subtracted 322 to obtain posterior information. And then subtracting the C2V information 326-433 of the self position from the posterior information of each row to obtain the variable node information V2C in the improved min-sum decoding algorithm, and finally converting the complementary code of the V2C information into the original code 334-338 for output.
The present invention can have a plurality of decoding architectures for implementing the improved min-sum decoding algorithm, and the example of the improved min-sum decoding architecture grouped by columns does not mean that the specific example to which the present invention is applied is limited to a specific flow or embodiment structure.
It should be noted that: the above parameters used in this example are only for convenience of describing the hardware architecture, and are not intended to limit the application scenarios of the present decoder. In addition, the improvement of the decoding algorithm on the channel information is not only suitable for the minimum sum decoding algorithm, but also suitable for other algorithms for iterative decoding based on soft information. Furthermore, the decoder based on the present algorithm may be implemented on any suitable hardware processor, e.g. an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), etc.
Claims (8)
1. LDPC decoder based on improved min-sum algorithm, characterized in that: the decoder adopts an improved minimum sum decoding algorithm grouped by columns, and comprises a Symbol data memory, a Bit likelihood ratio calculation unit, a Bit data memory, a Symbol processing unit, a check node processing unit, a selector, a register, an output data memory and a Symbol memory, wherein the decoding process of the decoder comprises the following steps:
(1) initialization processing: firstly, storing initial likelihood ratio data of Symbol input into a decoder in a Symbol data memory, calculating a Bit likelihood ratio corresponding to the initial likelihood ratio data, and then storing the Bit initial likelihood ratio data in a Bit data memory;
(2) after decoding is started, the Symbol processing unit receives the initial log-likelihood ratio of Symbol in the Symbol data memory, the initial log-likelihood ratio of corresponding Bit in the Bit data memory, and the C2V information transmitted to the variable node by the check node in the register, and calculates the V2C information transmitted to the check node by the variable node; meanwhile, the Symbol processing unit also performs hard decision on whether the check node connected with the current variable node meets the check, determines whether to finish decoding in advance according to a hard decision result, and needs to input the updated Symbol of the V2C information into a Symbol memory for storage in order to perform C2V information of the next iteration;
(3) the check node processing unit receives the V2C information from the Symbol processing unit and the sign of the V2C information of the last iteration to update and calculate the C2V information; and inputs the updated C2V information into registers and memory;
(4) when the information of all columns is updated, the iteration is finished, and the iteration count is added by 1;
(5) if the decoder completes decoding before the preset maximum iteration times, the decoder terminates iteration in advance, outputs the decoding result to the output data memory and declares the decoding success; otherwise, if the decoding is not successful after reaching the maximum number of iterations, the decoder will terminate the iterations and declare the decoding failure.
2. The improved min-sum algorithm based LDPC decoder as claimed in claim 1, wherein the decoder adopts a min-sum decoding algorithm grouped by columns, the width of the grouped by columns is a dimension of the submatrix, and the variable node processing unit is updated in units of bit column widths of Symbol.
3. The LDPC decoder according to claim 2, wherein the number NUM of Symbol processing units in each group of the minimum sum decoding algorithm is calculated in parallel
4. The improved min-sum algorithm based LDPC decoder of claim 1 wherein each check node processing unit of the decoder comprises one or more sub-check node units, up to a column-multiplicity, the sub-check node units compute updated C2V information in parallel, and the degree of parallelism is a dimension of the sub-matrix.
5. An LDPC decoding method based on an improved minimum sum algorithm is characterized by comprising the following steps:
(a) an initialization process: firstly, according to the initial log likelihood ratio of each received Symbol
To calculate the log likelihood ratio of Bit
I.e., V2C information passed to the check node by the initialized variable node, the expression is as follows:
wherein each Symbol may take a value of 2SymWidSo that the value range of x is 0-2SymWid-an integer of 1; k represents a Bit mark in Symbol, and the value range is an integer between 0 and SymWid-1; j represents Symbol mark, j is 0 to (N/SymWid) -1, N is code length;
(b) setting a maximum iteration time MAX, wherein the iteration time k is 1;
(c) and (3) information processing of the check nodes: firstly, finding a first minimum value min1, a second minimum value min2, an index min1_ idx of the first minimum value, a global symbol global sign and a current V2C information symbol V2C _ sign of each row according to V2C information to update C2V information transmitted to variable nodes by check nodes;
(d) each variable node collects log-likelihood ratio information of the check node connected with the variable node to perform hard decision to obtain an output codeword out, and the expression is as follows:
(e) and (3) information processing of variable nodes: when all variable nodes and the adjacent check nodes are subjected to iterative computation, messages transmitted to the variable nodes by the check nodes are updated by taking Symbol as a unit, and the expression is as follows:
x1＝x0＝outj (4)
wherein the content of the first and second substances,
representing a set of check nodes connected to the current position variable node;
representing a posteriori information of each variable node;
(f) stopping iteration: judging whether the decoding result meets the check, if so, stopping iteration and outputting the decoding result; otherwise, returning to the step (c) to continue the iteration, and adding 1 to the iteration number k until the maximum iteration number MAX is reached, and simultaneously giving a decoding failure mark.
6. The LDPC decoding method according to claim 5, wherein the step (a) comprises preprocessing the initial log-likelihood ratios of Symbol obtained.
7. The LDPC decoding method according to claim 5, wherein the C2V information update of step (C) comprises the following steps:
if V2C _ idx is min1_ idx, abs (C2V) is min2, otherwise abs (C2V) is min 1;
sign(C2V)＝sign(V2C_idx)·global sign；
where V2C _ idx denotes the index of the current V2C information, and sign (V2C _ idx) denotes the sign of the current V2C information.
8. The LDPC decoding method according to claim 6, wherein the LDPC decoding method comprises: the C2V information of step (C), i.e. the first minimum value min1, the second minimum value min2, the index of the first minimum value min1_ idx, and the global symbol in each row; wherein the index of the first minimum value indicates its position in the current row.
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| CN108880564B (en) * | 2018-06-26 | 2021-09-24 | 清华大学 | Low-density parity check code decoding method with cache fault-tolerant capability |
| CN109361403A (en) * | 2018-08-06 | 2019-02-19 | 建荣半导体（深圳）有限公司 | LDPC interpretation method, ldpc decoder and its storage equipment |
| WO2020077596A1 (en) * | 2018-10-18 | 2020-04-23 | 华为技术有限公司 | Decoding method and apparatus for ldpc codes |
| CN111475326A (en) * | 2019-01-23 | 2020-07-31 | 深圳衡宇芯片科技有限公司 | Method for training artificial intelligence to execute decoding program of low density parity check code |
| CN110278000B (en) * | 2019-07-16 | 2020-12-11 | 南京中科晶上通信技术有限公司 | Decoding method for realizing architecture by parallel decoding of LDPC code FPGA based on DVB-S2 standard |
| CN110708078B (en) * | 2019-11-08 | 2023-02-07 | 西安电子科技大学 | Global coupling LDPC code construction method based on base mode graph |
| CN112737599A (en) * | 2021-01-06 | 2021-04-30 | 北京邮电大学 | Self-learning rapid convergence decoding method and device for original pattern LDPC code |
| CN112702066B (en) * | 2020-12-10 | 2024-02-23 | 上海金卓科技有限公司 | LDPC decoding method, device, equipment and medium based on minimum sum algorithm |
| TWI774417B (en) * | 2021-06-11 | 2022-08-11 | 瑞昱半導體股份有限公司 | Decoding method with weight-based adjustment for parameters in algorithm and decoding system thereof |
| CN114006621A (en) * | 2021-11-05 | 2022-02-01 | 中国传媒大学 | Parallel decoding method and system |
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