CN112003611A - Ring oscillator and circuit implementation method - Google Patents
Ring oscillator and circuit implementation method Download PDFInfo
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Abstract
The invention discloses a ring oscillator, which comprises a current source circuit, an amplifying circuit, a frequency trimming device and a ring oscillator circuit formed by connecting phase inverters, wherein the amplifying circuit is connected with the current source circuit; the output end of the current source circuit is connected with the input end of the amplifying circuit; the amplifying circuit comprises a first N-type MOS tube, a second N-type MOS tube and a third N-type MOS tube; the grid electrode of the first N-type MOS tube, the drain electrode of the first N-type MOS tube and the grid electrode of the second N-type MOS tube are connected in parallel; the drain electrode of the second N-type MOS tube is connected with the grid electrode of the third N-type MOS tube in parallel; the source electrode of the second N-type MOS tube is connected with the frequency trimming device in series; and the source electrode of the first N-type MOS tube and the source electrode of the third N-type MOS tube are connected with the input end of the ring oscillator circuit. The invention provides a ring oscillator and a circuit implementation method, which can prevent the output frequency of the ring oscillator from being influenced by power supply voltage.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a ring oscillator and a circuit implementation method.
Background
A ring oscillator is one of the most common circuit blocks in an integrated circuit. The microcontroller chip has the advantages of simple structure, easy integration, low cost and the like, and is widely applied to the microcontroller chip.
The traditional ring oscillator circuit is formed by cascading an odd number of inverters end to end. The circuit structure of the conventional ring oscillator is simple, but the disadvantages thereof are also obvious. Because the oscillation frequency of the conventional ring oscillator is related to the on-resistance, parasitic capacitance and power supply voltage of the mosfet, and these variables are greatly influenced by the ambient temperature, the power supply voltage and the process parameters, the oscillation frequency generally has the disadvantages of low accuracy and large drift along with the temperature. Because of the above disadvantages of conventional ring oscillators, off-chip crystal oscillators have to be used instead in some situations where a high precision clock is required.
Disclosure of Invention
In view of the above technical problems, the present invention provides a ring oscillator and a circuit implementation method thereof, which can prevent the output frequency of the ring oscillator from being affected by the power supply voltage. The technical scheme is as follows:
the embodiment of the invention provides a ring oscillator, which comprises a current source circuit, an amplifying circuit, a frequency trimming device and a ring oscillator circuit formed by connecting phase inverters, wherein the amplifying circuit is connected with the current source circuit;
the output end of the current source circuit is connected with the input end of the amplifying circuit;
the amplifying circuit comprises a first N-type MOS tube, a second N-type MOS tube and a third N-type MOS tube;
the grid electrode of the first N-type MOS tube, the drain electrode of the first N-type MOS tube and the grid electrode of the second N-type MOS tube are connected in parallel;
the drain electrode of the second N-type MOS tube is connected with the grid electrode of the third N-type MOS tube in parallel;
the source electrode of the second N-type MOS tube is connected with the frequency trimming device in series;
and the source electrode of the first N-type MOS tube and the source electrode of the third N-type MOS tube are connected with the input end of the ring oscillator circuit.
Preferably, the current source circuit comprises a bias current source and a current mirror; the bias current source is connected with the current mirror and provides bias current.
As a preferred scheme, the current mirror comprises a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, and a fourth P-type MOS transistor;
the source electrodes of the first P-type MOS tube, the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are all connected with a power supply;
the grids of the first P-type MOS tube, the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are all connected with the anode of the bias current source;
the drain electrode of the first P-type MOS tube is connected with the anode of the bias current source;
and the drain electrodes of the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are all connected with the input end of the amplifying circuit.
As a preferred scheme, the output terminal of the amplifying circuit is connected to the input terminal of the ring oscillator circuit, and specifically includes:
the ring oscillator circuit is formed by connecting odd inverters end to end;
and the input end of the ring oscillator circuit is connected with the source electrode of the first N-type MOS tube and the source electrode of the third N-type MOS tube in parallel.
Preferably, the ring oscillator further comprises an output buffer; the input end of the output buffer is connected with the output end of the ring oscillator circuit.
Preferably, the frequency trimming device is a low temperature coefficient resistor.
Preferably, the frequency trimming device is formed by combining a positive temperature coefficient resistor and a negative temperature coefficient resistor.
Preferably, the frequency trimming device is a field effect transistor.
Preferably, the ratio of the width-to-length ratios of the first N-type MOS transistor, the second N-type MOS transistor, and the third N-type MOS transistor is equal to the ratio of the width-to-length ratios of the second P-type MOS transistor, the third P-type MOS transistor, and the fourth P-type MOS transistor.
In order to solve the same technical problem, an embodiment of the present invention provides a method for implementing a ring oscillator circuit, including:
inputting a power supply voltage and providing a bias current unrelated to the power supply voltage to a first feedback circuit through a current source circuit;
providing an amplified current to a ring oscillator circuit formed by connecting inverters by using a first feedback circuit;
the voltage variation of the first feedback circuit is suppressed with a second feedback circuit, while the input voltage variation of the ring oscillator circuit is suppressed with a third feedback circuit.
Compared with the prior art, the embodiment of the invention has the following beneficial effects:
the invention provides a ring oscillator and a circuit implementation method, wherein the scheme utilizes a first feedback circuit, a second feedback circuit and a third feedback circuit to stabilize the input voltage of a ring oscillator circuit; when the voltage of the ring oscillator circuit is reduced, the current provided for the ring oscillator circuit is increased through the first feedback circuit, and the voltage stability of the ring oscillator circuit is ensured; meanwhile, the voltage change of the first feedback circuit is restrained by the second feedback circuit, and the input voltage change of the ring oscillator circuit is restrained by the third feedback circuit, so that the output frequency is independent of the power supply voltage, and the noise interference resistance and the power supply restraint capability of the ring oscillator are improved.
In addition, the specific scheme of the invention provides bias current irrelevant to power supply voltage to the amplifying circuit by using a current source circuit; the amplifying circuit is composed of a first N-type MOS tube, a second N-type MOS tube and a third N-type MOS tube. In the first feedback circuit, when the voltage of the ring oscillator circuit is reduced, the bias current of the first N-type MOS tube is unchanged, the source voltage is reduced, the grid voltages of the first N-type MOS tube and the second N-type MOS tube are both reduced, and the grid voltage of the third N-type MOS tube is increased, so that the current supplied to the ring oscillator circuit is increased, and the voltage stability of the ring oscillator circuit is maintained; and the second feedback circuit comprises a second N-type MOS tube and a frequency trimming device, the third feedback circuit comprises a third N-type MOS tube and the ring oscillator circuit, and the three feedback loops can maintain the source voltage of the first N-type MOS tube, the source voltage of the second N-type MOS tube, the source voltage of the third N-type MOS tube and the input voltage of the ring oscillator circuit to be equal, so that the output frequency is independent of the power supply voltage.
Drawings
FIG. 1 is a flow chart of a method for implementing a ring oscillator circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a ring oscillator in an embodiment of the present invention;
fig. 3 is a schematic diagram of a feedback loop of a ring oscillator according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention further provides an exemplary embodiment of a method for implementing a ring oscillator circuit, including:
s101, inputting a power supply voltage, and providing a bias current irrelevant to the power supply voltage to a first feedback circuit through a current source circuit;
s102, providing an amplified current for a ring oscillator circuit formed by connecting phase inverters by using a first feedback circuit;
and S103, suppressing the voltage change of the first feedback circuit by using a second feedback circuit, and simultaneously suppressing the input voltage change of the ring oscillator circuit by using a third feedback circuit.
In this scheme, the providing of the amplified current to the ring oscillator circuit by using the first feedback circuit specifically includes:
the first feedback circuit comprises a first N-type MOS tube, a second N-type MOS tube and a third N-type MOS tube;
in this embodiment, the first feedback circuit is a negative feedback loop providing a high gain;
providing bias current for the first N-type MOS tube, the second N-type MOS tube and the third N-type MOS tube; the grid voltage of the first N-type MOS tube is equal to that of the second N-type MOS tube;
when the input voltage of the ring oscillator circuit is reduced and the voltage of the grid electrode and the source electrode of the first N-type MOS tube and the second N-type MOS tube is reduced, the grid electrode voltage of the third N-type MOS tube is increased and the ring oscillator circuit is provided with amplification current through the source electrode of the third N-type MOS tube.
It can be understood that if the odd number of power supply voltages VDD connected in series to form the ring oscillator circuit are instantaneously reduced and the bias current of the first N-type MOS transistor is not changed, the source voltage of the first N-type MOS transistor is reduced, the gate voltages of the first N-type MOS transistor and the second N-type MOS transistor are also reduced, the gate voltage of the third N-type MOS transistor is increased, and the current supplied to the inverter of the ring oscillator circuit is increased, thereby ensuring that the power supply voltage VDD of the inverter ring is stable.
In this embodiment, the suppressing the voltage variation of the first feedback circuit by using the second feedback circuit specifically includes:
suppressing the source voltage of the second N-type MOS tube by using a frequency trimming device; the second feedback circuit is assembled by connecting the drain electrode of the second N-type MOS tube with the drain electrode of a third P-type MOS tube and connecting the source electrode of the second N-type MOS tube with a frequency trimming device; it will be appreciated that the second feedback circuit is a source follower circuit with a feedback resistor; the drain input impedance of the second N-type MOS tube is large, the change of the power supply voltage hardly influences the current of the resistor R1, and the power supply suppression capability is improved.
Preferably, the frequency trimming device is a feedback resistor;
when the source voltage of the second N-type MOS tube is reduced instantly due to interference, the grid-source voltage of the second N-type MOS tube is increased, and the current supplied to the feedback resistor is increased.
Similarly, if the feedback resistor is interfered, the positive end voltage is instantly reduced, the gate source voltage of the second N-type MOS tube is increased, the current provided for the feedback resistor is increased, and the positive end voltage of the feedback resistor is ensured to be recovered to a stable value, so that the anti-noise interference capability can be improved through feedback regulation.
In this scheme, the third feedback circuit is used to suppress the input voltage variation of the ring oscillator circuit, specifically:
and increasing the input impedance of the third feedback circuit by using a third N-type MOS tube. It will be appreciated that the third feedback circuit is a source follower circuit with a feedback resistor; when the power supply voltage changes, the drain input impedance of the third N-type MOS tube is large, the power supply of the inverter ring changes slightly, and the power supply inhibition capacity is improved.
When the power supply of the inverter ring is reduced, the gate-source voltage of the third N-type MOS tube is increased, and the current supplied to the inverter ring is increased, so that the power supply voltage of the inverter ring is kept unchanged.
The invention provides an exemplary embodiment, a ring oscillator, comprising a current source circuit, an amplifying circuit, a frequency trimming device and a ring oscillator circuit formed by connecting phase inverters;
the output end of the current source circuit is connected with the input end of the amplifying circuit; it will be appreciated that the current source circuit also provides a bias current to the amplification circuit.
The adjusting end of the amplifying circuit is connected with the frequency trimming device in series and then grounded, and meanwhile, the output end of the amplifying circuit is connected with the input end of the ring oscillator circuit.
In a first preferred embodiment, the frequency modifier is a low temperature coefficient resistor.
In a second preferred embodiment, the frequency trimming device is formed by combining a positive temperature coefficient resistor and a negative temperature coefficient resistor.
In a third preferred embodiment of the present invention, the frequency modifier is a fet.
The invention provides a specific implementation mode, wherein the current source circuit comprises a bias current source and a current mirror; the bias current source is connected with the current mirror and provides bias current.
Specifically, the current mirror comprises a first P-type MOS tube, a second P-type MOS tube, a third P-type MOS tube and a fourth P-type MOS tube;
the source electrodes of the first P-type MOS tube, the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are all connected with a power supply; it is understood that the power supply herein refers to a positive voltage power supply VCC.
The grids of the first P-type MOS tube, the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are all connected with the anode of the bias current source;
the drain electrode of the first P-type MOS tube is connected with the anode of the bias current source;
the drain electrodes of the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are connected to the input end of the amplifying circuit.
The present invention provides two specific embodiments, wherein the amplifying circuit at least comprises a first follower circuit for stabilizing the voltage of the frequency trimming device, and a second follower circuit for stabilizing the input voltage of the ring oscillator circuit.
Specifically, the amplifying circuit comprises a first N-type MOS tube, a second N-type MOS tube and a third N-type MOS tube;
the grid electrode of the first N-type MOS tube, the drain electrode of the first N-type MOS tube and the grid electrode of the second N-type MOS tube are connected in parallel;
the drain electrode of the second N-type MOS tube is connected with the grid electrode of the third N-type MOS tube in parallel;
and the source electrode of the second N-type MOS tube is connected with the frequency trimming device in series.
It can be understood that the sources of the first N-type MOS transistor and the third N-type MOS transistor are output ends of the amplifying circuit.
Correspondingly, the drains of the second P-type MOS transistor, the third P-type MOS transistor and the fourth P-type MOS transistor are connected to the input terminal of the amplifying circuit, specifically:
the drain electrode of the second P-type MOS tube is connected with the grid electrode of the first N-type MOS tube, the drain electrode of the first N-type MOS tube and the grid electrode of the second N-type MOS tube in parallel;
the drain electrode of the third P-type MOS tube is connected with the drain electrode of the second N-type MOS tube and the grid electrode of the third N-type MOS tube in parallel;
and the drain electrode of the fourth P-type MOS tube is connected with the drain electrode of the third N-type MOS tube.
The invention provides three specific implementation modes, wherein the output end of the amplifying circuit is connected with the input end of the ring oscillator circuit, and the specific implementation modes are as follows:
the ring oscillator circuit is formed by connecting odd inverters end to end;
and the input end of the ring oscillator circuit is connected with the source electrode of the first N-type MOS tube and the source electrode of the third N-type MOS tube in parallel.
The present invention also provides a preferred embodiment, wherein the ring oscillator further comprises an output buffer; the input end of the output buffer is connected with the output end of the ring oscillator circuit.
The output buffer and the gate circuit of the buffer are added, and the anti-interference performance is improved by 10% of power supply voltage. In addition, the gate circuit with the buffer has the advantages of symmetrical output waveform, large alternating voltage gain, narrow bandwidth, small input capacitance and the like.
It should be noted that the bias current source only provides a current bias, and does not affect the oscillation frequency; therefore, the requirement for the precision and the temperature characteristic of the bias current source is not high, and the bias current source can be a positive temperature coefficient current, a negative temperature coefficient current or a zero temperature coefficient current.
Referring to fig. 2, an embodiment of a ring oscillator according to the present invention includes four P-type MOS transistors, three N-type MOS transistors, a resistor, an output buffer, and an odd number of inverters; the odd inverters are connected end to form an oscillation ring.
The source electrodes of the first P-type MOS tube, the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are connected with a power supply VCC; the grid electrodes of the first P-type MOS tube, the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are connected with the drain electrode of the first P-type MOS tube and the anode of a bias current source I1 to form a current source circuit;
the amplifying circuit comprises three N-type MOS tubes; the grid electrode of the first N-type MOS tube, the drain electrode of the first N-type MOS tube, the grid electrode of the second N-type MOS tube and the drain electrode of the second P-type MOS tube are connected; the drain electrode of the second N-type MOS tube, the drain electrode of the third P-type MOS tube and the grid electrode of the third N-type MOS tube are connected; the drain electrode of the fourth P-type MOS tube is connected with the drain electrode of the third N-type MOS tube; the source electrode of the second N-type MOS tube is connected with the positive end of the first resistor;
the odd inverters are connected end to form a ring oscillator circuit, a power supply of the ring oscillator circuit is connected with a source electrode of the first N-type MOS tube and a source electrode of the third N-type MOS tube, and the ring oscillator circuit further comprises odd load capacitors corresponding to the inverters.
The cathode of the bias current source I1, the first resistor, the ground of the odd-numbered end-to-end inverters, the grounding end of the output buffer and the negative ends of the odd-numbered load capacitors are all connected to the ground GND; the positive ends of the odd load capacitors are respectively connected with the output of each stage of inverter; the power end of the output buffer is connected with a power supply VCC, and the input of the output buffer is connected with the outputs of odd end-to-end direction devices.
In the embodiment, the circuit design is simple and the number of electronic devices is small, so that the ring oscillator circuit is simple and practical in overall structure, easy to build and cost-saving.
Further, the output clock frequency of the scheme is analyzed as follows:
the currents of the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are all mirrored from the current of the first P-type MOS tube. Assuming that the current proportional relationship between the currents of the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube and the current proportional relationship between the currents of the first P-type MOS tube are as follows:
wherein WP1、WP2、WP3、WP4The width of a channel of each of the first P-type MOS tube, the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube is respectively greater than the width of the channel of the first P-type MOS tube; l isP1、LP2、LP3、LP4The channel lengths of the first P-type MOS tube, the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are respectively.
Since the current of the first P-type MOS transistor is equal to the bias current source I1, the current values of the second P-type MOS transistor, the third P-type MOS transistor and the fourth P-type MOS transistor are respectively K4*I1、K3*I1、K2*I1。
The expression of the drain current of the MOS tube working in the saturation region is as follows:
therefore, the first and second electrodes are formed on the substrate,
wherein, IDIs drain current, μ is carrier mobility, CoxIs the unit capacitance of the gate oxide layer,
is the width-to-length ratio of MOS tube, VGSIs a gate-source voltage, VTHIs the threshold voltage.
Therefore, the gate-source voltages of the first N-type MOS transistor, the second N-type MOS transistor, and the third N-type MOS transistor are respectively:
the width-to-length ratios of the first N-type MOS tube, the second N-type MOS tube and the third N-type MOS tube are ensured to meet the following proportion:
it is possible to obtain:
VGSN1＝VGSN2＝VGSN3
namely, the gate-source voltages of the first N-type MOS tube, the second N-type MOS tube and the third N-type MOS tube are equal. Since the gate of the first N-type MOS transistor and the gate of the second N-type MOS transistor are connected together, the source voltage of the first N-type MOS transistor and the source voltage of the second N-type MOS transistor are equal, that is, the positive terminal voltage of the first resistor R1 and the power supply voltage VDD of the oscillation ring are equal.
Therefore, in a preferred embodiment of the present invention, the ratio of the width-to-length ratio of the first N-type MOS transistor, the second N-type MOS transistor, and the third N-type MOS transistor is equal to the ratio of the width-to-length ratio of the second P-type MOS transistor, the third P-type MOS transistor, and the fourth P-type MOS transistor.
Since the power consumed by the device can be expressed as:
where P is the power, V is the voltage across the device, I is the current flowing through the device, and R is the device resistance.
Therefore, the first and second electrodes are formed on the substrate,
the power dissipated by the first resistor R1 is:
and the power consumed by the oscillation ring is:
PRING＝VDD(K2+K4)I1＝CVDD 2f
wherein, PR1Is the power consumption, P, of the resistor R1RINGIs the power consumption of the oscillating ring, VDDIs the power supply voltage of the oscillation ring, C is the load capacitance of the inverter at each stage of the oscillation ring, R is the resistance of the resistor R1, and f is the oscillation frequency.
According to the above PR1And PRINGThe expression of (c) may be:
wherein, K2、K3、K4Is a constant in design.
From the expression of the clock oscillation frequency, the clock frequency is independent of the power supply voltage, independent of the MOS tube process parameters, and only dependent on the resistor R1 and the load capacitor C of each stage of the inverter loop. The oscillation frequency is related to the process deviation of the resistor and the capacitor at normal temperature, and the oscillation frequency can be adjusted to an accurate frequency value through the adjusting resistor R1. Because the temperature coefficient of the capacitor is very small, the resistor R1 can use low temperature drift resistance or use different temperature coefficient resistor combination, so the scheme can generate the accurate oscillation frequency with very low temperature coefficient.
Referring to fig. 3, in the present embodiment, the first feedback circuit is a feedback loop including a first N-type MOS transistor, a second N-type MOS transistor, a third N-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a connection relationship thereof, and an odd number of ring oscillator circuits formed by serially connecting a first inverter INV1 to an nth inverter INV.
Specifically, the drain of the third P-type MOS transistor is connected to the drain of the second N-type MOS transistor, and the source of the second N-type MOS transistor is connected to the resistor R1.
Specifically, the drain of the fourth P-type MOS transistor is connected to the drain of the third N-type MOS transistor, and the source of the third N-type MOS transistor is connected to the input terminal (i.e., VDD) of the ring oscillator circuit.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A ring oscillator is characterized by comprising a current source circuit, an amplifying circuit, a frequency trimming device and a ring oscillator circuit formed by connecting phase inverters;
the output end of the current source circuit is connected with the input end of the amplifying circuit;
the amplifying circuit comprises a first N-type MOS tube, a second N-type MOS tube and a third N-type MOS tube;
the grid electrode of the first N-type MOS tube, the drain electrode of the first N-type MOS tube and the grid electrode of the second N-type MOS tube are connected in parallel;
the drain electrode of the second N-type MOS tube is connected with the grid electrode of the third N-type MOS tube in parallel;
the source electrode of the second N-type MOS tube is connected with the frequency trimming device in series;
and the source electrode of the first N-type MOS tube and the source electrode of the third N-type MOS tube are connected with the input end of the ring oscillator circuit.
2. The ring oscillator of claim 1, wherein the current source circuit comprises a bias current source and a current mirror; the bias current source is connected with the current mirror and provides bias current.
3. The ring oscillator of claim 2, wherein the current mirror comprises a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a fourth P-type MOS transistor;
the source electrodes of the first P-type MOS tube, the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are all connected with a power supply;
the grids of the first P-type MOS tube, the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are all connected with the anode of the bias current source;
the drain electrode of the first P-type MOS tube is connected with the anode of the bias current source;
and the drain electrodes of the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are all connected with the input end of the amplifying circuit.
4. The ring oscillator of claim 1, wherein the output of the amplification circuit is connected to the input of the ring oscillator circuit, specifically:
the ring oscillator circuit is formed by connecting odd inverters end to end;
and the input end of the ring oscillator circuit is connected with the source electrode of the first N-type MOS tube and the source electrode of the third N-type MOS tube in parallel.
5. The ring oscillator of claim 1, further comprising an output buffer; the input end of the output buffer is connected with the output end of the ring oscillator circuit.
6. The ring oscillator of claim 1 wherein the frequency trimmer is a low temperature coefficient of resistance.
7. The ring oscillator of claim 1 wherein the frequency trimmer is a combination of a positive temperature coefficient resistor and a negative temperature coefficient resistor.
8. The ring oscillator of claim 1 wherein the frequency trimmer is a field effect transistor.
9. The ring oscillator of claim 3, wherein the ratio of the width-to-length ratios of the first N-type MOS transistor, the second N-type MOS transistor, and the third N-type MOS transistor is equal to the ratio of the width-to-length ratios of the second P-type MOS transistor, the third P-type MOS transistor, and the fourth P-type MOS transistor.
10. A method for implementing a ring oscillator circuit, comprising:
inputting a power supply voltage and providing a bias current unrelated to the power supply voltage to a first feedback circuit through a current source circuit;
providing an amplified current to a ring oscillator circuit formed by connecting inverters by using a first feedback circuit;
the voltage variation of the first feedback circuit is suppressed with a second feedback circuit, while the input voltage variation of the ring oscillator circuit is suppressed with a third feedback circuit.
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| CN117118219A (en) * | 2023-10-08 | 2023-11-24 | 西安航天民芯科技有限公司 | On-chip integrated soft start circuit |
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