CN112003577A

CN112003577A - High-precision switch capacitance type differential measurement circuit

Info

Publication number: CN112003577A
Application number: CN202010887172.0A
Authority: CN
Inventors: 张军; 庄志伟; 费俊驰; 董渊; 庄健
Original assignee: Wuxi Indie Microelectronics Technology Co Ltd
Current assignee: Wuxi Indie Microelectronics Technology Co Ltd
Priority date: 2020-08-28
Filing date: 2020-08-28
Publication date: 2020-11-27
Anticipated expiration: 2040-08-28
Also published as: CN112003577B

Abstract

The invention discloses a high-precision switch capacitance type differential measurement circuit, relating to the technical field of electronic circuits, wherein a switch capacitance circuit is arranged between a differential circuit and a differential input end, the switch capacitance circuit samples an input signal according to a first clock signal and provides the input signal for the differential circuit or enters a self-common mode to keep the common mode voltage unchanged, the switch capacitance circuit can isolate the interference of the input signal common mode voltage to a later-stage differential circuit, and simultaneously ensures that the input common mode voltage of an operational amplifier in the later-stage differential circuit is invariable and is input common mode bias voltage and voltage can be configured, thereby leading the operational amplifier to work in a more proper input common mode range, solving the overpressure problem caused by overlarge input common mode change of the operational amplifier, and reducing the requirements on the common mode rejection ratio and the linearity index of the operational amplifier, the design difficulty of the operational amplifier is reduced, and the reliability and the measurement precision of the measurement circuit are improved.

Description

High-precision switch capacitance type differential measurement circuit

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a high-precision switched capacitor type differential measurement circuit.

Background

Differential measurement circuits are generally required to have several characteristics: the input impedance is high so as not to influence the tested signal; the input common mode in a larger range can be tolerated, and the measurement accuracy of differential signals is ensured; the influence of the self-input offset of the operational amplifier on the measurement precision needs to be eliminated; it is desirable to keep the input common mode of the operational amplifier as stable as possible. A circuit structure diagram of a conventional switched capacitor type differential measurement circuit is shown in fig. 1, where ph1 and ph2 are non-overlapping (non-overlapping) clock signals, s1a, s1b, s2a, s2b, s3a, s3b, s4a, s4b, s5a, s5b, s6a, and s6b are all switches, and can be implemented by using a transmission gate circuit in practice, where s1a (ph2) in fig. 1 means that the switch s1a is controlled by the clock signal ph2 and is turned on during a high level period and is turned off during a low level period of the clock signal ph2, and s2a (ph1) means that the switch s2a is controlled by the clock signal ph1 and is turned on during a high level period and is turned off during a low level period of the clock signal ph1, and the control conditions of other switches can be analogized. C1a, C1b, C2a, C2b, C3a, and C3b are all capacitors, and may be implemented by MIM capacitors or MOM capacitors in practice. OPA1 is a fully differential operational amplifier, Vip/Vin is the input signal, Vop/Von is the output signal, Vi _ Vcm is the input common mode bias voltage, and Vo _ Vcm is the output common mode bias voltage.

In the circuit configuration shown in fig. 1, the following operation modes are included:

(1) reset/hold mode: during the periods when ph1 is high and ph2 is low, the upper plate of C1a/C1b switches from the input signal Vip/Vin to the input common mode bias voltage Vi _ Vcm (s1a/s1b is off and s2a/s2b is on). The lower plate of C3a/C3b switches from the input common mode bias voltage Vi _ Vcm to the voltage v1a/v1b of the lower plate of C2a/C2b (s3a/s3b is on, s4a/s4b is off). At the same time, the upper plate of C2a/C2b switches from the output signal Vop/Von to the output common mode bias voltage Vo _ Vcm (s5a/s5b off, s6a/s6b on). At this time, the input offset of the fully differential OPA1 is stored on the lower plates v1a and v1b of the capacitors C1a/C2a and C1b/C2b, and the offset voltage is cancelled when the subsequent circuit is working normally, so the input offset of the fully differential OPA1 itself does not affect the precision of the differential measurement circuit, which is one of the advantages of the switched capacitor type amplification circuit.

(2) evaluation mode: during periods when ph2 is high and ph1 is low, the upper plate of C1a/C1b switches from the input common mode bias voltage Vi _ Vcm to the input signal Vip/Vin, which is sampled (s1a/s1b on and s2a/s2b off). The lower plate of C3a/C3b is switched from v1a/v1b to the input common mode bias voltage Vi _ Vcm, and at the moment, the lower plate v1a/v1b of C2a/C2b is floated (s3a/s3b is turned off, and s4a/s4b is turned on). The upper plate of C2a/C2b switches from the output common mode bias voltage Vo _ Vcm to the output signal Vop/Von (s5a/s5b on, s6a/s6b off). At this time, the fully differential operational amplifier OPA1 forms an inverting amplifier through C1a/C2a and C1b/C2b, and finally outputs an effective value Vop/Von after the falling edge of ph2 comes.

(3) Other modes: ph1 and ph2 are both low (for a very short period of time), Vop/Von maintains the last active output. ph1 and ph2 are both high, which is not allowed to happen, and ph1 and ph2 are designed to be non-overlapping clocks to ensure that this does not happen.

However, the switched capacitor type differential measurement circuit has the following problems:

1. as can be seen from the above description of the operation principle, although the input offset of the fully differential operational amplifier OPA1 can be cancelled, the input common mode of the fully differential operational amplifier OPA1 changes with the change of the input signal, and when the common mode voltage of the input signal Vip/Vin changes greatly, the fully differential operational amplifier OPA1 is required to be an input rail-to-rail (inputailtorail) operational amplifier, which makes the design of the operational amplifier more difficult. This circuit fails particularly when the common mode voltage of the input signal Vip/Vin is far beyond the normal operating voltage of the operational amplifier, such as when the common mode voltage of the input signal Vip/Vin is up to 20V, while the fully differential operational amplifier OPA1 operates at 3.3V normal voltage.

2. Since the input common mode of the fully differential operational amplifier OPA1 cannot be constant (or cannot be changed within a small range), it is necessary that the fully differential operational amplifier OPA1 has a high common mode rejection ratio and linearity index, and it is known that the design difficulty of such an operational amplifier is very large.

Disclosure of Invention

The inventor provides a high-precision switched capacitor type differential measurement circuit aiming at the problems and technical requirements, and the technical scheme of the invention is as follows:

a high-precision switched capacitor type differential measurement circuit comprises a differential circuit and a switched capacitor circuit; the differential circuit at least comprises an operational amplifier, a third capacitor, a fourth switch and a fifth switch, wherein the non-inverting input end of the operational amplifier is connected with the lower polar plate of the third capacitor, the upper polar plate of the third capacitor is connected with the first input end of the differential circuit, and the first input end of the differential circuit is also connected with an input common-mode bias voltage through the fourth switch; the inverting input end of the operational amplifier is connected with the lower pole plate of the fourth capacitor, the upper pole plate of the fourth capacitor is connected with the second input end of the differential circuit, and the second input end of the differential circuit is also connected with an input common-mode bias voltage through a fifth switch; the fourth switch and the fifth switch are both controlled by the first clock signal;

the first input end and the second input end of the differential circuit are connected with the two differential input ends of the high-precision switch capacitance type differential measurement circuit through a switch capacitance circuit to obtain input signals, and the switch capacitance circuit at least comprises a capacitor and a switch controlled by a first clock signal;

when the first clock signal is at a high level, the switched capacitor circuit samples the input signal and provides the input signal to the differential circuit, the fourth switch and the fifth switch are both closed, and the voltages of the upper pole plates of the third capacitor and the fourth capacitor are switched to input common-mode bias voltage;

when the first clock signal is at a low level, the switched capacitor circuit enters a self-common mode and the common-mode voltage of the first input end and the second input end of the differential circuit is kept as an input common-mode bias voltage.

The switch capacitor circuit comprises a first switch, a second switch, a third switch, a first capacitor and a second capacitor, wherein one end of the first switch is connected with one differential input end of the high-precision switch capacitor type differential measurement circuit, the other end of the first switch is connected with a lower pole plate of the first capacitor, an upper pole plate of the first capacitor is connected with a first input end of the differential circuit, one end of the second switch is connected with the other differential input end of the high-precision switch capacitor type differential measurement circuit, the other end of the second switch is connected with a lower pole plate of the second capacitor, and an upper pole plate of the second capacitor is connected with a second input end of the differential circuit; the lower pole plate of the first capacitor is connected with the lower pole plate of the second capacitor through a third switch; the first switch and the second switch are both controlled by a first clock signal, the third switch is controlled by a second clock signal, and the second clock signal and the first clock signal are non-overlapping clock signals.

The further technical scheme is that when a first clock signal is switched to a high level and a second clock signal is switched to a low level, a first switch and a second switch are switched to be closed, a third switch is switched to be opened, a lower pole plate of a first capacitor and a lower pole plate of a second capacitor are switched from a short-circuit state to obtain an input signal, the input signal is sampled and provided for a differential circuit, and a first input end and a second input end of the differential circuit are switched to input common-mode bias voltage.

The further technical scheme is that when a first clock signal is switched to a low level and a second clock signal is switched to a high level, a first switch and a second switch are switched to be off, a third switch is switched to be on, a lower pole plate of a first capacitor and a lower pole plate of a second capacitor are switched to be in a short circuit state, a switched capacitor circuit enters a self common mode, common mode voltages of the lower pole plate of the first capacitor and the lower pole plate of the second capacitor before and after switching of the switches are unchanged, and the common mode voltages of a first input end and a second input end of a differential circuit are kept as input common mode bias voltages.

The differential circuit comprises a differential circuit, a high-precision switch capacitor type differential measurement circuit and a differential circuit, wherein the differential circuit comprises a differential amplifier and a differential circuit, the differential amplifier comprises two input ends and two output ends, and the two output ends of the differential amplifier are respectively connected with the two differential output ends of the high-precision switch capacitor type differential measurement circuit;

the non-inverting input end of the fully differential operational amplifier is further connected with an input common-mode bias voltage through a sixth switch and a seventh switch in sequence; the non-inverting input end of the fully differential operational amplifier is also connected with the lower pole plate of a fifth capacitor, the upper pole plate of the fifth capacitor is connected with the output common-mode bias voltage through an eighth switch, the upper pole plate of the fifth capacitor is also connected with the inverting output end of the fully differential operational amplifier through a ninth switch, the common end of the sixth switch and the seventh switch is connected with the lower pole plate of the sixth capacitor, and the upper pole plate of the sixth capacitor is connected with the inverting output end of the fully differential operational amplifier;

the inverting input end of the fully differential operational amplifier is also connected with an input common-mode bias voltage through a tenth switch and an eleventh switch in sequence; the inverting input end of the fully differential operational amplifier is also connected with a lower polar plate of a seventh capacitor, the upper polar plate of the seventh capacitor is connected with an output common-mode bias voltage through a twelfth switch, the upper polar plate of the seventh capacitor is also connected with the in-phase output end of the fully differential operational amplifier through a thirteenth switch, the common end of the tenth switch and the eleventh switch is connected with the lower polar plate of an eighth capacitor, and the upper polar plate of the eighth capacitor is connected with the in-phase output end of the fully differential operational amplifier;

the sixth switch, the eighth switch, the tenth switch and the twelfth switch are all controlled by a first clock signal, the seventh switch, the ninth switch, the eleventh switch and the thirteenth switch are all controlled by a second clock signal, and the second clock signal and the first clock signal are non-overlapping clock signals.

The differential circuit comprises a differential circuit, a high-precision switch capacitance type differential measurement circuit, a differential circuit and a control circuit, wherein the differential circuit comprises a high-precision switch capacitance type differential measurement circuit, a high-precision switch capacitance type differential measurement circuit and a differential circuit, wherein an operational amplifier in the differential circuit is a single-ended output operational amplifier which comprises two input ends and an output end;

the non-inverting input end of the single-ended output operational amplifier is further connected with an input common-mode bias voltage through a sixth switch and a seventh switch in sequence; the non-inverting input end of the single-ended output operational amplifier is also connected with a lower pole plate of a fifth capacitor, the upper pole plate of the fifth capacitor is grounded through an eighth switch and a ninth switch respectively, the common end of a sixth switch and a seventh switch is connected with the lower pole plate of a sixth capacitor, and the upper pole plate of the sixth capacitor is grounded;

the inverting input end of the single-ended output operational amplifier is also connected with an input common-mode bias voltage through a tenth switch and an eleventh switch in sequence; the inverting input end of the single-ended output operational amplifier is also connected with a lower pole plate of a seventh capacitor, an upper pole plate of the seventh capacitor is grounded through a twelfth switch, an upper pole plate of the seventh capacitor is also connected with the output end of the single-ended output operational amplifier through a thirteenth switch, the common end of the tenth switch and the eleventh switch is connected with a lower pole plate of an eighth capacitor, and an upper pole plate of the eighth capacitor is connected with the output end of the single-ended output operational amplifier;

The beneficial technical effects of the invention are as follows:

the application discloses a high-precision switched-capacitor type differential measurement circuit, which is connected with a switched-capacitor circuit between a differential circuit and a differential input terminal, the interference of the common-mode voltage of the input signal to the post-stage differential circuit can be cut off through the switching of the switch state in the switch capacitor circuit and the action of the capacitor, meanwhile, the input common-mode voltage of the operational amplifier in the later-stage differential circuit is ensured to be constant and not to be changed into the input common-mode bias voltage and the voltage can be configured, therefore, the operational amplifier works in a relatively proper input common mode range, the problem of overvoltage caused by overlarge input common mode change of the operational amplifier in the traditional switched capacitor type differential measurement circuit is solved, the requirements on the common mode rejection ratio and linearity index of the operational amplifier are reduced, the design difficulty of the operational amplifier is reduced, and the reliability and measurement precision of the measurement circuit are improved.

Drawings

Fig. 1 is a circuit configuration diagram of a conventional switched capacitor type differential measurement circuit.

Fig. 2 is a circuit configuration diagram of the high-precision switched capacitor type differential measurement circuit disclosed in the present application.

Fig. 3 is another circuit configuration diagram of the high-precision switched capacitor type differential measurement circuit disclosed in the present application.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The present application discloses a high-precision switched capacitor type differential measurement circuit, please refer to fig. 2 and 3, which includes a differential circuit and a switched capacitor circuit. The differential circuit at least comprises an operational amplifier OPA1, a third capacitor C3, a fourth capacitor C4, a fourth switch k4 and a fifth switch k5, wherein the non-inverting input end of the operational amplifier OPA1 is connected with the lower plate of the third capacitor C3, the upper plate of the third capacitor C3 is connected with the first input end (v 2a in the figure) of the differential circuit, and the first input end of the differential circuit is also connected with an input common-mode bias voltage Vi _ Vcm through a fourth switch k 4. The inverting input terminal of the operational amplifier OPA1 is connected to the lower plate of the fourth capacitor C4, the upper plate of the fourth capacitor C4 is connected to the second input terminal of the differential circuit (at v2b in the figure), and the second input terminal of the differential circuit is further connected to the input common mode bias voltage Vi _ Vcm through the fifth switch k 5. The fourth switch k4 and the fifth switch k5 are both controlled by the first clock signal ph1, and the reference numeral k4(ph1) in the figure indicates that the fourth switch k4 is controlled by the first clock signal ph1, and so on. The individual switches in this application may be implemented by transmission gate circuits.

The first input end and the second input end of the differential circuit are connected with the two differential input ends of the high-precision switch capacitance type differential measurement circuit through a switch capacitor circuit to obtain an input signal Vip/Vin, and the switch capacitor circuit at least comprises a capacitor and a switch controlled by a first clock signal ph 1. When the first clock signal ph1 is at high level, the switched capacitor circuit samples the input signal Vip/Vin and provides it to the differential circuit, the fourth switch k4 and the fifth switch k5 are both closed, and the upper plate voltages of the third capacitor C3 and the fourth capacitor C4 are switched to the input common mode bias voltage Vi _ Vcm, i.e., from v2a/v2b to Vi _ Vcm. When the first clock signal is at a low level, the switched capacitor circuit enters a self-common mode and the common-mode voltage of the first input terminal and the second input terminal of the differential circuit is kept as the input common-mode bias voltage Vi _ Vcm. Therefore, the switched capacitor circuit can isolate the interference of the input signal Vip/Vin common mode voltage to the post-stage circuit, and simultaneously ensure that the input common mode voltage of the operational amplifier OPA1 is constant, namely Vi _ Vcm, and the voltage can be a bias voltage designed in advance, so that the operational amplifier OPA1 works in a more proper input common mode range.

Referring to fig. 2 and 3, the switched capacitor circuit in this application includes a first switch k1, a second switch k2, a third switch k3, a first capacitor C1 and a second capacitor C2, one end of the first switch k1 is connected to one differential input end (Vip in the figure) of the high-precision switched capacitor type differential measurement circuit, the other end of the first switch k1 is connected to a lower plate of the first capacitor C1, and an upper plate of the first capacitor C1 is connected to the first input end of the differential circuit. One end of the second switch k2 is connected to the other differential input end (Vin in the figure) of the high-precision switched capacitor type differential measurement circuit, the other end is connected to the lower plate of the second capacitor C2, and the upper plate of the second capacitor C2 is connected to the second input end of the differential circuit. The lower plate of the first capacitor C1 and the lower plate of the second capacitor C2 are connected through a third switch k 3. The first switch k1 and the second switch k2 are both controlled by a first clock signal ph1, the third switch k3 is controlled by a second clock signal ph2, and the second clock signal ph2 and the first clock signal ph1 are non-overlapping clock signals.

Based on the circuit structure, the working principle of the high-precision switched capacitor type differential measurement circuit is as follows:

(1) sampling mode: when the first clock signal ph1 is switched to a high level and the second clock signal ph2 is switched to a low level, the first switch k1 and the second switch k2 are switched to be closed, the third switch k3 is switched to be opened, the lower plate of the first capacitor C1 and the lower plate of the second capacitor C2 are switched from a short-circuited state to obtain the input signal Vip/Vin, and the input signal Vip/Vin is sampled and supplied to the differential circuit. In the differential circuit, the fourth switch k4 and the fifth switch k5 are switched to be closed, the first input terminal and the second input terminal of the differential circuit are switched to the input common mode bias voltage Vi _ Vcm, and the subsequent differential circuit operates in reset/hold mode, storing the input offset voltage of the operational amplifier OPA 1.

(2) evaluation mode: when the first clock signal ph1 is switched to a low level and the second clock signal ph2 is switched to a high level, the first switch k1 and the second switch k2 are switched to an open state, the third switch k3 is switched to a closed state, the lower plate of the first capacitor C1 and the lower plate of the second capacitor C2 are switched to a short-circuited state from the acquired input signal Vip/Vin, the switched capacitor circuit enters a self-common mode, the common-mode voltages of the lower plate of the first capacitor C1 and the lower plate of the second capacitor C2 before and after switching are unchanged, the common-mode voltages of the first input end and the second input end of the differential circuit are kept unchanged as the input common-mode bias voltage Vi _ Vcm, namely the common-mode voltage of v2a/v2b is constant and is not changed into Vi _ Vcm, and the common-mode voltage of v1a/v1b is also constant and not changed into Vi _ Vcm, so that the problem of excessive overvoltage change of the operational amplifier OPA1 and the high common-mode ratio required for suppressing the common-mode voltage is solved . The subsequent differential circuit operates in evaluation mode, and the differential output end of the high-precision switched-capacitor type differential measurement circuit outputs effective value after the falling edge of the second clock signal ph2 arrives.

In the present application, the differential circuit may be a measurement circuit based on a fully differential operational amplifier, or may be a measurement circuit based on a normal operational amplifier:

as shown in fig. 2, when the operational amplifier OPA1 in the differential circuit is a fully differential operational amplifier, the fully differential operational amplifier OPA1 includes two input terminals and two output terminals, and the two output terminals of the fully differential operational amplifier OPA1 are respectively connected to the two differential output terminals Vop/Von of the high-precision switched capacitor type differential measurement circuit. The non-inverting input terminal of the fully differential operational amplifier OPA1 is also connected to the input common mode bias voltage Vi _ Vcm through the sixth switch k6 and the seventh switch k7 in this order. The non-inverting input terminal of the fully differential operational amplifier OPA1 is further connected to the lower plate of a fifth capacitor C5, the upper plate of the fifth capacitor C5 is connected to the output common mode bias voltage Vo _ Vcm through an eighth switch k8, the upper plate of the fifth capacitor C5 is further connected to the inverting output terminal of the fully differential operational amplifier OPA1 through a ninth switch k9, the common terminal of the sixth switch k6 and the seventh switch k7 is connected to the lower plate of a sixth capacitor C6, and the upper plate of the sixth capacitor C6 is connected to the inverting output terminal of the fully differential operational amplifier OPA 1. The inverting input terminal of the fully differential operational amplifier OPA1 is also connected to the input common mode bias voltage Vi _ Vcm through the tenth switch k10 and the eleventh switch k11 in this order. The inverting input terminal of the fully differential operational amplifier OPA1 is further connected to the lower plate of a seventh capacitor C7, the upper plate of the seventh capacitor C7 is connected to the output common mode bias voltage Vo _ Vcm through a twelfth switch k12, the upper plate of the seventh capacitor C7 is further connected to the non-inverting output terminal of the fully differential operational amplifier OPA1 through a tenth switch k13, the common terminal of the tenth switch k10 and the eleventh switch k11 is connected to the lower plate of an eighth capacitor C8, and the upper plate of the eighth capacitor C8 is connected to the non-inverting output terminal of the fully differential operational amplifier OPA 1. The sixth switch k6, the eighth switch k8, the tenth switch k10 and the twelfth switch k12 are all controlled by a first clock signal ph1, and the seventh switch k7, the ninth switch k9, the eleventh switch k11 and the thirteenth switch k13 are all controlled by a second clock signal ph 2.

When the operational amplifier OPA1 in the differential circuit is a single-ended output operational amplifier, as shown in fig. 3, the single-ended output operational amplifier OPA1 includes two input terminals and one output terminal, and the output terminal of the single-ended output operational amplifier OPA1 is connected to the differential output terminal Vop of the high-precision switched-capacitor type differential measurement circuit, similar to the circuit configuration of fig. 2 described above, and therefore denoted by the same reference numerals. The non-inverting input terminal of the single-ended output operational amplifier OPA1 is also connected to the input common mode bias voltage Vi _ Vcm through the sixth switch k6 and the seventh switch k7 in this order. The non-inverting input end of the single-ended output operational amplifier OPA1 is further connected to the lower plate of a fifth capacitor C5, the upper plate of the fifth capacitor C5 is grounded through an eighth switch k8 and a ninth switch k9, respectively, the common end of a sixth switch k6 and a seventh switch k7 is connected to the lower plate of a sixth capacitor C6, and the upper plate of the sixth capacitor C6 is grounded Gnd. The inverting input terminal of the single-ended output operational amplifier OPA1 is also connected to the input common mode bias voltage Vi _ Vcm through the tenth switch k10 and the eleventh switch k11 in this order. The inverting input terminal of the single-ended output operational amplifier OPA1 is further connected to the lower plate of a seventh capacitor C7, the upper plate of the seventh capacitor C7 is grounded through a twelfth switch k12, and the upper plate of the seventh capacitor C7 is further connected to the output terminal Vop of the single-ended output operational amplifier OPA1 through a tenth switch k 13. The common terminal of the tenth switch k10 and the eleventh switch k11 is connected to the lower plate of the eighth capacitor C8, and the upper plate of the eighth capacitor C8 is connected to the output terminal of the single-ended output operational amplifier OPA 1. Similarly, in the structure shown in fig. 2, the sixth switch k6, the eighth switch k8, the tenth switch k10 and the twelfth switch k12 are all controlled by the first clock signal ph1, and the seventh switch k7, the ninth switch k9, the eleventh switch k11 and the thirteenth switch k13 are all controlled by the second clock signal ph 2.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims

1. A high-precision switched capacitor type differential measurement circuit is characterized by comprising a differential circuit and a switched capacitor circuit; the differential circuit at least comprises an operational amplifier, a third capacitor, a fourth switch and a fifth switch, wherein the non-inverting input end of the operational amplifier is connected with the lower polar plate of the third capacitor, the upper polar plate of the third capacitor is connected with the first input end of the differential circuit, and the first input end of the differential circuit is also connected with an input common-mode bias voltage through the fourth switch; the inverting input end of the operational amplifier is connected with the lower pole plate of the fourth capacitor, the upper pole plate of the fourth capacitor is connected with the second input end of the differential circuit, and the second input end of the differential circuit is also connected with the input common-mode bias voltage through the fifth switch; the fourth switch and the fifth switch are both controlled by a first clock signal;

the first input end and the second input end of the differential circuit are connected with the two differential input ends of the high-precision switched capacitor type differential measurement circuit through the switched capacitor circuit to obtain input signals, and the switched capacitor circuit at least comprises a capacitor and a switch controlled by the first clock signal;

when the first clock signal is at a high level, the switched capacitor circuit samples the input signal and provides the input signal to the differential circuit, the fourth switch and the fifth switch are both closed, and the voltages of the upper plates of the third capacitor and the fourth capacitor are switched to the input common mode bias voltage;

when the first clock signal is at a low level, the switched capacitor circuit enters a self-common mode and the common-mode voltage of the first input end and the second input end of the differential circuit is kept at the input common-mode bias voltage.

2. The high-precision switched-capacitor differential measurement circuit according to claim 1, wherein the switched-capacitor circuit comprises a first switch, a second switch, a third switch, a first capacitor and a second capacitor, wherein one end of the first switch is connected to one differential input terminal of the high-precision switched-capacitor differential measurement circuit, the other end of the first switch is connected to a lower plate of the first capacitor, an upper plate of the first capacitor is connected to the first input terminal of the differential circuit, one end of the second switch is connected to the other differential input terminal of the high-precision switched-capacitor differential measurement circuit, the other end of the second switch is connected to a lower plate of the second capacitor, and an upper plate of the second capacitor is connected to the second input terminal of the differential circuit; the lower pole plate of the first capacitor is connected with the lower pole plate of the second capacitor through the third switch; the first switch and the second switch are both controlled by the first clock signal, the third switch is controlled by the second clock signal, and the second clock signal and the first clock signal are non-overlapping clock signals.

3. The high accuracy switched capacitor differential measurement circuit of claim 2, wherein when the first clock signal is switched to a high level and the second clock signal is switched to a low level, the first switch and the second switch are switched to be closed, the third switch is switched to be open, the lower plate of the first capacitor and the lower plate of the second capacitor are switched from a shorted state to obtain the input signal, the input signal is sampled and provided to the differential circuit, and the first input terminal and the second input terminal of the differential circuit are switched to the input common mode bias voltage.

4. The high-precision switched-capacitor differential measurement circuit according to claim 2, wherein when the first clock signal is switched to a low level and the second clock signal is switched to a high level, the first switch and the second switch are switched to be off, the third switch is switched to be on, the lower plate of the first capacitor and the lower plate of the second capacitor are switched to be in a short circuit state, the switched capacitor circuit enters a self-common mode, a common-mode voltage of the lower plate of the first capacitor and the lower plate of the second capacitor before and after switching is unchanged, and a common-mode voltage of the first input terminal and the second input terminal of the differential circuit is maintained as the input common-mode bias voltage.

5. The high-precision switched capacitor differential measurement circuit according to any of claims 1-4, wherein the operational amplifier of the differential circuit is a fully differential operational amplifier, the fully differential operational amplifier comprises two input terminals and two output terminals, and the two output terminals of the fully differential operational amplifier are respectively connected to the two differential output terminals of the high-precision switched capacitor differential measurement circuit;

the non-inverting input end of the fully differential operational amplifier is further connected with the input common-mode bias voltage through a sixth switch and a seventh switch in sequence; the non-inverting input end of the fully differential operational amplifier is further connected with a lower pole plate of a fifth capacitor, the upper pole plate of the fifth capacitor is connected with an output common-mode bias voltage through an eighth switch, the upper pole plate of the fifth capacitor is further connected with the inverting output end of the fully differential operational amplifier through a ninth switch, the common end of the sixth switch and the seventh switch is connected with the lower pole plate of the sixth capacitor, and the upper pole plate of the sixth capacitor is connected with the inverting output end of the fully differential operational amplifier;

the inverting input end of the fully differential operational amplifier is further connected with the input common mode bias voltage through a tenth switch and an eleventh switch in sequence; the inverting input end of the fully differential operational amplifier is further connected with a lower pole plate of a seventh capacitor, an upper pole plate of the seventh capacitor is connected with the output common-mode bias voltage through a twelfth switch, the upper pole plate of the seventh capacitor is further connected with the non-inverting output end of the fully differential operational amplifier through a tenth switch, a common end of the tenth switch and the eleventh switch is connected with a lower pole plate of an eighth capacitor, and an upper pole plate of the eighth capacitor is connected with the non-inverting output end of the fully differential operational amplifier;

the sixth switch, the eighth switch, the tenth switch and the twelfth switch are all controlled by the first clock signal, the seventh switch, the ninth switch, the eleventh switch and the thirteenth switch are all controlled by the second clock signal, and the second clock signal and the first clock signal are non-overlapping clock signals.

6. The high-precision switched-capacitor differential measurement circuit of any of claims 1-4, wherein the operational amplifier of the differential circuit is a single-ended output operational amplifier, the single-ended output operational amplifier having two input terminals and an output terminal, the output terminal of the single-ended output operational amplifier being connected to the differential output terminal of the high-precision switched-capacitor differential measurement circuit;

the non-inverting input end of the single-ended output operational amplifier is further connected with the input common-mode bias voltage through a sixth switch and a seventh switch in sequence; the non-inverting input end of the single-ended output operational amplifier is further connected with a lower pole plate of a fifth capacitor, an upper pole plate of the fifth capacitor is grounded through an eighth switch and a ninth switch respectively, a common end of the sixth switch and a common end of the seventh switch are connected with a lower pole plate of a sixth capacitor, and an upper pole plate of the sixth capacitor is grounded;

the inverting input end of the single-ended output operational amplifier is further connected with the input common-mode bias voltage through a tenth switch and an eleventh switch in sequence; the inverting input end of the single-ended output operational amplifier is further connected with a lower pole plate of a seventh capacitor, an upper pole plate of the seventh capacitor is grounded through a twelfth switch, an upper pole plate of the seventh capacitor is further connected with the output end of the single-ended output operational amplifier through a thirteenth switch, a common end of the tenth switch and the eleventh switch is connected with a lower pole plate of an eighth capacitor, and an upper pole plate of the eighth capacitor is connected with the output end of the single-ended output operational amplifier;