CN113452368A - Capacitance-voltage conversion circuit and application system - Google Patents
Capacitance-voltage conversion circuit and application system Download PDFInfo
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Abstract
The invention provides a capacitance-voltage conversion circuit, which comprises a first-stage conversion module and a second-stage conversion module, wherein the first-stage conversion module and the second-stage conversion module have the same circuit structure and respectively comprise a differential amplifier, two compensation capacitors and two holding capacitors; one ends of the two compensation capacitors are connected with a differential input signal and are respectively connected with a reference voltage through the first switch, the other ends of the two compensation capacitors are correspondingly connected with two differential input ends of the differential amplifier and are respectively correspondingly connected with one ends of the two holding capacitors through the second switch, one ends of the two holding capacitors are also respectively connected with the reference voltage through the third switch, and the other ends of the two holding capacitors are correspondingly connected with two differential output ends of the differential amplifier; during sampling phase, the first switch and the second switch are closed, and the third switch is opened; and when the phase is amplified, the first switch and the second switch are opened, and the third switch is closed. The capacitor-voltage conversion circuit provided by the invention solves the problem of low speed and low precision of the existing capacitor-voltage conversion circuit.
Description
Technical Field
The invention relates to the technical field of CMOS analog integrated circuit design, in particular to a capacitance-voltage conversion circuit and an application system.
Background
In recent years, with the rapid development of micro-mechanical systems (MEMS), capacitive MEMS gyroscopes have been widely used in inertial navigation systems such as satellites, vehicles, and deep sea due to their advantages of low power consumption, low temperature drift, high precision, and compatibility with CMOS processes.
The capacitive MEMS gyroscope is used as a sensing transduction unit and converts angular velocity into differential capacitance variable. In order to perform subsequent data processing, an analog front-end circuit (mainly comprising a capacitance-voltage conversion circuit and a Sigma delta analog-to-digital converter) is required to be added between the processor and the capacitive type MEMS gyroscope, so that the capacitance physical quantity is converted into a digital quantity.
The speed and precision of the capacitance-voltage conversion circuit are critical to the conversion of physical capacitance quantity into digital quantity, so how to design a high-speed and high-precision capacitance-voltage conversion circuit is a problem that needs to be solved urgently by those skilled in the art at the present stage.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a capacitance-voltage conversion circuit and an application system thereof, which are used to solve the problem of low speed and low precision of the prior capacitance-voltage conversion circuit.
To achieve the above and other related objects, the present invention provides a capacitance-voltage conversion circuit, including:
the second-stage conversion module is connected with the output end of the first-stage conversion module; the two circuit structures are the same and both comprise: one ends of the two compensation capacitors are connected with a differential input signal and are respectively connected with a reference voltage through a first switch, the other ends of the two compensation capacitors are correspondingly connected with two differential input ends of the differential amplifier and are respectively connected with one ends of the two holding capacitors through a second switch, one ends of the two holding capacitors are also respectively connected with the reference voltage through a third switch, and the other ends of the two holding capacitors are correspondingly connected with two differential output ends of the differential amplifier;
during sampling phase, the first switch and the second switch are closed, and the third switch is opened; and when the phase is amplified, the first switch and the second switch are opened, and the third switch is closed.
Optionally, the first-stage conversion module and the second-stage conversion module further include:
one ends of the two gain capacitors are respectively connected with a reference voltage through the first switch, and the other ends of the two gain capacitors are respectively correspondingly connected with two differential output ends of the differential amplifier through a fourth switch and are respectively connected with the reference voltage through a fifth switch;
during sampling phase, the fourth switch is opened, and the fifth switch is closed; and when the phase is amplified, the fourth switch is closed, and the fifth switch is opened.
Optionally, the capacitance-voltage conversion circuit further includes:
the two first-stage gain adjusting modules are respectively connected in parallel to two ends of the two gain capacitors in the first-stage conversion module; the two circuit structures are the same and respectively comprise N first-stage gain adjusting units connected in parallel; the first stage gain adjustment unit further comprises: the first-stage adjusting capacitor and the first-stage adjusting switch are connected in series; wherein N is a positive integer greater than or equal to 1.
Optionally, the second-stage conversion module further includes:
one ends of the two auxiliary gain capacitors are correspondingly connected with the two differential output ends of the first-stage conversion module through sixth switches respectively, and are connected with reference voltages through seventh switches respectively, and the other ends of the two auxiliary gain capacitors are correspondingly connected with one ends of the two compensation capacitors;
during sampling phase, the sixth switch is closed, and the seventh switch is opened; and when the phase is amplified, the sixth switch is opened, and the seventh switch is closed.
Optionally, the capacitance-voltage conversion circuit further includes:
the two second-stage gain adjusting modules are respectively connected in parallel to two ends of the two auxiliary gain capacitors; the two circuit structures are the same and both comprise M second-stage gain adjusting units connected in parallel; the second stage gain adjustment unit further comprises: the second-stage regulating capacitor and the second-stage regulating switch are connected in series; wherein M is a positive integer greater than or equal to 1.
Optionally, the capacitance-voltage conversion circuit further includes:
and the input common-mode feedback module is connected with one end of the two compensation capacitors in the first-stage conversion module and is used for eliminating error charges by comparing the common-mode voltage of the two differential input ends of the differential amplifier with the reference voltage.
Optionally, the input common mode feedback module includes:
the feedback circuit comprises two feedback capacitors and a feedback amplifier, wherein the two feedback capacitors are connected in series and then connected in parallel to one ends of the two compensation capacitors, one end of one feedback capacitor is connected with a reference voltage through an eighth switch, one end of the other feedback capacitor is connected with the reference voltage through a ninth switch, a connection node of the two feedback capacitors is connected with the reference voltage through a tenth switch and is connected with the output end of the feedback amplifier, the first input end of the feedback amplifier is connected with one end of one compensation capacitor, the second input end of the feedback amplifier is connected with one end of the other compensation capacitor, and the third input end of the feedback amplifier is connected with the reference voltage;
during sampling phase, the eighth switch, the ninth switch and the tenth switch are closed; and when the phase is amplified, the eighth switch, the ninth switch and the tenth switch are turned off.
Optionally, the feedback amplifier adopts a three-terminal input and single-terminal output folded cascode structure.
Optionally, the first stage conversion module further includes:
one end of each of the two auxiliary compensation capacitors is correspondingly connected with one end of each of the two compensation capacitors, and the other ends of the two auxiliary compensation capacitors are connected with each other, grounded through an eleventh switch and connected with a reference voltage through a twelfth switch;
during the sampling phase, the eleventh switch is opened, and the twelfth switch is closed; and in the amplification phase, the eleventh switch is closed, and the twelfth switch is opened.
Optionally, the capacitance-voltage conversion circuit further includes:
the two first-stage compensation modules are respectively connected in parallel to two ends of the two auxiliary compensation capacitors; the two circuits have the same structure and respectively comprise K first-stage compensation units connected in parallel; the first stage compensation unit further comprises: the first-stage compensation capacitor and the first-stage compensation switch are connected in series; wherein K is a positive integer greater than or equal to 1.
Optionally, the differential amplifier adopts a folded cascode structure with double-ended input and double-ended output.
Optionally, the differential amplifier further comprises: the circuit comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, wherein one end of the first capacitor is connected with a differential output end and is connected with one end of the third capacitor through a first advance switch, the other end of the first capacitor is connected with one end of the second capacitor and a control signal and is connected with one end of the fourth capacitor through a second advance switch, the other end of the second capacitor is connected with the other differential output end and is connected with the other end of the fourth capacitor through a third advance switch, one end of the third capacitor is connected with common-mode voltage through a fourth advance switch, the other end of the third capacitor is connected with one end of the fourth capacitor and is connected with reference voltage through a fifth advance switch, and the other end of the fourth capacitor is connected with the common-mode voltage through a sixth advance switch.
The invention also provides an application system, comprising: a capacitance-to-voltage conversion circuit as claimed in any preceding claim.
As described above, in the capacitor-voltage conversion circuit and the application system of the invention, the first-stage conversion module and the second-stage conversion module both adopt a two-step approach circuit strategy combining the compensation capacitor and the holding capacitor, thereby avoiding the return-to-zero state of the output voltage in the two-phase clock and realizing high-speed and high-precision signal output; the input common-mode feedback module can be combined to greatly reduce 1/A errors and eliminate error charges generated by common-mode values of two differential input ends of the main operational amplifier, so that the thermal noise caused by common-mode voltage drift is effectively inhibited while the common-mode voltage is ensured to be stable; the continuous gain adjustment of the circuit can be realized by combining the first-stage gain adjustment module and/or the second-stage gain adjustment module; the compensation of parasitic capacitance can be realized by combining the first-stage compensation module, and gain error and direct-current offset are eliminated; therefore, the design of the capacitance-voltage conversion circuit with large signal bandwidth, excellent dynamic range, low power consumption and accuracy is realized.
Drawings
Fig. 1 is a circuit block diagram of the capacitance-voltage conversion circuit according to the present invention.
Fig. 2 is a circuit diagram of the first stage conversion module, the first stage gain adjustment module, the input common mode feedback module, the first stage compensation module, and the carrier excitation generation module according to the present invention.
FIG. 3 is a circuit diagram of the second stage conversion module and the second stage gain adjustment module according to the present invention.
Fig. 4 is a circuit diagram of the differential amplifier of the present invention.
FIG. 5 is a timing diagram of two non-overlapping clock signals and two non-overlapping early turn-off clock signals according to the present invention.
Fig. 6 is a circuit diagram of the feedback amplifier according to the present invention.
Fig. 7 is a circuit block diagram of the application system according to the present invention.
Description of the element reference numerals
10 capacitance-voltage conversion circuit
100 first stage conversion module
200 second stage conversion module
300 first stage gain adjustment module
301 first stage gain adjustment unit
400 second stage gain adjustment module
401 second stage gain adjustment unit
500 input common mode feedback module
600 first stage compensation module
601 first stage compensation unit
700 clock generation module
701 internal clock unit
702 carrier clock unit
800 carrier excitation generating unit
20 gyroscope
30A/D converter
40 processor
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 7. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 3, the present embodiment provides a capacitance-voltage conversion circuit 10, including: the system comprises a first-stage conversion module 100 and a second-stage conversion module 200, wherein the second-stage conversion module 200 is connected with the output end of the first-stage conversion module 100; the first-stage conversion module 100 and the second-stage conversion module 200 have the same circuit structure, and both include: one differential amplifier, two compensation capacitors and two holding capacitors.
For the first-stage conversion module 100, one end of each of the two compensation capacitors (Cc1, Cc2) is connected to a differential input signal (inp, inn, i.e. an external differential signal), and is connected to a reference voltage Vref through a first switch (S11, S12), the other end of each of the two compensation capacitors (Cc1, Cc2) is correspondingly connected to two differential input ends of the differential amplifier (OTA _ diff1), and is correspondingly connected to one end of each of the two holding capacitors (CH1, CH2) through a second switch (S21, S22), one end of each of the two holding capacitors (CH1, CH2) is further connected to the reference voltage Vref through a third switch (S31, S32), and the other end of each of the two holding capacitors (CH1, CH2) is correspondingly connected to two differential output ends of the differential amplifier (OTA _ diff 1); in the second-stage conversion module 200, one end of each of the two compensation capacitors (Cc3, Cc4) is connected to a differential input signal (von, vop), i.e., a differential signal output by the first-stage conversion module 100, and is connected to a reference voltage Vref through a first switch (S13, S14), the other end of each of the two compensation capacitors (Cc3, Cc4) is correspondingly connected to two differential input terminals of the differential amplifier (OTA _ diff2), and is correspondingly connected to one end of each of the two holding capacitors (CH3, CH4) through a second switch (S23, S24), one end of each of the two holding capacitors (CH3, CH4) is further connected to the reference voltage Vref through a third switch (S33, S34), and the other end of each of the two holding capacitors (CH3, CH4) is correspondingly connected to two differential output terminals of the differential amplifier (OTA _ diff 2).
The first switch (S11-S14), the second switch (S21-S24) and the third switch (S31-S34) are controlled by two non-overlapping clock signals, wherein the first switch (S11-S14) and the second switch (S21-S24) are controlled by one clock signal (e.g. clk1), and the third switch (S31-S34) are controlled by the other clock signal (e.g. clk 2). During a sampling phase, the first switch (S11-S14) and the second switch (S21-S24) are closed, the third switch (S31-S34) is opened, one end of the compensation capacitor is connected with a reference voltage Vref, the other end of the compensation capacitor is connected with the differential input end of the differential amplifier and one end of the holding capacitor, and the other end of the holding capacitor is connected with the differential output end of the differential amplifier; and when the phase is amplified, the first switch (S11-S14) and the second switch (S21-S24) are opened, the third switch (S31-S34) is closed, one end of the compensation capacitor is connected with a differential input signal, the other end of the compensation capacitor is connected with a differential input end of the differential amplifier, one end of the holding capacitor is connected with a reference voltage, and the other end of the holding capacitor is connected with a differential output end of the differential amplifier. Because one end of the compensation capacitor is connected with the reference voltage during the sampling phase of one period, and one end of the holding capacitor is also connected with the reference voltage during the amplifying phase of the period, the reference voltage held by one end of the holding capacitor is transmitted to the other end of the compensation capacitor during the sampling phase of the next period, so that the voltages at two ends of the compensation capacitor are both the reference voltages, thereby the differential input end of the differential amplifier becomes a real 'virtual point' (the offset generated by the differential input end is eliminated due to the clamping action of the reference voltage Vref), and the other end of the holding capacitor keeps the output voltage value during the amplifying phase of the previous period, thereby avoiding the return-to-zero state of the output voltage in two non-overlapped clock signals (eliminating the return-to-zero operation in the traditional structure), being beneficial to the rapid establishment of the output voltage, and realizing the high-speed, And outputting a high-precision signal.
Specifically, as shown in fig. 4, the differential amplifiers (OTA _ diff1, OTA _ diff2) adopt a folded cascode structure with double-ended input and double-ended output to provide a large output swing; the method comprises the following steps: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10 and an eleventh MOS transistor M11, wherein a gate of the first MOS transistor M1 is connected to a first control signal (Vbtail), a source of the first MOS transistor M1 is grounded, a drain of the first MOS transistor M1 is connected to a source of the second MOS transistor M2 and a source of the third MOS transistor M3, a gate of the second MOS transistor M2 and a gate of the third MOS transistor M3 are used as differential input terminals to receive differential input signals (inn/von, inp/vop), a drain of the second MOS transistor M2 is connected to a source of the eighth MOS transistor M68653, a drain of the third MOS transistor M3 is connected to a drain of the ninth MOS transistor M8658 and a drain of the fourth MOS transistor M8672 (368672 and a drain of the fifth MOS transistor M867), a source of the fourth MOS transistor M4 and a source of the fifth MOS transistor M5 are grounded, a drain of the fourth MOS transistor M4 is connected to a source of the sixth MOS transistor M6, a drain of the fifth MOS transistor M5 is connected to a source of the seventh MOS transistor M7, a gate of the sixth MOS transistor M6 is connected to a gate of the seventh MOS transistor M7 and is connected to a second bias signal (Vb2), a drain of the sixth MOS transistor M6 and a drain of the seventh MOS transistor M7 are used as differential output terminals to generate differential signals (vop/voutp, von/voutn), a drain of the sixth MOS transistor M6 is further connected to a drain of the eighth MOS transistor M8, a drain of the seventh MOS transistor M7 is further connected to a drain of the ninth MOS transistor M9, a gate of the eighth MOS transistor M8 is connected to a gate of the ninth MOS transistor M9 and is connected to a third bias signal (Vb3), a source of the eighth MOS transistor M8 is connected to a drain of the tenth MOS transistor M10, the source of the ninth MOS transistor M9 is connected to the drain of the eleventh MOS transistor M11, the gate of the tenth MOS transistor M10 is connected to the gate of the eleventh MOS transistor M11 and to a second control signal (Vcmfbout), and the source of the tenth MOS transistor M10 is connected to the source of the eleventh MOS transistor M11 and to a power supply voltage.
More specifically, as shown in fig. 4, the differential amplifier (OTA _ diff1, OTA _ diff2) further includes: a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, wherein one end of the first capacitor C1 is connected to a differential output terminal (von/voutn) and is connected to one end of the third capacitor C3 through a first advance switch (Sd1), the other end of the first capacitor C1 is connected to one end of the second capacitor C2 and a second control signal (Vcmfbout) and is connected to one end of the fourth capacitor C4 through a second advance switch (Sd2), the other end of the second capacitor C2 is connected to another differential output terminal (vop/voutp) and is connected to the other end of the fourth capacitor C4 through a third advance switch (Sd3), one end of the third capacitor C3 is connected to a common mode voltage Vcm through a fourth advance switch (Sd4), the other end of the third capacitor C3 is connected to one end of the fourth capacitor C4 and is connected to a reference voltage Vref 5 through a fifth advance switch (Sd5), the other end of the fourth capacitor C4 is connected to the common mode voltage Vcm through a sixth advance switch (Sd 6).
The first advance switch (Sd1), the second advance switch (Sd2), the third advance switch (Sd3), the fourth advance switch (Sd4), the fifth advance switch (Sd5) and the sixth advance switch (Sd6) are controlled by two non-overlapping advance turn-off clock signals (the timing relationship between the two non-overlapping advance turn-off clock signals is shown in fig. 5), wherein the first advance switch (Sd1), the second advance switch (Sd2) and the third advance switch (Sd3) are controlled by an advance turn-off clock signal (such as clk1a), and the fourth advance switch (Sd4), the fifth advance switch (Sd5) and the sixth advance switch (Sd6) are controlled by another advance turn-off clock signal (such as clk2a) to reduce the charge sharing effect on the holding capacitor during amplifying phase and improve the accuracy of the output signal.
Specifically, as shown in fig. 2 and fig. 3, each of the first-stage conversion module 100 and the second-stage conversion module 200 further includes: two gain capacitors. For the first-stage conversion module 100, one end of each of the two gain capacitors (Ci1, Ci2) is connected to a reference voltage Vref through the first switch (S11, S12), and the other end of each of the two gain capacitors (Ci1, Ci2) is correspondingly connected to two differential output ends of the differential amplifier (OTA _ diff1) through a fourth switch (S41, S42), and is connected to the reference voltage Vref through a fifth switch (S51, S52); for the second-stage conversion module 200, one end of each of the two gain capacitors (Ci3, Ci4) is connected to a reference voltage Vref through the first switch (S13, S14), and the other end of each of the two gain capacitors (Ci3, Ci4) is correspondingly connected to two differential output terminals of the differential amplifier (OTA _ diff2) through the fourth switch (S43 ), and is connected to the reference voltage Vref through the fifth switch (S53, S54).
The fourth switch (S41-S44) and the fifth switch (S51-S54) are controlled by two non-overlapping clock signals, wherein the fifth switch (S51-S54) is controlled by one clock signal (e.g. clk1), and the fourth switch (S41-S44) is controlled by the other clock signal (e.g. clk 2). During a sampling phase, the fourth switch (S41-S43) is opened, the first switch (S11-S14) and the fifth switch (S51-S54) are closed, and both ends of the gain capacitor are connected with a reference voltage Vref; and in the amplification phase, the fourth switch (S41-S43) is closed, the first switch (S11-S14) and the fifth switch (S51-S54) are opened, one end of the gain capacitor is connected with one end of the compensation capacitor, and the other end of the gain capacitor is connected with the differential output end of the differential amplifier. Since both ends of the gain capacitor are connected to the reference voltage Vref at the time of sampling the phase, the residual charge of the amplification phase of the previous period can be eliminated.
Specifically, as shown in fig. 1 and fig. 2, the capacitance-voltage conversion circuit 10 further includes: two first-stage gain adjusting modules 300, which are respectively connected in parallel to two ends of the two gain capacitors (Ci1, Ci2) in the first-stage conversion module 100, are used for realizing continuous gain adjustment. More specifically, the two first-stage gain adjustment modules 300 have the same circuit structure, and each first-stage gain adjustment module includes N first-stage gain adjustment units 301 connected in parallel; the first stage gain adjustment unit 301 further includes: the first-stage adjusting capacitors (Ci11-Ci1n, Ci21-Ci2n) and the first-stage adjusting switches (Si11-Si1n, Si21-Si2n) are connected in series; wherein N is a positive integer greater than or equal to 1. Optionally, in this example, N is equal to 4. In the embodiment, different numbers of first-stage adjusting capacitors are selectively incorporated by controlling the number of the first-stage adjusting switches, so that 1-20 times of continuous gain adjustment is realized. It should be noted that the first-stage adjusting switches in each first-stage gain adjusting unit 301 are controlled by different switch control signals (e.g., swg1_1-swg4-1) to control the number of closed first-stage adjusting switches.
Specifically, as shown in fig. 3, the second-stage conversion module 200 further includes: and two auxiliary gain capacitors (Cy1, Cy2), wherein one ends of the two auxiliary gain capacitors (Cy1, Cy2) are respectively and correspondingly connected with the two differential output ends of the first-stage conversion module 100 through sixth switches (S61, S62), and are respectively and correspondingly connected with the reference voltage Vref through seventh switches (S71, S72), and the other ends of the two auxiliary gain capacitors (Cy1, Cy2) are respectively and correspondingly connected with one ends of the two compensation capacitors (Cc3, Cc 4).
The sixth switch (S61-S62) and the seventh switch (S71, S72) are controlled by two non-overlapping clock signals, wherein the sixth switch (S61-S62) is controlled by one clock signal (e.g. clk1), and the seventh switch (S71, S72) is controlled by the other clock signal (e.g. clk 2). During a sampling phase, the sixth switch (S61-S62) is closed, the seventh switch (S71, S72) is opened, one end of the auxiliary gain capacitor is connected with the differential output end of the first stage conversion module 100, and the other end of the auxiliary gain capacitor is connected with one end of the compensation capacitor; and during the amplification phase, the sixth switch (S61-S62) is opened, the seventh switch (S71, S72) is closed, one end of the auxiliary gain capacitor is connected with the reference voltage, and the other end of the auxiliary gain capacitor is connected with one end of the compensation capacitor.
Specifically, the capacitance-voltage conversion circuit 10 further includes: and two second-stage gain adjusting modules 400 respectively connected in parallel to two ends of the two auxiliary gain capacitors (Cy1, Cy2) for realizing continuous gain adjustment. More specifically, the two second-stage gain adjustment modules 400 have the same circuit structure, and each of the two second-stage gain adjustment modules includes: m parallel second stage gain adjustment units 401, said second stage gain adjustment units 401 further comprising: the second-stage regulating capacitors (Cy11-Cy1m, Cy21-Cy2m) and the second-stage regulating switches (Sy11-Sy1m, Sy21-Sy2m) are connected in series; wherein M is a positive integer greater than or equal to 1. Optionally, M is equal to 8 in this example. In this embodiment, the number of the second-stage adjusting switches is controlled to selectively incorporate different numbers of second-stage adjusting capacitors, so that 1-40 times of continuous gain adjustment is realized. It should be noted that the second-stage adjusting switches in each second-stage gain adjusting unit 401 are controlled by different switch control signals (e.g., swg1_2-swg8-2) to control the number of closed second-stage adjusting switches.
Specifically, as shown in fig. 1 and fig. 2, the capacitance-voltage conversion circuit 10 further includes: and an input common mode feedback module 500, connected to one end of the two compensation capacitors (Cc1, Cc2) in the first stage conversion module 100, for eliminating error charges by comparing the common mode voltage of the two differential input terminals of the differential amplifier OTA _ diff1 with the reference voltage Vref, so as to ensure the stability of the common mode voltage and effectively suppress thermal noise caused by common mode voltage drift.
More specifically, as shown in fig. 2, the input common mode feedback module 500 includes: two feedback capacitors (Cfb1, Cfb2) and a feedback amplifier (OTA _ icmfb), wherein the two feedback capacitors (Cfb1, Cfb2) are connected in series and then connected in parallel with one end of the two compensation capacitors (Cc1, Cc2), one end of one feedback capacitor (Cfb1) is connected with a reference voltage Vref through an eighth switch (S8), one end of the other feedback capacitor (Cfb2) is connected with the reference voltage Vref through a ninth switch (S9), a connection node of the two feedback capacitors (Cfb1, Cfb2) is connected with the reference voltage Vref through a tenth switch (S10), and is connected to an output terminal of said feedback amplifier (OTA _ icmfb), a first input terminal of said feedback amplifier (OTA _ icmfb) being connected to one terminal of said compensation capacitor (Cc1), a second input terminal of the feedback amplifier (OTA _ icmfb) is connected to one terminal of another of the compensation capacitors (Cc2), the third input of the feedback amplifier (OTA _ icmfb) is connected to a reference voltage Vref.
The eighth switch (S8), the ninth switch (S9), and the tenth switch (S10) are all controlled by a clock signal (e.g., clk1) of two non-overlapping clocks. In a sampling phase, the eighth switch (S8), the ninth switch (S9) and the tenth switch (S10) are closed, and reference voltages are connected to two ends of two feedback capacitors; in the amplification phase, the eighth switch (S8), the ninth switch (S9), and the tenth switch (S10) are turned off, and a differential input signal is connected to both ends of two feedback capacitors connected in series.
As shown in fig. 6, the feedback amplifier (OTA _ icmfb) adopts a three-terminal input and single-terminal output folded cascode structure, and includes: a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, a twelfth MOS transistor M22 and a thirteenth MOS transistor M23, a gate of the twelfth MOS transistor M12 is connected to a second N-type bias signal (Vbn2), a source of the twelfth MOS transistor M12 is grounded, a drain of the twelfth MOS transistor M12 is connected to a source of the thirteenth MOS transistor M9, a source of the fourteenth MOS transistor M14 and a source of the fifteenth MOS transistor M15, a gate of the thirteenth MOS transistor M13 and a gate of the fourteenth MOS transistor M14 serve as a first input terminal and a second input terminal for receiving a differential input signal (inn, inp and a drain of the thirteenth MOS transistor M14 serve as a first input terminal and a drain of the fourteenth MOS transistor M20 and a drain of the fourteenth MOS transistor M8658, a drain of the fifteenth MOS transistor M15 is connected to a source of the twenty-first MOS transistor M21, a gate of the sixteenth MOS transistor M16 and a gate of the seventeenth MOS transistor M17 are connected to each other and to a drain of the nineteenth MOS transistor M19, a source of the sixteenth MOS transistor M16 and a source of the seventeenth MOS transistor M17 are grounded, a drain of the sixteenth MOS transistor M16 is connected to a source of the eighteenth MOS transistor M18, a drain of the seventeenth MOS transistor M17 is connected to a source of the nineteenth MOS transistor M19, a gate of the eighteenth MOS transistor M18 is connected to a gate of the nineteenth MOS transistor M19 and to a first N-type bias signal (Vbn1), a drain of the eighteenth MOS transistor M18 is connected to a drain of the twentieth MOS transistor M20 and serves as an output end of the feedback amplifier, a drain of the nineteenth MOS transistor M19 is connected to a drain of the twenty-first MOS transistor M21, and a drain of the twentieth MOS transistor M20 is connected to a gate of the twenty-second bias transistor M2 (Vbp 21), the source of the twentieth MOS transistor M20 is connected to the drain of the twentieth MOS transistor M22, the source of the twenty-first MOS transistor M21 is connected to the drain of the twenty-third MOS transistor M23, the gate of the twenty-second MOS transistor M22 is connected to the gate of the twenty-third MOS transistor M23 and to a first P-type bias signal (Vbp1), and the source of the twenty-second MOS transistor M22 and the source of the twenty-third MOS transistor M23 are connected to a power supply voltage.
Specifically, as shown in fig. 2, the first-stage conversion module 100 further includes: and two auxiliary compensation capacitors (Cn1, Cn2), wherein one end of each of the two auxiliary compensation capacitors (Cn1, Cn2) is correspondingly connected with one end of each of the two compensation capacitors (Cc1, Cc2), and the other ends of the two auxiliary compensation capacitors (Cn1, Cn2) are connected with each other, grounded through an eleventh switch, and connected with a reference voltage through a twelfth switch.
The eleventh switch (S11) and the twelfth switch (S12) are controlled by two non-overlapping clock signals, wherein the twelfth switch (S12) is controlled by one clock signal (e.g., clk1), and the eleventh switch (S11) is controlled by the other clock signal (e.g., clk 2). During the sampling phase, the eleventh switch (S11) is opened, the twelfth switch (S12) is closed, and a reference voltage Vref is connected at the connection node of the two auxiliary compensation capacitors (Cn1 and Cn 2); in the amplification phase, the eleventh switch (S11) is closed, the twelfth switch (S12) is opened, and the connection node of the two auxiliary compensation capacitors (Cn1, Cn2) is grounded.
Specifically, as shown in fig. 1 and fig. 2, the capacitance-voltage conversion circuit 10 further includes: and the two first-stage compensation modules 600 are respectively connected in parallel to two ends of the two auxiliary compensation capacitors (Cn1, Cn2) and are used for matching parasitic capacitors. More specifically, the two first-stage compensation modules 600 have the same circuit structure, and each of the two first-stage compensation modules includes: k parallel first stage compensation units 601, said first stage compensation units 601 further comprising: the first-stage compensation capacitors (Cn11-Cn15, Cn21-Cn25) and the first-stage compensation switches (Sn11-Sn15, Sn21-Sn25) are connected in series; wherein K is a positive integer greater than or equal to 1. Optionally, in this example, K is equal to 5. In this embodiment, the first-stage compensation capacitors with different numbers are selectively incorporated by controlling the number of the first-stage compensation switches, so that the matching of the step length 300fF and the total compensation capacitor 9.6pF is realized for the generated parasitic capacitors, the influence on the input common-mode voltage drift is reduced, and the gain error and the dc offset are eliminated. It should be noted that the first stage compensation switches in each first stage compensation unit are controlled by different switch control signals (such as swc1-swc5) to realize the control of the number of closures of the first stage compensation switches.
Specifically, as shown in fig. 1, the capacitance-voltage conversion circuit 10 further includes: a clock generating module 700 for providing the first stage conversion module 100 and the second stage conversion module 200 with two non-overlapping clock signals (clk1, clk2) and two non-overlapping early turn-off clock signals (clk1a, clk2 a). It should be noted that the clock generating module 700 is any conventional circuit structure capable of implementing the above-mentioned functions, and the specific circuit composition thereof is not limited in this embodiment.
Specifically, as shown in fig. 1 and fig. 2, the capacitance-voltage conversion circuit 10 further includes: and a carrier excitation generating module 800, configured to generate a carrier excitation signal and apply the carrier excitation signal to the gyroscope, so that the gyroscope generates a capacitance change. More specifically, the carrier excitation generating module 800 includes: a tenth switch (S13) and a fourteenth switch (S14), wherein one end of the tenth switch (S13) is grounded, one end of the fourteenth switch (S14) is connected to a reference voltage Vref, and the other end of the tenth switch (S13) and the other end of the fourteenth switch (S14) are connected to each other and generate a carrier _ input. The tenth switch (S13) and the fourteenth switch (S14) are controlled by two non-overlapping clock signals, wherein the tenth switch (S13) is controlled by one clock signal (e.g., clk1), and the fourteenth switch (S14) is controlled by the other clock signal (e.g., clk 2).
When the capacitance-voltage conversion circuit 10 further includes the carrier excitation generating module 800, the clock generating module 700 includes: an internal clock unit 701 and a carrier clock unit 702, the internal clock unit 701 is configured to provide two non-overlapping clock signals (clk1, clk2) and two non-overlapping early-off clock signals (clk1a, clk2a) for the first stage conversion module 100 and the second stage conversion module 200, and the carrier clock unit 702 is configured to provide two non-overlapping clock signals (clk1, clk2) for the carrier excitation generation module 800. In the embodiment, the internal clock unit 701 and the carrier clock unit 702 generate identical two-phase non-overlapping clock signals (clk1, clk2), so that noise crosstalk can be avoided.
Accordingly, as shown in fig. 7, the present embodiment further provides an application system, where the application system includes: the capacitance-voltage conversion circuit 10 as described above.
Specifically, the application system further includes: the gyroscope comprises a gyroscope 20, an analog-to-digital converter 30 and a processor 40, wherein the gyroscope 20 is used for converting an angular velocity related to a to-be-measured value into a capacitance variation, the capacitance-voltage conversion circuit 10 is used for converting the capacitance variation into an analog voltage variation, the analog-to-digital converter 30 is used for converting the analog voltage variation into a digital variation, and the processor 40 is used for performing subsequent data processing on the digital variation.
In summary, in the capacitor-voltage conversion circuit and the application system of the invention, the first-stage conversion module and the second-stage conversion module both adopt a two-step approach circuit strategy combining the compensation capacitor and the holding capacitor, thereby avoiding the return-to-zero state of the output voltage in the two-phase clock and realizing high-speed and high-precision signal output; the input common-mode feedback module can be combined to greatly reduce 1/A errors and eliminate error charges generated by common-mode values of two differential input ends of the main operational amplifier, so that the thermal noise caused by common-mode voltage drift is effectively inhibited while the common-mode voltage is ensured to be stable; the continuous gain adjustment of the circuit can be realized by combining the first-stage gain adjustment module and/or the second-stage gain adjustment module; the compensation of parasitic capacitance can be realized by combining the first-stage compensation module, and gain error and direct-current offset are eliminated; therefore, the design of the capacitance-voltage conversion circuit with large signal bandwidth, excellent dynamic range, low power consumption and accuracy is realized. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. A capacitance-to-voltage conversion circuit, comprising:
the second-stage conversion module is connected with the output end of the first-stage conversion module; the two circuit structures are the same and both comprise: one ends of the two compensation capacitors are connected with a differential input signal and are respectively connected with a reference voltage through a first switch, the other ends of the two compensation capacitors are correspondingly connected with two differential input ends of the differential amplifier and are respectively connected with one ends of the two holding capacitors through a second switch, one ends of the two holding capacitors are also respectively connected with the reference voltage through a third switch, and the other ends of the two holding capacitors are correspondingly connected with two differential output ends of the differential amplifier;
during sampling phase, the first switch and the second switch are closed, and the third switch is opened; and when the phase is amplified, the first switch and the second switch are opened, and the third switch is closed.
2. The capacitance-to-voltage conversion circuit of claim 1, wherein the first stage conversion module and the second stage conversion module each further comprise:
one ends of the two gain capacitors are respectively connected with a reference voltage through the first switch, and the other ends of the two gain capacitors are respectively correspondingly connected with two differential output ends of the differential amplifier through a fourth switch and are respectively connected with the reference voltage through a fifth switch;
during sampling phase, the fourth switch is opened, and the fifth switch is closed; and when the phase is amplified, the fourth switch is closed, and the fifth switch is opened.
3. The capacitance-to-voltage conversion circuit of claim 2, further comprising:
the two first-stage gain adjusting modules are respectively connected in parallel to two ends of the two gain capacitors in the first-stage conversion module; the two circuit structures are the same and respectively comprise N first-stage gain adjusting units connected in parallel; the first stage gain adjustment unit further comprises: the first-stage adjusting capacitor and the first-stage adjusting switch are connected in series; wherein N is a positive integer greater than or equal to 1.
4. The capacitance-to-voltage conversion circuit of claim 2 or 3, wherein the second stage conversion module further comprises:
one ends of the two auxiliary gain capacitors are correspondingly connected with the two differential output ends of the first-stage conversion module through sixth switches respectively, and are connected with reference voltages through seventh switches respectively, and the other ends of the two auxiliary gain capacitors are correspondingly connected with one ends of the two compensation capacitors;
during sampling phase, the sixth switch is closed, and the seventh switch is opened; and when the phase is amplified, the sixth switch is opened, and the seventh switch is closed.
5. The capacitance-to-voltage conversion circuit of claim 4, further comprising:
the two second-stage gain adjusting modules are respectively connected in parallel to two ends of the two auxiliary gain capacitors; the two circuit structures are the same and both comprise M second-stage gain adjusting units connected in parallel; the second stage gain adjustment unit further comprises: the second-stage regulating capacitor and the second-stage regulating switch are connected in series; wherein M is a positive integer greater than or equal to 1.
6. The capacitance-to-voltage conversion circuit of claim 1, further comprising:
and the input common-mode feedback module is connected with one end of the two compensation capacitors in the first-stage conversion module and is used for eliminating error charges by comparing the common-mode voltage of the two differential input ends of the differential amplifier with the reference voltage.
7. The capacitance-to-voltage conversion circuit of claim 6, wherein the input common mode feedback module comprises:
the feedback circuit comprises two feedback capacitors and a feedback amplifier, wherein the two feedback capacitors are connected in series and then connected in parallel to one ends of the two compensation capacitors, one end of one feedback capacitor is connected with a reference voltage through an eighth switch, one end of the other feedback capacitor is connected with the reference voltage through a ninth switch, a connection node of the two feedback capacitors is connected with the reference voltage through a tenth switch and is connected with the output end of the feedback amplifier, the first input end of the feedback amplifier is connected with one end of one compensation capacitor, the second input end of the feedback amplifier is connected with one end of the other compensation capacitor, and the third input end of the feedback amplifier is connected with the reference voltage;
during sampling phase, the eighth switch, the ninth switch and the tenth switch are closed; and when the phase is amplified, the eighth switch, the ninth switch and the tenth switch are turned off.
8. The capacitance-to-voltage conversion circuit of claim 7, wherein the feedback amplifier employs a three-terminal input, single-terminal output folded cascode configuration.
9. The capacitance-to-voltage conversion circuit of claim 1, wherein the first stage conversion module further comprises:
one end of each of the two auxiliary compensation capacitors is correspondingly connected with one end of each of the two compensation capacitors, and the other ends of the two auxiliary compensation capacitors are connected with each other, grounded through an eleventh switch and connected with a reference voltage through a twelfth switch;
during the sampling phase, the eleventh switch is opened, and the twelfth switch is closed; and in the amplification phase, the eleventh switch is closed, and the twelfth switch is opened.
10. The capacitance-to-voltage conversion circuit of claim 9, further comprising:
the two first-stage compensation modules are respectively connected in parallel to two ends of the two auxiliary compensation capacitors; the two circuits have the same structure and respectively comprise K first-stage compensation units connected in parallel; the first stage compensation unit further comprises: the first-stage compensation capacitor and the first-stage compensation switch are connected in series; wherein K is a positive integer greater than or equal to 1.
11. The capacitance-to-voltage conversion circuit of claim 1, wherein the differential amplifier employs a double-ended input, double-ended output folded cascode configuration.
12. The capacitance-to-voltage conversion circuit of claim 11, wherein the differential amplifier further comprises: the circuit comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, wherein one end of the first capacitor is connected with a differential output end and is connected with one end of the third capacitor through a first advance switch, the other end of the first capacitor is connected with one end of the second capacitor and a control signal and is connected with one end of the fourth capacitor through a second advance switch, the other end of the second capacitor is connected with the other differential output end and is connected with the other end of the fourth capacitor through a third advance switch, one end of the third capacitor is connected with common-mode voltage through a fourth advance switch, the other end of the third capacitor is connected with one end of the fourth capacitor and is connected with reference voltage through a fifth advance switch, and the other end of the fourth capacitor is connected with the common-mode voltage through a sixth advance switch.
13. An application system, comprising: a capacitance-to-voltage conversion circuit as claimed in any one of claims 1 to 12.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114018298A (en) * | 2021-10-22 | 2022-02-08 | 西安电子科技大学 | Capacitance-voltage conversion circuit for MEMS capacitive sensor |
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Denomination of invention: Capacitor voltage conversion circuit and application system Granted publication date: 20220610 Pledgee: Agricultural Bank of China Limited Shanghai pilot Free Trade Zone New Area Branch Pledgor: Shanghai Xinwen Technology Co.,Ltd. Registration number: Y2024310000050 |