CN215897691U - Switched capacitor amplifier with adjustable Miller compensation - Google Patents
Switched capacitor amplifier with adjustable Miller compensation Download PDFInfo
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- CN215897691U CN215897691U CN202121855032.1U CN202121855032U CN215897691U CN 215897691 U CN215897691 U CN 215897691U CN 202121855032 U CN202121855032 U CN 202121855032U CN 215897691 U CN215897691 U CN 215897691U
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Abstract
The utility model discloses a switched capacitor amplifier with adjustable Miller compensation, which relates to the field of electronic circuits. The amplifier peripheral circuit is controlled by the first control signal to enable the switch capacitor amplifier to work in an amplification phase, the adjustable Miller capacitor in the operational amplifier is controlled by the first control signal to have a first capacitance value with a smaller capacitance value, the loop bandwidth is larger, and the step response speed is higher. The amplifier peripheral circuit is controlled by the second control signal to enable the switch capacitor amplifier to work in the reset phase, the adjustable Miller capacitor in the operational amplifier is controlled by the second control signal to have a larger second capacitance value, the loop bandwidth is narrow, and the loop can be ensured to have sufficient phase margin.
Description
Technical Field
The utility model relates to the field of electronic circuits, in particular to a switched capacitor amplifier with adjustable Miller compensation.
Background
A switched capacitor amplifier is a commonly used gain circuit with an output that is several times the input. Capacitors in integrated circuits usually have very good matching, and switched capacitor amplifiers can achieve very accurate gain, and are a common choice in the field of analog signal amplification, buffering and driving. The switched capacitor amplifier has several advantages as follows: firstly, the switched capacitor amplifier cannot cause direct current load to a signal source or a preceding stage circuit; secondly, the amplification ratio is determined by the capacitance ratio, and the precision is higher; and thirdly, the device often has a zero setting function, so that offset and noise can be reduced.
To overcome the input offset voltage and 1/f noise of the operational amplifier, a resettable switched capacitor amplifier is often used. Such switched capacitor amplifiers have two phases, which are typically reset (or zeroed) and amplified. When the operational amplifier is placed in the switched capacitor amplifier, it is in negative feedback, which needs to be ensured to be stable, and if the feedback coefficient f becomes larger and larger (i.e. the closed loop gain a0 becomes smaller and smaller), the phase margin of the switched capacitor amplifier approaches 0 degree, which will cause oscillation, and thus the operational amplifier needs to be compensated. However, the feedback coefficient of the switched capacitor amplifier is one in the reset phase and depends on the gain in the amplification phase. The gain at the amplification phase is often more than one time, even as much as several tens to a hundred times, so that the requirements for loop compensation are very different. If the op-amp is compensated for in accordance with the settling conditions of the reset phase, the loop bandwidth and settling time at the amplification phase will be greatly affected.
SUMMERY OF THE UTILITY MODEL
The inventor provides a switched capacitor amplifier with adjustable miller compensation aiming at the problems and the technical requirements, and the technical scheme of the utility model is as follows:
the utility model provides an adjustable miller compensated switched capacitor amplifier, this switched capacitor amplifier includes operational amplifier and connects the amplifier peripheral circuit outside operational amplifier, and operational amplifier includes adjustable miller electric capacity inside, and amplifier peripheral circuit and adjustable miller electric capacity are all controlled by switched capacitor amplifier's control signal, and switched capacitor amplifier's control signal includes non-overlapping first control signal and second control signal:
the amplifier peripheral circuit is controlled by a first control signal to enable the switch capacitor amplifier to work in an amplification phase, and the adjustable Miller capacitor in the operational amplifier is controlled by the first control signal to have a first capacitance value;
or the amplifier peripheral circuit is controlled by a second control signal to enable the switch capacitor amplifier to work in a reset phase, and the adjustable Miller capacitor in the operational amplifier is controlled by the second control signal to have a second capacitance value;
wherein the first capacitance value is smaller than the second capacitance value.
The further technical scheme is that the adjustable Miller capacitor in the operational amplifier comprises a plurality of capacitor branches connected in parallel, each capacitor branch is provided with a Miller capacitor, at least one capacitor branch is also connected in series with an adjusting switch controlled by a control signal of the switched capacitor amplifier, and the adjusting switch is controlled by a first control signal to be switched off and a second control signal to be switched on.
The further technical scheme is that each capacitor branch is also connected with a return-to-zero resistor in series.
The further technical scheme is that a unity gain buffer is also connected in series on each capacitance branch.
The further technical scheme is that the operational amplifier internally comprises a first-stage operational amplifier and a second-stage operational amplifier which are cascaded, an adjustable Miller capacitor is connected between the output ends of the first-stage operational amplifier and the operational amplifier, and the open-loop gain of the operational amplifier reaches a preset threshold value.
The further technical scheme is that the first-stage operational amplifier is a differential input-stage amplifier, and the second-stage operational amplifier is an output-stage amplifier.
The further technical scheme is that the first-stage operational amplifier is a folding cascode amplifier, and the second-stage operational amplifier is a rail-to-rail output buffer-stage amplifier.
The beneficial technical effects of the utility model are as follows:
the application discloses a switched capacitor amplifier with adjustable Miller compensation, wherein an operational amplifier in the switched capacitor amplifier is internally provided with an adjustable Miller capacitor, the capacitance value of the adjustable Miller capacitor has a larger capacitance value under the reset phase of the switched capacitor amplifier, the bandwidth of a loop is narrower, and the loop can be ensured to have sufficient phase margin; and the capacitance value is smaller under the amplification phase of the switched capacitor amplifier, the loop bandwidth is larger, and the step response speed is higher.
Drawings
Fig. 1 is a block diagram of an amplifier peripheral circuit of the switched capacitor amplifier of the present application.
Fig. 2 is a block diagram of another amplifier peripheral circuit of the switched capacitor amplifier of the present application.
Fig. 3 is a schematic diagram of an internal structure of an operational amplifier and switching signals corresponding to the peripheral circuits of the amplifier shown in fig. 1.
Fig. 4 is a schematic diagram of another internal structure of an operational amplifier and switching signals corresponding to the amplifier peripheral circuit shown in fig. 2.
Fig. 5 is a waveform control diagram of each switching signal in the amplifier peripheral circuit shown in fig. 2.
Fig. 6 is another structure diagram of the operational amplifier based on fig. 3.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application discloses a switched capacitor amplifier with adjustable Miller compensation, which comprises an operational amplifier 1 and an amplifier peripheral circuit connected to the outside of the operational amplifier, wherein two different amplifier peripheral circuits in the switched capacitor amplifier under different embodiments are shown in figures 1 and 2, and the amplifier peripheral circuits connected to the outside of the operational amplifier 1 in figures 1 and 2 are all the amplifier peripheral circuits.
The operational amplifier 1 internally comprises an adjustable miller capacitor, an amplifier peripheral circuit and the adjustable miller capacitor are controlled by control signals of the switched capacitor amplifier, and the control signals of the switched capacitor amplifier comprise a first control signal and a second control signal which are not overlapped. The amplifier peripheral circuit is controlled by a first control signal to enable the switch capacitor amplifier to work in an amplification phase, and the adjustable Miller capacitor in the operational amplifier is controlled by the first control signal to have a first capacitance value. Or, the amplifier peripheral circuit is controlled by the second control signal to make the switched capacitor amplifier work in the reset phase, and the adjustable miller capacitor in the operational amplifier is controlled by the second control signal to have the second capacitance value. Wherein the first capacitance value is smaller than the second capacitance value.
That is, in the switched capacitor amplifier disclosed in the present application, the capacitance value of the adjustable miller capacitor in the operational amplifier is adjustable, and when the switched capacitor amplifier is in the reset phase, the adjustable miller capacitor in the operational amplifier has a larger capacitance value, that is, the operational amplifier has a larger compensation capacitor, the loop bandwidth is narrower, and the loop can be ensured to have a sufficient phase margin. When the switched capacitor amplifier is in the amplifying phase, the adjustable miller capacitor in the operational amplifier has a smaller capacitance value, that is, the operational amplifier has a smaller compensation capacitor, a larger loop bandwidth and a faster step response speed.
In order to reduce the direct current gain error, the operational amplifier is generally required to have higher open loop gain which can be as high as 70dB to 120dB, the operational amplifier in the application adopts a two-stage CMOS amplifier, the operational amplifier internally comprises a first-stage operational amplifier and a second-stage operational amplifier which are cascaded, an adjustable Miller capacitor is connected between the output ends of the first-stage operational amplifier and the operational amplifier, the open loop gain of the operational amplifier reaches a preset threshold value, and the preset threshold value can be configured in a self-defining way. As shown in fig. 3, an implementation structure of the operational amplifier is shown, the first stage operational amplifier is a differential input stage amplifier, and the second stage operational amplifier is an output stage amplifier, and the open loop gain of the operational amplifier of the common structure can reach 60dB to 80 dB. In another implementation structure of the operational amplifier shown in fig. 4, the first-stage operational amplifier is a folded cascode amplifier, and the second-stage operational amplifier is a rail-to-rail output buffer stage amplifier, and the open-loop gain of the operational amplifier in the common structure can reach 80dB to 100 dB. In practice, other structures may be adopted, or an auxiliary operational amplifier for increasing the gain may be added to the first-stage operational amplifier to further increase the open-loop gain of the operational amplifier. The circuit of the two-stage operational amplifier is conventional, and the circuit configuration thereof will not be described in detail in this application.
Specifically, as shown in fig. 3 and 4, the adjustable miller capacitance in the operational amplifier 1 includes a plurality of parallel capacitor branches, each capacitor branch is provided with a miller capacitance Cc, at least one capacitor branch is also connected in series with an adjusting switch K controlled by a control signal of the switched capacitor amplifier, the adjusting switch is controlled by a first control signal to be turned off and controlled by a second control signal to be turned on, and the adjusting switch K may be actually implemented by a switch tube as shown in fig. 3, or may be implemented by an electronic switch as shown in fig. 4. In practical application, the adjustable miller capacitor generally comprises two parallel capacitor branches, and the adjustable miller capacitor in the application can be obtained by connecting one miller capacitor with an adjusting switch K in parallel at two ends of the miller capacitor in the existing operational amplifier.
In fig. 3, for example, the amplifier peripheral circuit structure shown in fig. 1 is adopted outside the operational amplifier, a non-inverting input terminal Vin + of the operational amplifier is grounded, an inverting input terminal Vin-is connected with the input signal Vin through a capacitor C1 and a switch k1, and a common terminal of the capacitor C1 and the switch k1 is grounded through a switch k 2. The inverting input Vin-of the operational amplifier 1 is also connected to the output Vout of the operational amplifier via a switch k 3. The inverting input terminal of the operational amplifier is also grounded through a capacitor C2 and a switch k4, and the common terminal of the capacitor C2 and the switch k4 is connected to the output terminal Vout of the operational amplifier through a switch k 5. The switch k1 and the switch k5 are controlled by the φ 1 signal, the switches k2, k3 and k4 are controlled by the φ 2 signal, and the φ 1 signal and the φ 2 signal are bidirectional non-overlapping clock signals. Then the tuning switch K in the tunable miller capacitance in the operational amplifier is controlled by the phi 2 signal, as shown in fig. 3.
The first control signal of the switch capacitor amplifier comprises a high level phi 1 and a low level phi 2, and the switch capacitor amplifier works in an amplification phase; the adjusting switch K is turned off, and the capacitance value of the adjustable Miller capacitor is a first lower capacitance value. The second control signal of the switched capacitor amplifier comprises that phi 2 is high level, phi 1 is low level, the output end of the operational amplifier is connected with the inverting input end of the operational amplifier, the left side of the capacitor C1 is grounded, so that the input equivalent offset voltage of the operational amplifier is stored in the capacitor C1, the switched capacitor amplifier works in the reset phase, the adjusting switch K is closed, and the capacitance value of the adjustable miller capacitor is a second higher capacitance value.
In fig. 4, taking the amplifier peripheral circuit structure shown in fig. 2 as an example of an external operational amplifier, the non-inverting input terminal Vin + and the inverting input terminal Vin-of the operational amplifier are respectively connected to two differential inputs CM _ H and CM _ L through two capacitors 50C, and a switch S3 is connected between the differential inputs CM _ H and CM _ L. The non-inverting input terminal Vin + of the operational amplifier is also connected to vcm through a switch S1. The non-inverting input terminal Vin + of the operational amplifier is further connected with a capacitor C3, and the other end of the capacitor C3 is grounded through a switch S4 and is connected with vcm through a switch S4_ n. A capacitor C4 and a switch S2 are connected in parallel between the inverting input terminal Vin-and the output terminal Vout of the operational amplifier. The control signals of the switches S1 and S2 are the same, the control signal of the switch S3 is a delay signal obtained by delaying the time of S1 and S2 by a first predetermined time period, the control signal of the switch S4_ n is a delay signal obtained by delaying the time of S3 by a second predetermined time period, and the switch S4 and the switch S4_ n are a pair of opposite signals. Then the adjustment switch K in the adjustable miller capacitance in the op amp is the same as the control signals for switches S1 and S2, as shown in fig. 4.
The control waveforms of the switches in fig. 2 are as shown in fig. 5, the first control signal of the switched capacitor amplifier includes that S1 and S2 are turned off at low level, and the switched capacitor amplifier operates in the amplifying phase; the adjusting switch K is switched off under the action of low level, and the capacitance value of the adjustable Miller capacitor is a first lower capacitance value. The second control signal of the switched capacitor amplifier comprises that S1 and S2 are closed at high level, the output end of the operational amplifier is connected with the inverting input end of the operational amplifier, the switched capacitor amplifier works at a reset phase, the adjusting switch K is closed under the action of the high level, and the capacitance value of the adjustable miller capacitor is a second higher capacitance value. As can be seen from the embodiments formed in fig. 1 and 3 and the embodiments formed in fig. 2 and 4, the control signal of the switched capacitor amplifier actually includes the switching signals of a plurality of switches, and therefore, the non-overlap between the first control signal and the second control signal means the non-overlap of the switching signals, that is, the level of the same switching signal in the first control signal is different from the level of the same switching signal in the second control signal. For example, in the embodiment formed by fig. 1 and 3, the phi 1 signal is high in the first control signal and low in the second control signal, and the phi 2 signal is low in the first control signal and high in the second control signal.
Furthermore, a return-to-zero resistor R0 is connected in series to each of the capacitance branches of the adjustable miller capacitance in the operational amplifier 1, as shown in fig. 4, the return-to-zero resistor R0 is used to control the position of the right half-plane (RHP) zero point, so as to further optimize the circuit performance.
Furthermore, each capacitance branch of the adjustable miller capacitance in the operational amplifier 1 is also connected in series with a unity gain buffer, as shown in fig. 6, a unit gain buffer a1 and a2 are respectively connected in series on the two capacitance branches, and the unity gain buffer is used for blocking the feedforward path of the miller capacitance, eliminating the zero point of the right half-plane (RHP), and further optimizing the circuit performance. The unity gain buffer may be implemented with a source follower.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.
Claims (7)
1. An adjustable miller compensation switched capacitor amplifier, wherein the switched capacitor amplifier comprises an operational amplifier and an amplifier peripheral circuit connected outside the operational amplifier, the operational amplifier internally comprises an adjustable miller capacitor, the amplifier peripheral circuit and the adjustable miller capacitor are both controlled by a control signal of the switched capacitor amplifier, and the control signal of the switched capacitor amplifier comprises a first control signal and a second control signal which are not overlapped:
the amplifier peripheral circuit is controlled by the first control signal to enable the switched capacitor amplifier to work in an amplification phase, and the adjustable Miller capacitor in the operational amplifier is controlled by the first control signal to have a first capacitance value;
or the amplifier peripheral circuit is controlled by the second control signal to enable the switched capacitor amplifier to work in a reset phase, and the adjustable miller capacitor in the operational amplifier is controlled by the second control signal to have a second capacitance value;
wherein the first capacitance value is smaller than the second capacitance value.
2. The switched capacitor amplifier of claim 1, wherein the adjustable miller capacitor in the operational amplifier comprises a plurality of capacitor branches connected in parallel, each capacitor branch is provided with a miller capacitor, at least one capacitor branch is further connected in series with an adjusting switch controlled by a control signal of the switched capacitor amplifier, and the adjusting switch is controlled by the first control signal to be turned off and controlled by the second control signal to be turned on.
3. The switched capacitor amplifier of claim 2, wherein a return-to-zero resistor is further connected in series to each of the capacitor branches.
4. The switched capacitor amplifier of claim 2, wherein a unity gain buffer is further connected in series with each capacitor branch.
5. The switched capacitor amplifier of any of claims 1-4, wherein the operational amplifier comprises a first stage operational amplifier and a second stage operational amplifier in cascade, the adjustable miller capacitor is connected between the first stage operational amplifier and an output terminal of the operational amplifier, and an open loop gain of the operational amplifier reaches a predetermined threshold.
6. The switched-capacitor amplifier of claim 5, wherein the first-stage operational amplifier is a differential input-stage amplifier and the second-stage operational amplifier is an output-stage amplifier.
7. The switched-capacitor amplifier of claim 5, wherein the first-stage operational amplifier is a folded cascode amplifier and the second-stage operational amplifier is a rail-to-rail output buffer stage amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121855032.1U CN215897691U (en) | 2021-08-09 | 2021-08-09 | Switched capacitor amplifier with adjustable Miller compensation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121855032.1U CN215897691U (en) | 2021-08-09 | 2021-08-09 | Switched capacitor amplifier with adjustable Miller compensation |
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| Publication Number | Publication Date |
|---|---|
| CN215897691U true CN215897691U (en) | 2022-02-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121855032.1U Active CN215897691U (en) | 2021-08-09 | 2021-08-09 | Switched capacitor amplifier with adjustable Miller compensation |
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| Country | Link |
|---|---|
| CN (1) | CN215897691U (en) |
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2021
- 2021-08-09 CN CN202121855032.1U patent/CN215897691U/en active Active
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