CN112003496B - Piezoelectric and optical energy collaborative acquisition circuit - Google Patents
Piezoelectric and optical energy collaborative acquisition circuit Download PDFInfo
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Abstract
The invention discloses a piezoelectric and optical energy collaborative acquisition circuit which is characterized by comprising a piezoelectric transducer, a direct current transducer, a peak value and zero crossing detection module, a delay and pulse signal generator, a maximum power point tracker, a logic controller, a first comparator, a first inverter, an inductor, a first energy storage capacitor, a second energy storage capacitor, a first diode, a second diode, a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a first rectification controllable switch, a second rectification controllable switch, a third rectification controllable switch and a fourth rectification controllable switch; the piezoelectric energy collection circuit has the advantages that the peak voltage extraction of piezoelectric vibration energy and the maximum power point extraction of direct current energy are realized based on a single inductor, and the direct current energy collection of the direct current transducer is controlled by generating sampling signals for the peak value and the zero-crossing detection of the piezoelectric energy, so that the cost is reduced, the energy consumption is saved, the collection power of the piezoelectric energy is improved, and the energy collection efficiency of the whole circuit is higher.
Description
Technical Field
The invention relates to an energy acquisition circuit structure, in particular to a piezoelectric and optical energy cooperative acquisition circuit.
Background
The piezoelectric vibration energy collection is a method for collecting vibration energy in the environment by utilizing the piezoelectric effect of a piezoelectric material, because the output voltage of a piezoelectric plate is an alternating current signal, and general electronic equipment is powered by a direct current power supply, an interface circuit is needed between the piezoelectric plate and the electronic equipment, the conversion from the alternating current voltage to the direct current voltage is realized through the interface circuit, the simplest interface circuit is a full-bridge rectifier circuit, but the efficiency of the full-bridge rectifier circuit is very low, so that a self-powered series synchronous controllable switch energy capture circuit, a parallel synchronous controllable switch energy capture circuit and a synchronous charge extraction circuit are proposed.
The collection of the direct current energy is a method of converting other forms of energy in the environment into electric energy by using a direct current transducer and then collecting the electric energy, for example, a photovoltaic cell can convert light energy in the environment into electric energy, a temperature difference thermoelectric sheet can convert heat energy in the environment into electric energy, however, the output current of the direct current transducers can be reduced along with the increase of the output voltage, and only when the product of the output voltage and the output current of the direct current transducer is maximum, the output power of the direct current transducer can be kept maximum; for example, when the output voltage of the photovoltaic cell is 3/4~4/5 of its open circuit voltage, the output power of the DC transducer can be maintained at a high level, and when the output voltage of the temperature difference thermoelectric sheet is 1/2 of its open circuit voltage, the output power of the DC transducer is maximum.
In order to collect more environmental energy, piezoelectric vibration energy and direct current energy can be collected simultaneously, but the existing multi-source energy collector basically adopts a time-sharing multiplexing scheme to share an inductor, in order to avoid energy backflow, namely high-voltage energy pumps energy to low-voltage energy, the prior art adopts each energy output to be connected with a diode so as to prevent energy backflow; although this approach avoids the energy backflow problem, it increases the power consumption of the circuit and reduces the conversion efficiency of the circuit.
Disclosure of Invention
The invention aims to solve the technical problem of providing a piezoelectric and optical energy cooperative acquisition circuit which can simultaneously acquire piezoelectric vibration energy and other direct current energy sources and has higher overall acquisition efficiency.
The technical scheme adopted by the invention for solving the technical problems is as follows: a piezoelectric and optical energy cooperative acquisition circuit comprises a piezoelectric transducer, a direct current transducer for converting optical energy into direct current voltage, a peak value and zero crossing detection module, a delay and pulse signal generator, a maximum power point tracker, a logic controller, a first comparator, a first inverter, an inductor, a first energy storage capacitor, a second energy storage capacitor, a first diode, a second diode, a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a first rectification controllable switch, a second rectification controllable switch, a third rectification controllable switch and a fourth rectification controllable switch,
one end of the piezoelectric transducer, the positive input end of the first comparator, one end of the first rectification controllable switch and one end of the second rectification controllable switch are connected, the other end of the piezoelectric transducer, the negative input end of the first comparator, one end of the third rectification controllable switch and one end of the fourth rectification controllable switch are connected, the other end of the first rectification controllable switch and the other end of the fourth rectification controllable switch are all grounded, the other end of the second rectification controllable switch, the other end of the third rectification controllable switch, one end of the first rectification controllable switch and the peak value are connected with the input end of the zero-crossing detection module, the output end of the first comparator, the control end of the second rectification controllable switch, the control end of the fourth rectification controllable switch and the input end of the first inverter are connected, the output end of the first inverter, the control end of the first controllable rectifier switch and the control end of the third controllable rectifier switch are connected, the other end of the first controllable rectifier switch, one end of the second controllable rectifier switch and one end of the third controllable rectifier switch are connected, the other end of the second controllable rectifier switch, one end of the first energy storage capacitor, the positive end of the direct current transducer and the voltage input end of the maximum power point tracker are connected, the negative end of the direct current transducer and the other end of the first energy storage capacitor are all grounded, the other end of the third controllable rectifier switch, one end of the inductor and the negative electrode of the first diode are connected, the positive electrode of the first diode is grounded, the other end of the inductor, one end of the fourth controllable rectifier switch and the positive electrode of the second diode are connected, the other end of the fourth controllable switch is grounded, the cathode of the second diode is connected with one end of the second energy storage capacitor, the other end of the second energy storage capacitor is grounded, the peak value is connected with the output end of the zero-crossing detection module, the input end of the delay and pulse signal generator and the third input end of the logic controller, the output end of the delay and pulse signal generator, the control signal input end of the maximum power point tracker and the second input end of the logic controller are connected, the output end of the maximum power point tracker is connected with the first input end of the logic controller, the first output end of the logic controller is connected with the control end of the first controllable switch, and the second output end of the logic controller is connected with the control end of the second controllable switch, a third output end of the logic controller is connected with a control end of the third controllable switch, a fourth output end of the logic controller is connected with a control end of the fourth controllable switch, and a logic expression of the logic controller is as follows:
wherein, among others,
representing an input signal at a first input of said logic controller,
an input signal representing a second input of said logic controller,
an input signal representing a third input of said logic controller,
an inverted signal representing the input signal at the third input of said logic controller,
an inverted signal representing the input signal at the second input of said logic controller,
an output signal representing a first output of said logic controller,
an output signal representing a second output of said logic controller,
an output signal representing a third output of said logic controller,
representing an output signal at a fourth output of said logic controller.
The peak value and zero-crossing detection module comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second comparator, a third comparator and a first AND gate, wherein one end of the first resistor, the positive input end of the second comparator and one end of the first controllable switch are connected, the negative input end of the second comparator is grounded, the other end of the first resistor, one end of the second resistor, one end of the third resistor and the negative input end of the third comparator are connected, the other end of the third resistor, the positive input end of the third comparator and one end of the first capacitor are connected, the other end of the second resistor and the other end of the first capacitor are all grounded, the output end of the second comparator is connected with the first input end of the first AND gate, and the output end of the third comparator is connected with the second input end of the first AND gate, the output end of the first AND gate is connected with the input end of the delay and pulse signal generator and the third input end of the logic controller.
The delay and pulse signal generator comprises a second inverter, a third inverter, a fourth inverter, a second capacitor, a third capacitor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a third diode, a fourth comparator and a fifth comparator, wherein the input end of the second inverter is connected with the output end of the peak value and zero crossing detection module, the output end of the second inverter is connected with one end of the second capacitor, the other end of the second capacitor, one end of the fourth resistor and the input end of the third inverter are connected, the output end of the third inverter is connected with the input end of the fourth inverter, and the output end of the fourth inverter is connected with one end of the fifth resistor, the other end of the fifth resistor, the one end of the sixth resistor, the one end of the seventh resistor and the positive input end of the fourth comparator are connected, the other end of the seventh resistor is connected with the negative electrode of the third diode, the one end of the eighth resistor, the one end of the ninth resistor, the one end of the third capacitor and the negative input end of the fourth comparator are connected, the other end of the eighth resistor is connected with the positive voltage output end of the external dc power supply, the output end of the fourth comparator, the one end of the twelfth resistor and the control signal input end of the maximum power point tracker are connected, the other end of the twelfth resistor, the one end of the tenth resistor, the one end of the eleventh resistor and the positive input end of the fifth comparator are connected, the negative input end of the fifth comparator, the positive input end of the fifth comparator, the negative input end of the sixth comparator, the negative input end of the seventh resistor, the negative input end of the eighth resistor, the negative input end of the sixth resistor and the negative input end of the fifth comparator are connected, One end of the thirteenth resistor is connected with one end of the fourth capacitor, the anode of the third diode, the other end of the tenth resistor, the other end of the thirteenth resistor and the output end of the fifth comparator are connected, and the other end of the fourth resistor, the other end of the sixth resistor, the other end of the ninth resistor, the other end of the eleventh resistor, the other end of the third capacitor and the other end of the fourth capacitor are all grounded.
The maximum power point tracker comprises a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a fifth capacitor, a fifth inverter, a second AND gate, a first NMOS (N-channel metal oxide semiconductor) tube and a sixth comparator, wherein one end of the fourteenth resistor, one end of the sixteenth resistor and the positive end of the DC transducer are connected, the other end of the fourteenth resistor, the source of the first NMOS tube and one end of the fifteenth resistor are connected, the drain of the first NMOS tube, one end of the fifth capacitor and the negative input end of the sixth comparator are connected, the other end of the fifth capacitor and the other end of the fifteenth resistor are all grounded, the gate of the first NMOS tube, the input end of the fifth inverter and the delay are connected with the output end of the pulse signal generator, and the other end of the sixteenth resistor is connected with the positive end of the DC transducer, One end of the seventeenth resistor is connected with the positive input end of the sixth comparator, the other end of the seventeenth resistor, the output end of the sixth comparator and the first input end of the second and gate are connected, the second input end of the second and gate is connected with the output end of the fifth inverter, and the output end of the second and gate is connected with the first input end of the logic controller.
The logic controller comprises a sixth inverter, a seventh inverter, a first OR gate and a second OR gate, the first input end of the first OR gate, the input end of the sixth inverter and the first input end of the second OR gate are connected and used as the third input end of the logic controller, a second input terminal of the first or gate is connected to an input terminal of the seventh inverter and serves as a second input terminal of the logic controller, a second input terminal of the second or gate serves as a first input terminal of the logic controller, an output terminal of the first or gate serves as a first output terminal of the logic controller, the output end of the sixth inverter is used as the second output end of the logic controller, the output end of the seventh inverter is used as the third output end of the logic controller, and the output end of the second or gate is used as the fourth output end of the logic controller.
Compared with the prior art, the piezoelectric energy collection circuit has the advantages that the peak voltage extraction of piezoelectric vibration energy and the maximum power point extraction of direct-current energy are realized based on a single inductor, the direct-current energy converter is controlled to collect the direct-current energy by generating sampling signals according to the peak value and the zero-crossing detection of the piezoelectric energy, the traditional sampling signal generator is omitted, the cost is reduced, the energy consumption is saved, meanwhile, the piezoelectric energy converter is injected with energy within the time period of sampling the direct-current energy by the direct-current energy converter, the voltage at the initial moment of piezoelectric vibration is equal to the open-circuit voltage of the direct-current energy, the piezoelectric energy collection power is improved, and the energy collection efficiency of the whole circuit is higher; the dc transducer may also be a conventional product that converts other energy into dc voltage.
Drawings
FIG. 1 is a schematic diagram of the circuit structure of the present invention;
FIG. 2 is a schematic circuit diagram of an embodiment of a peak and zero crossing detection module;
FIG. 3 is a schematic circuit diagram of an embodiment of a delay and pulse signal generator;
fig. 4 is a schematic circuit diagram of a maximum power point tracker in an embodiment;
fig. 5 is a schematic circuit diagram of the logic controller according to the embodiment.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
A piezoelectric and optical energy cooperative acquisition circuit comprises a piezoelectric transducer PZT, a direct current transducer PV for converting optical energy into direct current voltage, a peak value and zero crossing detection module U1, a delay and pulse signal generator U2, a maximum power point tracker U3, a logic controller U4, a first comparator CMP1, a first inverter INV1, an inductor L, a first energy storage capacitor Cpv, a second energy storage capacitor Cso, a first diode D1, a second diode D2, a first controllable switch S1, a second controllable switch S2, a third controllable switch S3, a fourth controllable switch S4, a first rectifying controllable switch Sr1, a second rectifying controllable switch Sr2, a third rectifying controllable switch Sr3 and a fourth rectifying controllable switch Sr4, one end of the piezoelectric transducer CMP, a positive input end of the first comparator 1, one end of the first rectifying controllable switch Sr1 and one end of the second rectifying controllable switch Sr2 are connected, and the other end of the piezoelectric transducer is connected with the other end of the first rectifying controllable switch Sr 36, The negative input end of a first comparator CMP1, one end of a third rectification controllable switch Sr3 and one end of a fourth rectification controllable switch Sr4 are connected, the other end of the first rectification controllable switch Sr1 and the other end of the fourth rectification controllable switch Sr4 are all grounded, the other end of a second rectification controllable switch Sr2, the other end of a third rectification controllable switch Sr3, one end of a first controllable switch S1 and the peak value are connected with the input end of a zero-crossing detection module U1, the output end of the first comparator CMP1, the control end of a second rectification controllable switch Sr2, the control end of a fourth rectification controllable switch Sr4 and the input end of a first inverter INV1 are connected, the output end of the first inverter INV1, the control end of the first rectification controllable switch Sr1 and the control end of the third rectification controllable switch Sr3 are connected, the other end of the first controllable switch S1, one end of the second controllable switch S2 and one end of the third controllable switch S3 are connected, the other end of the second controllable switch S2 is connected, One end of the first energy storage capacitor Cpv, the positive end of the dc transducer PV and the voltage input end of the maximum power point tracker U3 are connected, the negative end of the dc transducer PV and the other end of the first energy storage capacitor Cpv are both grounded, the other end of the third controllable switch S3, one end of the inductor L and the negative electrode of the first diode D1 are connected, the positive electrode of the first diode D1 is grounded, the other end of the inductor L, one end of the fourth controllable switch S4 and the positive electrode of the second diode D2 are connected, the other end of the fourth controllable switch S4 is grounded, the negative electrode of the second diode D2 is connected to one end of the second energy storage capacitor Csto the ground, the other end of the second energy storage capacitor Csto the ground, the peak value is connected to the output end of the zero-crossing detection module U1, the input end of the delay and pulse signal generator U2 and the third input end of the logic controller U4, the delay is connected to the output end of the pulse signal generator U2, the control signal input end of the maximum power point tracker U3 and the second input end of the logic controller U4, the output end of the maximum power point tracker U3 is connected with the first input end of the logic controller U4, the first output end of the logic controller U4 is connected with the control end of the first controllable switch S1, the second output end of the logic controller U4 is connected with the control end of the second controllable switch S2, the third output end of the logic controller U4 is connected with the control end of the third controllable switch S3, the fourth output end of the logic controller U4 is connected with the control end of the fourth controllable switch S4, and the logic expression of the logic controller U4 is as follows:
wherein, among others,
an input signal representing a first input of a logic controller U4,
an input signal representing a second input of the logic controller U4,
an input signal representing a third input of the logic controller U4,
presentation logic controllerThe inverse of the input signal at the third input of U4,
an inverted signal representing the input signal at the second input of the logic controller U4,
an output signal representing a first output of the logic controller U4,
an output signal representing a second output of the logic controller U4,
an output signal representing a third output of the logic controller U4,
represents the output signal of the fourth output of the logic controller U4.
The peak AND zero-crossing detection module U1 includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second comparator CMP2, a third comparator CMP3 AND a first AND gate AND1, one end of the first resistor R1, the positive input end of the second comparator CMP2 AND one end of the first controllable switch S1 are connected, the negative input end of the second comparator CMP2 is grounded, the other end of the first resistor R1, one end of the second resistor R2, one end of the third resistor R3 AND the negative input end of the third comparator 3 are connected, the other end of the third resistor R3, the positive input end of the third comparator CMP3 AND one end of the first capacitor C3 are connected, the other end of the second resistor R3 AND the other end of the first capacitor C3 are both grounded, the output end of the second comparator 3 is connected to the first AND gate of the first AND gate 3, the third comparator CMP3 AND the input end of the first AND gate control signal generator U3 AND the first AND the output end of the third comparator CMP3 are connected to the first AND input end of the first AND control signal generator U3 And end connection.
The delay and pulse signal generator U2 includes a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fourth resistor R4, a fifth resistor R4, a sixth resistor R4, a seventh resistor R4, an eighth resistor R4, a ninth resistor R4, a tenth resistor R4, an eleventh resistor R4, a twelfth resistor R4, a thirteenth resistor R4, a third diode D4, a fourth comparator CMP4 and a fifth comparator CMP4, an input terminal of the second inverter INV4 is connected to an output terminal of the peak-to-zero-crossing detection module U4, an output terminal of the second inverter INV 72 is connected to one end of the second capacitor C4, another terminal of the second capacitor C4, one end of the fourth resistor R4 and an input terminal of the third inverter 4, an output terminal of the third inverter INV4 is connected to the input terminal of the fourth inverter INV4, an output terminal of the fourth inverter INV4 is connected to the fifth input terminal of the fourth inverter 4, the other end of the fifth resistor R5, one end of the sixth resistor R6, one end of the seventh resistor R7, and the positive input end of the fourth comparator CMP4 are connected, the other end of the seventh resistor R7 is connected to the negative electrode of the third diode D3, one end of the eighth resistor R8, one end of the ninth resistor R9, one end of the third capacitor C3, and the negative input end of the fourth comparator CMP4 are connected, the other end of the eighth resistor R8 is connected to the positive voltage output end of the external dc power supply, the output end of the fourth comparator CMP4, one end of the twelfth resistor R12, and the control signal input end of the maximum power point tracker U3 are connected, the other end of the twelfth resistor R12, one end of the tenth resistor R10, one end of the eleventh resistor R11, and the positive input end of the fifth comparator CMP5 are connected, the negative input end of the fifth comparator 5, one end of the thirteenth resistor R13, and one end of the fourth capacitor C4 are connected, and the positive input end of the positive diode D3 is connected to the third diode CMP 363554, The other end of the tenth resistor R10, the other end of the thirteenth resistor R13 and the output end of the fifth comparator CMP5 are connected, and the other end of the fourth resistor R4, the other end of the sixth resistor R6, the other end of the ninth resistor R9, the other end of the eleventh resistor R11, the other end of the third capacitor C3 and the other end of the fourth capacitor C4 are all grounded. Wherein, the output voltage of the positive voltage output end of the external direct current power supply is 1.8V, 5V or 3.3V.
The maximum power point tracker U3 includes a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a fifth capacitor C5, a fifth inverter INV5, a second AND gate AND2, a first NMOS tube M1 AND a sixth comparator CMP6, one end of the fourteenth resistor R14, one end of the sixteenth resistor R16 AND the positive terminal of the dc converter PV are connected, the other end of the fourteenth resistor R14, the source of the first NMOS tube M1 AND one end of the fifteenth resistor R15 are connected, the drain of the first NMOS tube M1, one end of the fifth capacitor C5 AND the negative input terminal of the sixth comparator CMP6 are connected, the other end of the fifth capacitor C5 AND the other end of the fifteenth resistor R15 are all grounded, the gate of the first NMOS tube M1, the input terminal of the fifth inverter INV5 AND the delay are connected to the output terminal of the pulse signal generator U2, the positive input terminal of the sixteenth resistor R16, the seventeenth resistor R17 AND the sixth comparator CMP6 are connected, the other end of the seventeenth resistor R17, the output end of the sixth comparator CMP6, AND the first input end of the second AND gate AND2 are connected, the second input end of the second AND gate AND2 is connected to the output end of the fifth inverter INV5, AND the output end of the second AND gate AND2 is connected to the first input end of the logic controller U4.
The logic controller U4 includes a sixth inverter INV6, a seventh inverter INV7, a first OR gate OR1 and a second OR gate OR2, a first input terminal of the first OR1, an input terminal of the sixth inverter INV6 and a first input terminal of the second OR gate OR2 are connected and serve as a third input terminal of the logic controller U4, a second input terminal of the first OR gate OR1 is connected to an input terminal of the seventh inverter INV7 and serve as a second input terminal of the logic controller U4, a second input terminal of the second OR gate OR2 serves as a first input terminal of the logic controller U4, an output terminal of the first OR gate OR1 serves as a first output terminal of the logic controller U4, an output terminal of the sixth inverter INV6 serves as a second output terminal of the logic controller U4, an output terminal of the seventh inverter INV7 serves as a third output terminal of the logic controller U4, and an output terminal of the second OR gate OR2 serves as a fourth output terminal 4 of the logic controller U969634.
The working principle of the above embodiment is as follows:
in a positive half period, the voltage of one end of the piezoelectric transducer PZT is higher than that of the other end, at the moment, the first comparator CMP1 outputs a high-level signal, the second rectification controllable switch Sr2 and the fourth rectification controllable switch Sr4 are conducted, one end of the piezoelectric transducer PZT is communicated with one end of the first controllable switch S1, the other end of the piezoelectric transducer PZT is grounded, the open-circuit voltage of the piezoelectric transducer PZT is continuously increased in the positive half period, when the open-circuit voltage of the piezoelectric transducer PZT reaches a peak value, the peak value and zero-crossing detection module U1 generates a controllable switch signal, and a controllable switch control signal is generated by the logic controller U4 to control the conduction of the first controllable switch S1, the third controllable switch S3 and the fourth controllable switch S4, a parasitic capacitor and an inductor L in the piezoelectric transducer PZT form an LC resonance loop, and after 1/4 resonance periods, the electric energy accumulated on the piezoelectric transducer PZT is completely transferred to the inductor L, when the current of the inductor L reaches the peak value, the logic controller U4 immediately controls the first controllable switch S1 and the fourth controllable switch S4 to be turned off, then the energy stored in the inductor L is released to the second storage capacitor Csto through the first diode D1 and the second diode D2, thereby completing the extraction of the piezoelectric vibration energy of the positive half cycle, and then after a short delay, the delay and pulse signal generator U2 generates a sampling signal and transmits the sampling signal to the second input terminal of the logic controller U4, the logic controller U4 controls the first controllable switch S1 and the second controllable switch S2 to be turned on, and at this time, the dc transducer PV charges the first storage capacitor Cpv and the piezoelectric transducer PZT piezoelectric transducer until the voltages of the first storage capacitor Cpv and the piezoelectric transducer PZT are charged to be as high as the open circuit voltage of the dc transducer PV, and then the delay and the sampling signal generated by the pulse signal generator U2 activates the maximum power point tracker U3, when the first energy storage capacitor Cpv reaches the maximum power point, the maximum power point tracker U3 generates a controllable switch control signal through the logic controller U4 to turn on the second controllable switch S2, the third controllable switch S3 and the fourth controllable switch S4, then the energy of the first energy storage capacitor Cpv is gradually transferred to the inductor L, because the energy of the first energy storage capacitor Cpv is released, the voltage at the two ends of the first energy storage capacitor Cpv is reduced, the fourth controllable switch S4 is turned off, and then the energy stored in the inductor L is released to the second energy storage capacitor Csto through the second diode D2, so that the dc converter PV completes the maximum power point extraction of the dc energy;
in a negative half period, one end voltage of the piezoelectric transducer PZT is lower than the other end voltage, at the moment, the first comparator CMP1 outputs a low voltage, the first rectification controllable switch Sr1 and the third rectification controllable switch Sr3 are conducted, the other end of the piezoelectric transducer PZT is communicated with one end of the first controllable switch S1, one end of the piezoelectric transducer PZT is grounded, the open-circuit voltage of the piezoelectric transducer PZT is continuously increased in the negative half period, when the open-circuit voltage of the piezoelectric transducer PZT reaches a peak value, the peak value and zero-crossing detection module U1 generates a controllable switch signal to be sent to the logic controller U4, the logic controller U4 generates a controllable switch control signal to control the conduction of the first controllable switch S1, the third controllable switch S3 and the fourth controllable switch S4, a parasitic capacitor and an inductor L in the piezoelectric transducer PZT form an LC resonance loop, and after 1/4 resonance periods, all electric energy accumulated on the piezoelectric transducer PZT is transferred to the inductor L, when the current of the inductor L reaches the peak value, the logic controller U4 immediately controls the first controllable switch S1 and the fourth controllable switch S4 to be turned off, then the energy stored in the inductor L is released to the second storage capacitor Csto through the first diode D1 and the second diode D2, thereby completing the extraction of the negative half-cycle piezoelectric vibration energy, and then after a short delay, the delay and pulse signal generator U2 generates a sampling signal and transmits the sampling signal to the logic controller U4, the logic controller U4 generates a controllable switch control signal to control the first controllable switch S1 and the second controllable switch S2 to be turned on, and at this time, the dc transducer Cpv charges the first storage capacitor Cpv and the piezoelectric transducer PZT until the voltages of the first storage capacitor Cpv and the piezoelectric transducer PZT are charged to be as high as the open-circuit voltage of the dc transducer PV, and at this time, the sampling signal activates the maximum power point tracker U3, then, a maximum power collecting controllable switch signal of the dc energy collected by the dc energy converter PV is generated, when the first energy storage capacitor Cpv reaches a maximum power point, the logic controller U4 generates a controllable switch control signal to control the second controllable switch S2, the third controllable switch S3 and the fourth controllable switch S4 to be turned on, the energy of the first energy storage capacitor Cpv starts to be transferred to the inductor L, and since the energy of the first energy storage capacitor Cpv is released, the voltage at the two ends of the first energy storage capacitor Cpv will drop, the fourth controllable switch S4 is turned off, and the energy stored in the inductor L is gradually released to the second energy storage capacitor Csto through the second diode D2, so that the dc energy converter PV completes maximum power point extraction of the dc energy.
Claims (5)
1. A piezoelectric and optical energy collaborative acquisition circuit is characterized in that: comprises a piezoelectric transducer, a direct current transducer for converting light energy into direct current voltage, a peak value and zero crossing detection module, a delay and pulse signal generator, a maximum power point tracker, a logic controller, a first comparator, a first inverter, an inductor, a first energy storage capacitor, a second energy storage capacitor, a first diode, a second diode, a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a first rectification controllable switch, a second rectification controllable switch, a third rectification controllable switch and a fourth rectification controllable switch,
one end of the piezoelectric transducer, the positive input end of the first comparator, one end of the first rectification controllable switch and one end of the second rectification controllable switch are connected, the other end of the piezoelectric transducer, the negative input end of the first comparator, one end of the third rectification controllable switch and one end of the fourth rectification controllable switch are connected, the other end of the first rectification controllable switch and the other end of the fourth rectification controllable switch are all grounded, the other end of the second rectification controllable switch, the other end of the third rectification controllable switch, one end of the first rectification controllable switch and the peak value are connected with the input end of the zero-crossing detection module, the output end of the first comparator, the control end of the second rectification controllable switch, the control end of the fourth rectification controllable switch and the input end of the first inverter are connected, the output end of the first inverter, the control end of the first controllable rectifier switch and the control end of the third controllable rectifier switch are connected, the other end of the first controllable rectifier switch, one end of the second controllable rectifier switch and one end of the third controllable rectifier switch are connected, the other end of the second controllable rectifier switch, one end of the first energy storage capacitor, the positive end of the direct current transducer and the voltage input end of the maximum power point tracker are connected, the negative end of the direct current transducer and the other end of the first energy storage capacitor are all grounded, the other end of the third controllable rectifier switch, one end of the inductor and the negative electrode of the first diode are connected, the positive electrode of the first diode is grounded, the other end of the inductor, one end of the fourth controllable rectifier switch and the positive electrode of the second diode are connected, the other end of the fourth controllable switch is grounded, the cathode of the second diode is connected with one end of the second energy storage capacitor, the other end of the second energy storage capacitor is grounded, the peak value is connected with the output end of the zero-crossing detection module, the input end of the delay and pulse signal generator and the third input end of the logic controller, the output end of the delay and pulse signal generator, the control signal input end of the maximum power point tracker and the second input end of the logic controller are connected, the output end of the maximum power point tracker is connected with the first input end of the logic controller, the first output end of the logic controller is connected with the control end of the first controllable switch, and the second output end of the logic controller is connected with the control end of the second controllable switch, a third output end of the logic controller is connected with a control end of the third controllable switch, a fourth output end of the logic controller is connected with a control end of the fourth controllable switch, and a logic expression of the logic controller is as follows:
wherein, among others,
representing an input signal at a first input of said logic controller,
an input signal representing a second input of said logic controller,
an input signal representing a third input of said logic controller,
an inverted signal representing the input signal at the third input of said logic controller,
an inverted signal representing the input signal at the second input of said logic controller,
an output signal representing a first output of said logic controller,
an output signal representing a second output of said logic controller,
an output signal representing a third output of said logic controller,
representing an output signal at a fourth output of said logic controller.
2. A piezoelectric and optical energy cooperative acquisition circuit as claimed in claim 1, wherein: the peak value and zero-crossing detection module comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second comparator, a third comparator and a first AND gate, wherein one end of the first resistor, the positive input end of the second comparator and one end of the first controllable switch are connected, the negative input end of the second comparator is grounded, the other end of the first resistor, one end of the second resistor, one end of the third resistor and the negative input end of the third comparator are connected, the other end of the third resistor, the positive input end of the third comparator and one end of the first capacitor are connected, the other end of the second resistor and the other end of the first capacitor are all grounded, the output end of the second comparator is connected with the first input end of the first AND gate, and the output end of the third comparator is connected with the second input end of the first AND gate, the output end of the first AND gate is connected with the input end of the delay and pulse signal generator and the third input end of the logic controller.
3. A piezoelectric and optical energy cooperative acquisition circuit as claimed in claim 1, wherein: the delay and pulse signal generator comprises a second inverter, a third inverter, a fourth inverter, a second capacitor, a third capacitor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a third diode, a fourth comparator and a fifth comparator, wherein the input end of the second inverter is connected with the output end of the peak value and zero crossing detection module, the output end of the second inverter is connected with one end of the second capacitor, the other end of the second capacitor, one end of the fourth resistor and the input end of the third inverter are connected, the output end of the third inverter is connected with the input end of the fourth inverter, and the output end of the fourth inverter is connected with one end of the fifth resistor, the other end of the fifth resistor, the one end of the sixth resistor, the one end of the seventh resistor and the positive input end of the fourth comparator are connected, the other end of the seventh resistor is connected with the negative electrode of the third diode, the one end of the eighth resistor, the one end of the ninth resistor, the one end of the third capacitor and the negative input end of the fourth comparator are connected, the other end of the eighth resistor is connected with the positive voltage output end of the external dc power supply, the output end of the fourth comparator, the one end of the twelfth resistor and the control signal input end of the maximum power point tracker are connected, the other end of the twelfth resistor, the one end of the tenth resistor, the one end of the eleventh resistor and the positive input end of the fifth comparator are connected, the negative input end of the fifth comparator, the positive input end of the fifth comparator, the negative input end of the sixth comparator, the negative input end of the seventh resistor, the negative input end of the eighth resistor, the negative input end of the sixth resistor and the negative input end of the fifth comparator are connected, One end of the thirteenth resistor is connected with one end of the fourth capacitor, the anode of the third diode, the other end of the tenth resistor, the other end of the thirteenth resistor and the output end of the fifth comparator are connected, and the other end of the fourth resistor, the other end of the sixth resistor, the other end of the ninth resistor, the other end of the eleventh resistor, the other end of the third capacitor and the other end of the fourth capacitor are all grounded.
4. A piezoelectric and optical energy cooperative acquisition circuit as claimed in claim 1, wherein: the maximum power point tracker comprises a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a fifth capacitor, a fifth inverter, a second AND gate, a first NMOS (N-channel metal oxide semiconductor) tube and a sixth comparator, wherein one end of the fourteenth resistor, one end of the sixteenth resistor and the positive end of the DC transducer are connected, the other end of the fourteenth resistor, the source of the first NMOS tube and one end of the fifteenth resistor are connected, the drain of the first NMOS tube, one end of the fifth capacitor and the negative input end of the sixth comparator are connected, the other end of the fifth capacitor and the other end of the fifteenth resistor are all grounded, the gate of the first NMOS tube, the input end of the fifth inverter and the delay are connected with the output end of the pulse signal generator, and the other end of the sixteenth resistor is connected with the positive end of the DC transducer, One end of the seventeenth resistor is connected with the positive input end of the sixth comparator, the other end of the seventeenth resistor, the output end of the sixth comparator and the first input end of the second and gate are connected, the second input end of the second and gate is connected with the output end of the fifth inverter, and the output end of the second and gate is connected with the first input end of the logic controller.
5. A piezoelectric and optical energy cooperative acquisition circuit as claimed in claim 1, wherein: the logic controller comprises a sixth inverter, a seventh inverter, a first OR gate and a second OR gate, the first input end of the first OR gate, the input end of the sixth inverter and the first input end of the second OR gate are connected and used as the third input end of the logic controller, a second input terminal of the first or gate is connected to an input terminal of the seventh inverter and serves as a second input terminal of the logic controller, a second input terminal of the second or gate serves as a first input terminal of the logic controller, an output terminal of the first or gate serves as a first output terminal of the logic controller, the output end of the sixth inverter is used as the second output end of the logic controller, the output end of the seventh inverter is used as the third output end of the logic controller, and the output end of the second or gate is used as the fourth output end of the logic controller.
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