CN112002765A - Silicon rectifier diode chip for three-dimensional integrated array packaging - Google Patents
Silicon rectifier diode chip for three-dimensional integrated array packaging Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 67
- 239000010703 silicon Substances 0.000 title claims abstract description 67
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 66
- 238000004806 packaging method and process Methods 0.000 title abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 239000002131 composite material Substances 0.000 claims abstract description 29
- 238000002161 passivation Methods 0.000 claims abstract description 24
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 20
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 20
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 20
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 10
- 230000007797 corrosion Effects 0.000 claims description 8
- 238000005260 corrosion Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000001704 evaporation Methods 0.000 claims description 7
- QQMBHAVGDGCSGY-UHFFFAOYSA-N [Ti].[Ni].[Ag] Chemical compound [Ti].[Ni].[Ag] QQMBHAVGDGCSGY-UHFFFAOYSA-N 0.000 claims description 6
- 238000013329 compounding Methods 0.000 claims description 6
- ZNKMCMOJCDFGFT-UHFFFAOYSA-N gold titanium Chemical compound [Ti].[Au] ZNKMCMOJCDFGFT-UHFFFAOYSA-N 0.000 claims description 6
- 229910001258 titanium gold Inorganic materials 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 238000003466 welding Methods 0.000 abstract description 12
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 239000007769 metal material Substances 0.000 abstract 1
- 239000005360 phosphosilicate glass Substances 0.000 description 14
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A silicon rectifier diode chip for three-dimensional integrated array packaging has a mesa structure and is passivated into PSG and SiO2The composite structure has the same material for the front and back metal electrodes. The silicon rectifier diode chip has small volume and light weight; using PSG and SiO2The composite passivation structure has the advantages that the chip has high reverse voltage resistance and small reverse leakage, and particularly has good reverse blocking high-temperature characteristics; the front and back metal materials are made of the same material, so that the three-dimensional welding between the chip and the shell and between the chip and the chip is completed at one time, and the efficiency and the reliability of the three-dimensional integrated packaging of the chip are improved. By adopting the silicon rectifier diode chip, 16 chips can be integrated in a space of 7mm multiplied by 10mm multiplied by 2.5mm by double-chip laminated three-dimensional welding, and a 600V 8-path three-dimensional integrated rectifier array device can be checked through high temperature reverse bias at 150 ℃, 1000h and reliability of temperature cycle of-65-175 ℃ and 500 times.
Description
Technical Field
The invention relates to a silicon rectifier diode chip packaged in a three-dimensional integrated array, and belongs to the technical field of integrated power rectifier arrays.
Background
The power rectifier array has the advantages of small volume, high reliability, good space applicability and the like, can replace the traditional discrete rectifier diode device, greatly saves space, simplifies system circuit layout, gradually becomes a key high-performance protection device for solving the problems of reverse connection prevention, leakage prevention and the like in electronic equipment, and particularly has wide requirements in the high-reliability application fields of aerospace, aviation, military, national defense and the like.
With the development of a new generation of equipment power supply system towards miniaturization, light weight, low power consumption and high power density, a system circuit framework is inevitably changed, performance requirements of a rectifier diode chip used in the system are high in reverse withstand voltage, low in reverse leakage, low in forward voltage and high in switching speed, and higher requirements are provided for the chip, so that the size is required to be further reduced, the weight is reduced, the consistency and the reliability of chip parameters are improved, and the integration level of the chip is improved, so that the three-dimensional integration assembly efficiency and the process consistency of multiple chips are further improved, and finally the high-reliability packaging of a three-dimensional integrated rectifier array device is realized.
Structurally, the conventional silicon rectifier diode chip mainly has two structures, namely a plane structure and a mesa structure. Wherein the front surface of the planar structure rectifier diode chip comprises P+An anode current active area and a terminal current passive area, the chip area is large, and simultaneously the chip with a planar structure is welded in a three-dimensional lamination modeThe end is easy to have short circuit of the anode and the cathode, which is not beneficial to the packaging yield and the device reliability; the whole area of the front surface of the mesa structure rectifier diode chip is P+The anode current active region has small chip area, and the reliability of the double-chip three-dimensional laminated welding table-board terminal is high, so that the table-board structure chip is more favorable for realizing a miniaturized three-dimensional integrated rectifier array device.
In terms of process, most of the conventional mesa rectifier diode chips are diffusion diodes. It forms P+NN+The structure is specifically implemented by adopting N-type Czochralski silicon as an original silicon wafer, and performing phosphorus predeposition at a high temperature of not lower than 1200 ℃ to form high-concentration N+Layer, sand blasting the other side of the wafer to remove about 15 microns, performing boron deposition, and performing boron diffusion and phosphorus redistribution at a temperature of not lower than 1200 ℃ for several hours to form high-concentration P+Layer of thereby forming P+NN+And (5) structure. The defects of the table rectifier diode chip produced by the traditional process are as follows: 1) p in chip structure+And the N structure can be formed only by high-temperature diffusion at the temperature of not less than 1200 ℃ for hours, the process processing period is longer, and the deep junction diode chip is particularly not suitable for processing; 2) even if the details of the diffusion process are finely controlled, the diffusion junction depth, the junction doping concentration and the distribution uniformity and consistency are difficult to ensure, so that the stability and consistency of the performance of the produced chip are difficult to improve; 3) the passivation layer of the traditional mesa rectifier diode chip is made of glass or polyimide, so that the chip has poor high-temperature resistance, and particularly, the leakage current of a device is large after double-chip lamination packaging; 4) the anode electrode and the cathode electrode of the chip are mostly made of different materials, the chip adopting the structure usually needs the chip and the bottom plate, the chip and the chip to be respectively welded, so that a double-chip three-dimensional laminated structure can be formed, the welding process is complex, and the consistency and the reliability of the packaging process are not facilitated.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: overcomes the defects of the prior art, provides a silicon rectifier diode chip for three-dimensional integrated array packaging, the chip is of a mesa structure, and the chip passivation is PSG and SiO2The composite structure has the same structure of the front and back metal electrodes. The silicon rectifier diode chip has the advantages of high reverse withstand voltage, small reverse leakage, good high-temperature characteristic and structure suitable for three-dimensional integrated packaging.
The purpose of the invention is realized by the following technical scheme:
a silicon rectifier diode chip for three-dimensional integrated array package is a mesa structure and comprises an anode metal electrode and an anode P+Cathode N-Cathode ohmic contact region N+A cathode metal electrode, a passivation protective layer;
the anode P+Cathode N-Cathode ohmic contact region N+It forms P+N-N+Structure; the anode metal electrode and the cathode metal electrode are made of the same material and are positioned at P+N-N+Two sides of the structure;
the passivation protective layer is PSG and SiO2And (4) compounding a passivation structure.
Preferably, the anode P of the silicon rectifier diode chip packaged in the three-dimensional integrated array is a positive electrode P+The film is a low-resistance boron-doped epitaxial structure, the resistivity is 0.002-0.004 ohm-cm, and the thickness is 15-30 mu m; the cathode N-The film is a phosphorus-doped epitaxial structure, the resistivity is 15-30 omega-cm, and the thickness is 15-50 mu m.
Preferably, the thickness of the silicon rectifier diode chip facing the three-dimensional integrated array package is PSG
SiO2Has a thickness of
Preferably, the anode metal electrode and the cathode metal electrode of the silicon rectifier diode chip packaged in the three-dimensional integrated array are both of a titanium-nickel-silver composite structure or a titanium-gold composite structure.
Preferably, the height of the chip table surface of the silicon rectifier diode chip facing the three-dimensional integrated array package is 50-100 micrometers; the thickness of the chip is 200-220 μm.
The preparation method of the silicon rectifying diode chip comprises the following steps:
selecting a silicon multilayer composite epitaxial material;
step (2), forming a silicon mesa structure on the silicon multilayer composite epitaxial material through corrosion;
step (3) passivating and protecting the table-board through deposition, photoetching and etching to form PSG and SiO2Compounding a passivation structure;
step (4), forming an anode metal electrode on the passivated silicon mesa structure through evaporation, photoetching and corrosion;
step (5), grinding and thinning the back side of the silicon mesa structure of which the anode metal electrode is finished;
and (6) evaporating the thinned silicon mesa structure to form a cathode metal electrode.
In the preparation method of the silicon rectifier diode chip packaged in the three-dimensional integrated array, preferably, the anode metal electrode and the cathode metal electrode are made of the same material, and a titanium-nickel-silver composite structure or a titanium-gold composite structure is selected.
In the preparation method of the silicon rectifier diode chip oriented to the three-dimensional integrated array package, preferably, the PSG has a thickness of
SiO2Has a thickness of
Compared with the prior art, the invention has the following beneficial effects:
(1) according to the silicon rectifier diode chip, the chip is of a table-board structure, and is small in size and light in weight;
(2) the silicon rectifier diode chip terminal passivation protective layer adopts PSG and SiO2A composite passivation structure made of glass or polyimide, PSG and SiO2The composite passivation structure has good protection effect, small reverse leakage current of the chip and good stability of reverse blocking characteristic, and is more favorable for improving the yield and reliability of the double-chip laminated welding;
(3) the silicon rectifier diode chip front and back metal adopts the same structure and is matched with a proper alloy soldering lug, the assembly and the welding of the chip and the bottom plate and the three-dimensional laminated structure of the chip and the chip can be completed at one time, the welding process is simplified, and the packaging efficiency and the consistency and the reliability of the welding process are improved;
(4) by adopting the silicon rectifier diode chip, 16 chips can be integrated in a space of 7mm multiplied by 10mm multiplied by 2.5mm by double-chip laminated three-dimensional welding, and a 600V 8-path three-dimensional integrated rectifier array device can be checked through high temperature reverse bias at 150 ℃, 1000h, temperature cycles of-65 ℃ to 175 ℃ and reliability of 500 times of temperature cycles;
(5) the silicon rectifier diode chip is based on three-layer composite epitaxial materials, and forms deep junction heavy doping P compared with the traditional diffusion type silicon rectifier diode chip+The N structure has simple manufacturing process and simplified chip manufacturing process, and is beneficial to improving the finished product rate of chip manufacturing and the stability and consistency of performance;
(6) the silicon rectifier diode chip adopts a table-board structure, has simple chip terminals, less parasitic parameters and small chip area compared with a planar rectifier diode chip, and is favorable for improving the integration level of a chip of a three-dimensional integrated rectifier array device.
Drawings
FIG. 1 is a cross-sectional view of a silicon rectifier diode chip according to the present invention.
FIG. 2 is a schematic diagram of the vertical height and thickness of a silicon rectifier diode chip according to the present invention.
FIG. 3 is a schematic diagram of a lateral structure of a silicon rectifier diode chip according to the present invention.
Fig. 4 is a schematic cross-sectional view of a three-dimensional stacked package employing a silicon rectifier diode chip according to the present invention.
Fig. 5 is a top view of an 8-way, 16-chip rectifier array using the silicon rectifier diode chip of the present invention.
Attached pictureRecording: 1-Anode P+2-cathode N-3-cathode ohmic contact region N+4-anode metal electrode, 5-cathode metal electrode, and 6-passivation protective layer. T-chip thickness, H-terminal silicon mesa height, L-chip length, W-chip width, D-rectifier chip, P-shell.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
A silicon rectifier diode chip for three-dimensional integrated array package is a mesa structure and comprises an anode metal electrode 4 and an anode P +1. Cathode N -2. Cathode ohmic contact region N +3. A cathode metal electrode 5 and a passivation protective layer 6; the anode P +1. Cathode N -2. Cathode ohmic contact region N +3 it forms P+N-N+Structure; the anode metal electrode 4 and the cathode metal electrode 5 are made of the same material and are positioned at P+N-N+Two sides of the structure; the passivation protective layer 6 is PSG and SiO2And (4) compounding a passivation structure.
As a preferable mode of the present invention, the anode P +1 is a low-resistance boron-doped epitaxial structure, the resistivity is 0.002-0.004 ohm-cm, and the thickness is 15-30 mu m; the cathode N -2 is a phosphorus-doped epitaxial structure, the resistivity is 15 omega cm-30 omega cm, and the thickness is 15 mu m-50 mu m.
A preparation method of a silicon rectifier diode chip facing to a three-dimensional integrated array package comprises the following steps:
selecting a silicon multilayer composite epitaxial material;
step (2), forming a silicon mesa structure on the silicon multilayer composite epitaxial material through corrosion;
step (3) passivating and protecting the table-board through deposition, photoetching and etching to form PSG and SiO2Compounding a passivation structure;
step (4), forming an anode metal electrode on the passivated silicon mesa structure through evaporation, photoetching and corrosion;
step (5), grinding and thinning the back side of the silicon mesa structure of which the anode metal electrode is finished;
and (6) evaporating the thinned silicon mesa structure to form a cathode metal electrode.
As a preferred embodiment of the present invention, the PSG has a thickness of
SiO2Has a thickness of
In a preferred embodiment of the present invention, the anode metal electrode (4) and the cathode metal electrode (5) are both a titanium-nickel-silver composite structure or a titanium-gold composite structure.
As a preferred scheme of the invention, the height of the chip mesa is 50-100 μm; the thickness of the chip is 200-220 μm.
Example 1:
a silicon rectifier diode chip for three-dimensional integrated array package comprises an anode P +1. Cathode N -2. Cathode ohmic contact region N +3. An anode metal electrode 4, a cathode metal electrode 5 and a passivation protective layer 6. As shown in fig. 1.
Anode P+The film is a low-resistance boron-doped epitaxial structure, the resistivity is 0.002-0.004 ohm-cm, and the thickness is 15-30 mu m; the cathode N is a phosphorus-doped epitaxial structure, the resistivity is 15-30 omega-cm, and the thickness is 15-50 mu m; cathode ohmic contact region N+The resistivity is 0.002-0.004 ohm cm, and the thickness is 150-180 mu m; .
The height H of the terminal table surface of the chip is 50-100 mu m; the chip terminal passivation protective layer P is PSG and SiO2A composite passivation structure wherein the PSG has a thickness of
SiO2Has a thickness of
The anode metal electrode A and the cathode metal electrode C are of the same multilayer composite metal structure, a titanium-nickel-silver composite structure or a titanium-gold composite structure, and the total thickness of the metal layers is 0.2-2 mu m; the chip thickness T is 200 μm to 220 μm, as shown in FIG. 2. The chip length L is 1000 μm to 1300 μm, and the chip width W is 1000 μm to 1300 μm, as shown in FIG. 3.
Example 2:
the method for manufacturing the silicon rectifier diode chip in embodiment 1 includes:
1 selecting a silicon multilayer composite epitaxial material, wherein P is+Resistivity of 0.004 ohm cm and thickness of 15 μm; n is a radical of-Resistivity of 15 omega cm and thickness of 30 μm; n is a radical of+Resistivity of 0.004. omega. cm and thickness of 480 μm;
2 forming a silicon mesa structure on the silicon multilayer composite epitaxial material through corrosion, wherein the mesa height is 55 mu m;
3, passivating and protecting the mesa by deposition, photoetching and etching to form PSG and SiO2A composite passivation structure wherein the PSG has a thickness of
SiO2Has a thickness of
4, forming an anode metal electrode by the passivation protection structure through evaporation, photoetching and corrosion, wherein the total thickness of the metal layer is 2 mu m;
5, grinding the back side of the structure of the finished anode metal electrode to thin, and then remaining the thickness of 200 mu m;
6 pairs of thinned wafers are evaporated to form cathode metal electrodes
And 7, dicing the wafer with the cathode metal electrode to obtain a rectifier diode chip, wherein the length L of the chip is 1000-1300 mu m, and the width W of the chip is 1000-1300 mu m.
Example 3:
the 8-channel and 16-channel chip rectifying array adopting the silicon rectifying chip comprises a chip D, a metal wire W, a metal solder S and a metal shell P, and is shown in figure 4. The preparation method comprises the following steps:
(1) selecting a 16-pin metal shell, wherein the volume of an inner cavity is 7mm multiplied by 10mm multiplied by 2.5 mm; selecting a chip welding and sealing material which is made of a PbSnAg solder sheet or an AuSn solder sheet; and selecting an inner lead bonding wire made of gold.
(2) And sequentially installing bottom solder S in the inner cavity of the packaging shell, installing a bottom chip D on the bottom solder, installing upper solder S on the bottom chip, and installing an upper chip D on the upper solder to finish chip assembly.
(3) Putting the assembled chip and the shell into a vacuum sintering furnace to complete chip welding;
(4) after the chip is welded, the structure is subjected to lead bonding in the chip by adopting a bonding machine, and the bonding material is a gold wire to complete the electrical performance leading-out interconnection of the chip;
(5) and (4) putting the structure after the wire bonding into parallel seam welding equipment, and sealing the shell and the cover plate to complete the structure sealing. The structure after sealing is shown in fig. 5. .
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (8)
1. The silicon rectifier diode chip is characterized in that the silicon rectifier diode chip is of a mesa structure and comprises an anode metal electrode (4) and an anode P+(1) Cathode N-(2) Cathode ohmic contact region N+(3) Cathode goldA metal electrode (5) and a passivation protective layer (6);
the anode P+(1) Cathode N-(2) Cathode ohmic contact region N+(3) It forms P+N-N+Structure; the anode metal electrode (4) and the cathode metal electrode (5) are made of the same material and are positioned at P+N-N+Two sides of the structure;
the passivation protective layer (6) is PSG and SiO2And (4) compounding a passivation structure.
2. The silicon rectifier diode chip for the three-dimensional integrated array package as claimed in claim 1, wherein the anode P is formed of a silicon nitride material+(1) The film is a low-resistance boron-doped epitaxial structure, the resistivity is 0.002-0.004 ohm-cm, and the thickness is 15-30 mu m; the cathode N-(2) The film is a phosphorus-doped epitaxial structure, the resistivity is 15-30 omega-cm, and the thickness is 15-50 mu m.
3. The silicon rectifier diode chip oriented to the three-dimensional integrated array package of claim 1, wherein the PSG has a thickness of
SiO2Has a thickness of
4. The silicon rectifier diode chip facing the three-dimensional integrated array package as claimed in claim 1, wherein the anode metal electrode (4) and the cathode metal electrode (5) are both a titanium-nickel-silver composite structure or a titanium-gold composite structure.
5. The silicon rectifier diode chip oriented to the three-dimensional integrated array package of claim 1, wherein the height of the chip mesa is 50 μm to 100 μm; the thickness of the chip is 200-220 μm.
6. The method for preparing the silicon rectifier diode chip facing the three-dimensional integrated array package as claimed in claim 1 or 2, characterized by comprising the following steps:
selecting a silicon multilayer composite epitaxial material;
step (2), forming a silicon mesa structure on the silicon multilayer composite epitaxial material through corrosion;
step (3) passivating and protecting the table-board through deposition, photoetching and etching to form PSG and SiO2Compounding a passivation structure;
step (4), forming an anode metal electrode on the passivated silicon mesa structure through evaporation, photoetching and corrosion;
step (5), grinding and thinning the back side of the silicon mesa structure of which the anode metal electrode is finished;
and (6) evaporating the thinned silicon mesa structure to form a cathode metal electrode.
7. The method for manufacturing a silicon rectifier diode chip packaged in a three-dimensional integrated array according to claim 6, wherein the anode metal electrode and the cathode metal electrode are made of the same material, and a titanium-nickel-silver composite structure or a titanium-gold composite structure is selected.
8. The method for preparing the silicon rectifier diode chip oriented to the three-dimensional integrated array package according to claim 6, wherein the PSG has a thickness of
SiO2Has a thickness of
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| CN108400131A (en) * | 2018-02-02 | 2018-08-14 | 中国电子科技集团公司第五十五研究所 | Interior cascaded structure diode pipe heap |
| CN110911499A (en) * | 2019-09-27 | 2020-03-24 | 北京时代民芯科技有限公司 | Glass-sealed voltage regulating diode, tube core and manufacturing method thereof |
| CN110867415A (en) * | 2019-12-16 | 2020-03-06 | 中国电子科技集团公司第四十三研究所 | Three-dimensional integrated rectifier array and manufacturing method thereof |
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