CN111999627B - MOS (Metal oxide semiconductor) tube verification fixed framework based on voltage drop circuit and verification method - Google Patents
MOS (Metal oxide semiconductor) tube verification fixed framework based on voltage drop circuit and verification method Download PDFInfo
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- CN111999627B CN111999627B CN202010771303.9A CN202010771303A CN111999627B CN 111999627 B CN111999627 B CN 111999627B CN 202010771303 A CN202010771303 A CN 202010771303A CN 111999627 B CN111999627 B CN 111999627B
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- 238000012795 verification Methods 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 17
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 5
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 5
- 239000004065 semiconductor Substances 0.000 title claims abstract description 5
- 238000012360 testing method Methods 0.000 claims abstract description 19
- 238000006243 chemical reaction Methods 0.000 claims abstract description 12
- 238000009413 insulation Methods 0.000 claims description 7
- 238000013461 design Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000006467 substitution reaction Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a voltage drop circuit-based MOS (metal oxide semiconductor) tube verification fixed framework and a verification method, which comprise the following steps: the voltage drop circuit includes: the device comprises a load point conversion chip, a capacitance element and an inductance element, wherein a frame and an insulating plate are arranged above the load point conversion chip, the insulating plate is embedded into the top of the frame, the frame comprises two low-impedance high-conductivity rods, the bottom ends of the two low-impedance high-conductivity rods are respectively connected with the capacitance element and the inductance element, and the top ends of the two low-impedance high-conductivity rods form a test point for MOS tube verification. The invention reduces the verification error of the MOS tube caused by the instability of the test point by arranging the fixed frame, effectively shortens the time required by error judgment and debugging after the verification test, and further reduces the consideration and the cost of adding components.
Description
Technical Field
The invention belongs to the technical field of power supply production inspection, and particularly relates to a MOS (metal oxide semiconductor) tube verification fixed framework based on a voltage drop circuit and a verification method.
Background
Nowadays, POL ("Point of Load" Load converter) is already integrated into an IC chip, and generally the POL IC chip includes: the controller, driver circuit and Power MOSFET, POL IC chip is in the voltage drop circuit, usually designed between MLCC ("chip multilayer ceramic capacitor") and inductor ("inductor") on the real board side.
Based on the relationship between the practical application of the board end and the manufacturing technology of the MOSFET, when designing the step-down switching circuit, the difference between the withstand voltage value that can be borne between the D pole and the S pole of the MOSFET and the voltage value of the input power supply is limited to a certain extent, and generally, the selection of the model of the MOSFET will be selected according to the voltage value of the input power supply and the current value that needs to be borne. However, in practical situations, instability of the selected test point during verification of the design circuit causes resonance of the voltage waveform, so that the actual value and the verification value deviate to some extent, which causes misjudgment of designers and verifiers, so that the overall design exceeds the specification and wastes space.
There is no perfect solution to the above problems, and usually, the method is to only shorten the extension line of the test point, or add a buffer to gradually reduce the resonance of the voltage waveform, but the two methods will reduce the efficiency of the whole buck converter; the extension line of the test point is shortened, so that the mismatching of the extension line of the test point and other credit lines or power lines is increased, the tin coating difficulty is increased, and the time required by the integral verification is relatively increased; the judgment of the verification report is seriously affected if the verification method is not fixed, if the judgment error is caused, a buffer is required to be added or copper is required to be paved to solve the problem of the judgment error, but the additional problems of reducing the overall efficiency of the buck converter, generating heat, increasing the production cost and the like are brought, and the ideal effect is not achieved.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a MOS transistor verification fixing structure and a verification method based on a voltage drop circuit to solve the above-mentioned technical problems.
In a first aspect, the present invention provides a MOS transistor verification fixing structure based on a voltage drop circuit, including: the voltage drop circuit includes: the device comprises a load point conversion chip, a capacitance element and an inductance element, wherein a frame and an insulating plate are arranged above the load point conversion chip, the insulating plate is embedded into the top of the frame, the frame comprises two low-impedance high-conductivity rods, the bottom ends of the two low-impedance high-conductivity rods are respectively connected with the capacitance element and the inductance element, and the top ends of the two low-impedance high-conductivity rods form a test point for MOS tube verification.
Furthermore, the insulation board is insulating plastic plate, just the insulation board size is greater than load point conversion chip, the insulation board is used for avoiding mistake when verifying and touches and cause the short circuit risk.
Furthermore, the framework is arranged on the power panel in a DIP (dual in-line package) piece loading mode.
In a second aspect, the present invention provides a method for verifying a MOS transistor based on a voltage drop circuit, including:
detecting verification values of voltages at two ends of the MOS tube by using the test points formed by the framework;
acquiring an actual value of voltage at two ends of a drain and a source of an MOS tube;
comparing the verification value with an actual value: and if the difference between the verification value and the actual value is within a reasonable error range, judging that the MOS transistor is qualified.
The beneficial effect of the invention is that,
according to the MOS tube verification fixed framework and the verification method based on the voltage drop circuit, provided by the invention, the verification error of the MOS tube caused by the instability of the test point is reduced by arranging the fixed framework, the time required by error judgment and debugging after verification test is effectively shortened, the consideration and cost of adding components are further reduced, the integral design is more perfect, and designers and verification testers can judge the correctness of the drain-source voltage waveform of the MOS tube more quickly and conveniently.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic side sectional view of an architecture of one embodiment of the present invention;
wherein, 1, load point conversion chip; 2. a capacitive element; 3. an inductance element; 4. a frame; 5. an insulating plate; 6. and testing the points.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.
The following explains key terms appearing in the present invention:
ESL (Equivalent Series industries): an equivalent series inductance;
ESR (Equivalent Series Resistance): equivalent series resistance.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
Example 1
As shown in fig. 1, the present embodiment provides a MOS transistor verification fixing structure based on a voltage drop circuit, which includes: the voltage drop circuit includes: the device comprises a load point conversion chip 1, a capacitor element 2 and an inductor element 3, wherein a frame 4 and an insulating plate 5 are arranged above the load point conversion chip 1, the insulating plate 5 is embedded into the top of the frame 4, the frame 4 comprises two low-impedance high-conductivity rods, the bottom ends of the two low-impedance high-conductivity rods are respectively connected with the capacitor element 2 and the inductor element 3, and the top ends of the two low-impedance high-conductivity rods form a test point 6 for verifying an MOS (metal oxide semiconductor) tube; the insulating plate is an insulating plastic plate, and the size of the insulating plate is larger than that of the load point conversion chip; the framework is arranged on the power panel in a DIP (dual in-line package) piece loading mode.
In addition, an embodiment of the present invention provides a method for verifying an MOS transistor based on a voltage drop circuit, where the method is based on a fixed structure for verifying an MOS transistor based on a voltage drop circuit, and the method includes:
detecting verification values of voltages at two ends of the MOS tube by using the test points formed by the framework;
acquiring the actual value of the voltage at two ends of the drain and the source of the MOS tube;
comparing the verification value with an actual value: and if the difference between the verification value and the actual value is within a reasonable error range, judging that the MOS transistor is qualified.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions should be within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure and the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (3)
1. A fixed framework is verified to MOS pipe based on voltage drop circuit, its characterized in that includes: the voltage drop circuit includes: the device comprises a load point conversion chip, a capacitance element and an inductance element, wherein a frame and an insulating plate are arranged above the load point conversion chip, the insulating plate is embedded into the top of the frame, the frame comprises two low-impedance high-conductivity rods, the bottom ends of the two low-impedance high-conductivity rods are respectively connected with the capacitance element and the inductance element, and the top ends of the two low-impedance high-conductivity rods form a test point for verifying an MOS (metal oxide semiconductor) tube;
the insulation board is insulating plastic plate, just the insulation board size is greater than load point conversion chip, the insulation board is used for avoiding mistake when verifying to touch and causes the short circuit risk.
2. The MOS tube verification fixing structure based on the voltage drop circuit as claimed in claim 1, wherein the structure is disposed on the power panel by means of an upper DIP device.
3. A method for verifying MOS transistors based on a droop circuit, the method being based on the fixed architecture for verifying MOS transistors based on a droop circuit as claimed in any one of claims 1 to 2, the method comprising:
detecting verification values of voltages at two ends of the MOS tube by using the test points formed by the framework;
acquiring the actual value of the voltage at two ends of the drain and the source of the MOS tube;
comparing the verification value with an actual value: and if the difference between the verification value and the actual value is within a reasonable error range, judging that the MOS transistor is qualified.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010771303.9A CN111999627B (en) | 2020-08-04 | 2020-08-04 | MOS (Metal oxide semiconductor) tube verification fixed framework based on voltage drop circuit and verification method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010771303.9A CN111999627B (en) | 2020-08-04 | 2020-08-04 | MOS (Metal oxide semiconductor) tube verification fixed framework based on voltage drop circuit and verification method |
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| Publication Number | Publication Date |
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| CN111999627A CN111999627A (en) | 2020-11-27 |
| CN111999627B true CN111999627B (en) | 2022-12-16 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201611352U (en) * | 2009-12-30 | 2010-10-20 | 比亚迪股份有限公司 | Test circuit for MOSFET |
| CN206024169U (en) * | 2016-08-30 | 2017-03-15 | 佛山冠今光电科技有限公司 | A kind of high PF circuit of low cost by differential mode test of being struck by lightning |
| CN207380122U (en) * | 2017-11-13 | 2018-05-18 | 欣旺达电子股份有限公司 | MOSFET hourglass source electrode resistance test circuits |
| CN110556788A (en) * | 2019-08-21 | 2019-12-10 | 苏州浪潮智能科技有限公司 | Protection method of synchronous buck conversion circuit and novel synchronous buck conversion circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003083496A1 (en) * | 2002-04-02 | 2003-10-09 | Philips Intellectual Property & Standards Gmbh | Testable cascode circuit and method for testing the same |
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2020
- 2020-08-04 CN CN202010771303.9A patent/CN111999627B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201611352U (en) * | 2009-12-30 | 2010-10-20 | 比亚迪股份有限公司 | Test circuit for MOSFET |
| CN206024169U (en) * | 2016-08-30 | 2017-03-15 | 佛山冠今光电科技有限公司 | A kind of high PF circuit of low cost by differential mode test of being struck by lightning |
| CN207380122U (en) * | 2017-11-13 | 2018-05-18 | 欣旺达电子股份有限公司 | MOSFET hourglass source electrode resistance test circuits |
| CN110556788A (en) * | 2019-08-21 | 2019-12-10 | 苏州浪潮智能科技有限公司 | Protection method of synchronous buck conversion circuit and novel synchronous buck conversion circuit |
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| CN111999627A (en) | 2020-11-27 |
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