CN111999627B - MOS (Metal oxide semiconductor) tube verification fixed framework based on voltage drop circuit and verification method - Google Patents

Abstract

The invention provides a voltage drop circuit-based MOS (metal oxide semiconductor) tube verification fixed framework and a verification method, which comprise the following steps: the voltage drop circuit includes: the device comprises a load point conversion chip, a capacitance element and an inductance element, wherein a frame and an insulating plate are arranged above the load point conversion chip, the insulating plate is embedded into the top of the frame, the frame comprises two low-impedance high-conductivity rods, the bottom ends of the two low-impedance high-conductivity rods are respectively connected with the capacitance element and the inductance element, and the top ends of the two low-impedance high-conductivity rods form a test point for MOS tube verification. The invention reduces the verification error of the MOS tube caused by the instability of the test point by arranging the fixed frame, effectively shortens the time required by error judgment and debugging after the verification test, and further reduces the consideration and the cost of adding components.

Description

A fixed structure and verification method for MOS transistor verification based on voltage drop circuit

technical field

The invention belongs to the technical field of power supply production inspection, and in particular relates to a voltage-drop circuit-based MOS tube verification fixed structure and verification method.

Background technique

Nowadays, POL ("Point of Load", point-of-load converter) has been integrated into the IC chip. Usually, the POL IC chip includes: controller, drive circuit and Power MOSFET. On the actual board side, the POL IC chip is in the voltage drop circuit. Typically designed between MLCCs ("Chip Multilayer Ceramic Capacitors") and Indoctors ("Inductors").

Based on the actual application of the board and the relationship between the MOSFET manufacturing technology, when designing a step-down switching circuit, there is a certain limit to the difference between the withstand voltage value between the D pole and the S pole of the MOSFET and the voltage value of the input power supply. , Generally, in the selection of the MOSFET model, it will be selected according to the actual voltage value of the input power supply and the current value that needs to be borne. But in practice, the instability of the test points selected when verifying the design circuit causes the resonance of the voltage waveform, which makes the actual value deviate from the verified value, causing misjudgment by designers and verifiers, so that the overall design exceeds specs, waste of space.

There is no perfect solution to the above problems at present. The usual method is to only shorten the extension line of the test point, or add a buffer to gradually reduce the resonance of the voltage waveform, but these two methods will reduce the overall buck converter. Among them, shortening the extension line of the test point will increase the doubts that the extension line of the test point will be short-circuited with other credit lines or power lines, and increase the difficulty of tinning, and the time required for the overall verification will be relatively increased; the verification method The judgment of the unfixed verification report has a serious impact. If the misjudgment is caused, there is no way to distinguish it. It is necessary to increase the buffer or copper to solve the misjudgment problem, but this will reduce the overall efficiency of the step-down converter and generate Additional problems such as heat and increased production costs cannot achieve the desired effect.

Contents of the invention

In view of the above-mentioned deficiencies in the prior art, the present invention provides a MOS transistor verification fixed framework and verification method based on a voltage drop circuit to solve the above-mentioned technical problems.

In the first aspect, the present invention provides a MOS transistor verification and fixed architecture based on a voltage drop circuit, including: the voltage drop circuit includes: a point-of-load conversion chip, a capacitive element, and an inductive element, and a frame is set above the point-of-load conversion chip , an insulating plate, the insulating plate is embedded in the top of the frame, the frame includes two low-impedance high-conduction rods, the bottom ends of the two low-impedance high-conduction rods are respectively connected to the capacitive element and the inductive element, and the two low-impedance high-conduction rods are respectively connected to the capacitive element and the inductive element The top of the high-impedance conduction rod constitutes a test point for MOS tube verification.

Further, the insulating plate is an insulating plastic plate, and the size of the insulating plate is larger than the point-of-load conversion chip, and the insulating plate is used to avoid the risk of short circuit caused by false touch during verification.

Further, the structure is set on the power board by means of a DIP component.

In a second aspect, the present invention provides a method for verifying a MOS transistor based on a voltage drop circuit, including:

Use the test points formed by the structure to detect the verification value of the voltage at both ends of the MOS tube;

Obtain the actual value of the voltage across the drain and source of the MOS transistor;

Comparing the verification value with the actual value: if the difference between the verification value and the actual value is within a reasonable error range, it is judged that the MOS tube is qualified.

The beneficial effect of the present invention is that,

The present invention provides a MOS tube verification fixed framework and verification method based on a voltage drop circuit. By setting a fixed frame, the verification error of the MOS tube caused by the instability of the test point is reduced, and the error correction due to misjudgment after the verification test is effectively shortened. The time required further reduces the consideration and cost of adding components, making the overall design more perfect, allowing designers and verification testers to judge the correctness of the drain-source voltage waveform of the MOS tube more quickly and conveniently.

In addition, the design principle of the present invention is reliable, the structure is simple, and has very wide application prospects.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, In other words, other drawings can also be obtained from these drawings on the premise of not paying creative work.

Fig. 1 is a side sectional structural schematic diagram of the framework of an embodiment of the present invention;

Among them, 1. Load point conversion chip; 2. Capacitive element; 3. Inductive element; 4. Frame; 5. Insulating board; 6. Test point.

detailed description

In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described The embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention based on specific situations.

The following key terms appearing in the present invention are explained:

ESL (Equivalent Series Inductance): equivalent series inductance;

ESR (Equivalent Series Resistance): equivalent series resistance.

The present invention will be described in detail below with reference to the accompanying drawings and examples.

Example 1

As shown in FIG. 1 , this embodiment provides a MOS transistor verification and fixed architecture based on a voltage drop circuit, including: the voltage drop circuit includes: a point-of-load conversion chip 1, a capacitive element 2, and an inductive element 3. A frame 4 and an insulating plate 5 are arranged above the point conversion chip 1, and the insulating plate 5 is embedded in the top of the frame 4. The frame 4 includes two low-impedance and high-conduction rods, and the bottom ends of the two low-impedance and high-conduction rods are respectively connected to the The capacitive element 2 and the inductive element 3 are connected, and the tops of the two low-impedance and high-conduction rods form the test point 6 for MOS tube verification; the insulating plate is an insulating plastic plate, and the size of the insulating plate is larger than that of the point-of-load conversion chip; the structure is set on the power board by way of DIP parts.

The frame 4 is a low-impedance high-conduction material, which can effectively reduce the phenomenon of extra ESR and ESL generated by unstable voltage test points. The insulating plate 5 is used to avoid the risk of short circuit caused by false touch during verification, and can avoid There is a risk of short circuit caused by false assembly in the factory trial production stage or test verification stage, or even in the mass production stage. In this embodiment, evaluation and design have been added in the initial board decoration stage, and the test verification point is fixed. Through the way of DIP parts, the crosstalk of signals and the work difficulty of the decoration process are reduced.

In addition, an embodiment of the present invention provides a method for verifying a MOS transistor based on a voltage drop circuit. The method is based on a fixed architecture for verifying a MOS transistor based on a voltage drop circuit. The method includes:

Use the test points formed by the structure to detect the verification value of the voltage at both ends of the MOS tube;

Obtain the actual value of the voltage across the drain and source of the MOS transistor;

Comparing the verification value with the actual value: if the difference between the verification value and the actual value is within a reasonable error range, it is judged that the MOS tube is qualified.

Although the present invention has been described in detail in conjunction with preferred embodiments with reference to the accompanying drawings, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, those skilled in the art can make various equivalent modifications or replacements to the embodiments of the present invention, and these modifications or replacements should be within the scope of the present invention/any Those skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention, and all should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (3)

1. A MOS tube verification fixed architecture based on a voltage drop circuit, characterized in that, comprising: the voltage drop circuit includes: a point-of-load conversion chip, a capacitive element and an inductance element, and a framework, An insulating plate, the insulating plate is embedded in the top of the frame, the frame includes two low-impedance high-conduction rods, the bottom ends of the two low-impedance high-conduction rods are respectively connected to the capacitive element and the inductive element, and the two low-impedance The top of the high conduction bar constitutes the test point for MOS tube verification; The insulating plate is an insulating plastic plate, and the size of the insulating plate is larger than the point-of-load conversion chip, and the insulating plate is used to avoid the risk of short circuit caused by false touch during verification. 2. A MOS transistor verification and fixing structure based on a voltage drop circuit according to claim 1, wherein the structure is arranged on the power board by means of a DIP component. 3. A method for verifying a MOS transistor based on a voltage drop circuit, said method being based on a fixed architecture for verifying a MOS transistor based on a voltage drop circuit according to any one of claims 1-2, characterized in that said method includes : Use the test points formed by the structure to detect the verification value of the voltage at both ends of the MOS tube; Obtain the actual value of the voltage across the drain and source of the MOS transistor; Comparing the verification value with the actual value: if the difference between the verification value and the actual value is within a reasonable error range, it is judged that the MOS tube is qualified.

Images