CN111999590A - Startup and shutdown test circuit and startup and shutdown test system - Google Patents
Startup and shutdown test circuit and startup and shutdown test system Download PDFInfo
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- CN111999590A CN111999590A CN202011168379.9A CN202011168379A CN111999590A CN 111999590 A CN111999590 A CN 111999590A CN 202011168379 A CN202011168379 A CN 202011168379A CN 111999590 A CN111999590 A CN 111999590A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
Abstract
The invention provides a startup and shutdown test circuit and a startup and shutdown test system, wherein the startup and shutdown test circuit comprises a signal conversion circuit, a control circuit connected with the signal conversion circuit, and at least one test interface connected with the control circuit; the signal conversion circuit is used for connecting an upper computer, receiving a control signal sent by the upper computer and converting the control signal into a preset logic level; the control circuit is used for receiving the converted control signal and transmitting a power supply opening instruction and a power supply closing instruction to the at least one test interface according to the switching times and the switching intervals in the control signal; the at least one test interface is used for connecting tested equipment, sending the power supply opening instruction and the power supply closing instruction to the tested equipment and transmitting a communication signal after the tested equipment is opened to the upper computer through the signal conversion circuit. The invention can realize the automatic test of the on/off of the tested equipment and improve the efficiency of the on/off test.
Description
Technical Field
The invention relates to the field of hardware testing, in particular to a startup and shutdown testing circuit and a startup and shutdown testing system.
Background
In the existing on-off test process of the equipment, the on-off test of the equipment is generally completed manually by a tester, so that the efficiency is low when a large number of on-off test tasks of the equipment are performed.
Disclosure of Invention
In view of the above problems, the present invention provides a power on/off test circuit and a power on/off test system to achieve an automatic test of power on/off of a device under test, and improve the efficiency of the power on/off test.
In order to achieve the purpose, the invention adopts the following technical scheme:
a startup and shutdown test circuit comprises a signal conversion circuit, a control circuit connected with the signal conversion circuit, and at least one test interface connected with the control circuit;
the signal conversion circuit is used for connecting an upper computer, receiving a control signal sent by the upper computer and converting the control signal into a preset logic level;
the control circuit is used for receiving the converted control signal and transmitting a power supply opening instruction and a power supply closing instruction to the at least one test interface according to the switching times and the switching intervals in the control signal;
the at least one test interface is used for connecting tested equipment, sending the power supply opening instruction and the power supply closing instruction to the tested equipment and transmitting a communication signal after the tested equipment is opened to the upper computer through the signal conversion circuit.
Preferably, in the power on/off test circuit, the signal conversion circuit includes a logic level conversion chip and an RS232 interface;
a first TTL level output pin of the logic level conversion chip is connected with a second pin of the RS232 interface;
a first RS232 level input pin of the logic level conversion chip is connected with a third pin of the RS232 interface;
a second RS232 level input pin and a second TTL level input pin of the logic level conversion chip are grounded;
and a fifth pin of the RS232 interface is grounded.
Preferably, in the power on/off test circuit, the control circuit comprises a microcontroller;
a first asynchronous receiving and transmitting pin of the microcontroller is connected with a first TTL level input pin of the logic level conversion chip;
and a second asynchronous receiving and transmitting pin of the microcontroller is connected with a first RS232 level output pin of the logic level conversion chip.
Preferably, in the power on/off test circuit, the microcontroller comprises a GD32F205xx series single chip microcomputer.
Preferably, the power on/off test circuit further includes a clock circuit connected to the control circuit;
the clock circuit is used for providing a clock signal for the control circuit.
Preferably, in the power on/off test circuit, the clock circuit includes an active crystal oscillator, a resistor, and a capacitor;
a third pin of the active crystal oscillator is connected to an oscillator pin of the microcontroller through the resistor;
a fourth pin of the active crystal oscillator is connected with a driving power supply and is grounded through a capacitor;
and the second pin of the active crystal oscillator is grounded.
The invention also provides a startup and shutdown test system which comprises an upper computer and the startup and shutdown test circuit.
Preferably, in the power on/off test system, the upper computer generates a corresponding control signal after receiving the input power on/off times and power on/off intervals and sends the control signal to the power on/off test circuit;
the power on/off test circuit sends a power on instruction and a power off instruction to the tested equipment according to the power on/off times and the power on/off intervals in the control signal, and transmits a communication signal after the tested equipment is turned on to the upper computer;
and the upper computer records the received times of the communication signals as the successful times of the startup and shutdown of the tested equipment.
Preferably, in the power on/off test system, after receiving the connection signal, the upper computer controls the power on/off test circuit to immediately send the power off instruction.
Preferably, in the power on/off test system, when the upper computer does not receive the connection signal through the power on/off interval, the power on/off test circuit is controlled to stop sending the power on command and the power off command.
The invention provides a startup and shutdown test circuit, which comprises a signal conversion circuit, a control circuit connected with the signal conversion circuit, and at least one test interface connected with the control circuit; the signal conversion circuit is used for connecting an upper computer, receiving a control signal sent by the upper computer and converting the control signal into a preset logic level; the control circuit is used for receiving the converted control signal and transmitting a power supply opening instruction and a power supply closing instruction to the at least one test interface according to the switching times and the switching intervals in the control signal; the at least one test interface is used for connecting tested equipment, sending the power supply opening instruction and the power supply closing instruction to the tested equipment and transmitting a communication signal after the tested equipment is opened to the upper computer through the signal conversion circuit. The on-off test circuit sends the power supply opening instruction and the power supply closing instruction to the tested equipment through the transmission of the control signal of the upper computer, and transmits the communication signal after the tested equipment is opened to the upper computer, thereby realizing the automatic test of the on-off of the tested equipment and improving the efficiency of the on-off test.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.
Fig. 1 is a schematic structural diagram of a power on/off test circuit according to embodiment 1 of the present invention;
fig. 2 is a schematic structural diagram of a power on/off test circuit according to embodiment 2 of the present invention;
fig. 3 is a schematic structural diagram of another startup and shutdown test circuit provided in embodiment 2 of the present invention;
fig. 4 is a schematic structural diagram of a third startup and shutdown test circuit provided in embodiment 2 of the present invention;
fig. 5 is a schematic circuit structure diagram of a signal conversion circuit according to embodiment 3 of the present invention;
fig. 6 is a schematic circuit structure diagram of a clock circuit provided in embodiment 3 of the present invention;
fig. 7 is a schematic structural diagram of a startup and shutdown test system according to embodiment 4 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
Example 1
Fig. 1 is a schematic structural diagram of a power on/off test circuit provided in embodiment 1 of the present invention.
The on/off test circuit 100 comprises a signal conversion circuit 110, a control circuit 120 connected with the signal conversion circuit 110, and at least one test interface 130 connected with the control circuit 120;
the signal conversion circuit 110 is used for connecting an upper computer, receiving a control signal sent by the upper computer and converting the control signal into a preset logic level;
in an embodiment of the present invention, the upper computer includes a computer device with computing capability, such as a computer, a tablet computer, and a mobile phone. The upper computer can be connected with the signal conversion circuit 110 by an interface conversion mode, for example, when the signal conversion circuit 110 provides an RS232 interface, the computer can be connected with the signal conversion circuit 110 and communicate by using a USB to RS232 interface data line, so that the upper computer communicates with the startup and shutdown test circuit 100.
In the embodiment of the present invention, the control signal sent by the upper computer includes the number of times that the device to be tested needs to be turned on and off, and the interval between each time of turning on and turning off, that is, the on and off interval, the number of times of turning on and turning off and the on and off interval are input by the user in the upper computer, and the upper computer can generate a corresponding control signal after receiving the number of times of turning on and turning off and the on and off interval, and transmit the control signal to the signal conversion circuit 110.
In the embodiment of the present invention, the switch test circuit includes a signal conversion circuit 110, and the signal conversion circuit 110 converts the control signal sent by the upper computer into a preset logic level, so that the converted control signal is adapted to the control circuit 120. For example, when the host computer is a computer, the control signal transmitted through the RS232 interface is an RS232 level signal, and the RS232 level signal can be converted into a TTL level signal (TTL, transistor-transistor logic) after passing through the signal conversion circuit 110.
The control circuit 120 is configured to receive the converted control signal, and transmit a power on instruction and a power off instruction to the at least one test interface 130 according to the number of times of power on/off and the power on/off interval in the control signal;
in the embodiment of the present invention, after receiving the converted control signal, for example, after receiving the TTL level control signal, the control circuit 120 may extract the corresponding on/off times and the on/off interval information from the control signal, and transmit the power on instruction and the power off instruction to the test interface 130 according to the on/off times and the on/off interval, so that the device under test connected to the test interface 130 receives the power on instruction to perform the power on operation, and performs the power off operation when receiving the power off instruction. That is, the control circuit 120 sends a power on command to the device under test through the test interface 130, and sends a power off command to the device under test after the power on/off interval, thereby completing a power on/off test. After the power on/off test is completed once, the next power on command may be sent immediately, or after a preset time, the next power on command may be sent, which is not limited herein. According to the control instruction of the upper computer, the control circuit 120 can select the number of the test interfaces 130 to be outputted and the specific test interface 130.
The at least one test interface 130 is used for connecting a device to be tested, sending the power on instruction and the power off instruction to the device to be tested, and transmitting a connection signal after the device to be tested is turned on to the upper computer through the signal conversion circuit 110.
In the embodiment of the invention, whether the tested equipment is normally started or not is determined through the communication signal of the tested equipment. The upper computer can be connected with the tested equipment through the network through the serial port, after the tested equipment receives the power supply starting instruction and is successfully started, the upper computer can receive the connection signal of the tested equipment, the successful starting of the tested equipment can be determined, the upper computer can record the successful starting number once, and the connection signal is not received after the startup interval, so the starting fails. Similarly, after the tested device receives the power supply closing instruction and is successfully closed, the upper computer stops receiving the connection signal of the tested device, that is, the tested device can be determined to be successfully closed, the upper computer can record the number of successful one-time shutdown, and the upper computer fails to receive the connection signal after the shutdown interval. The plurality of test interfaces 130 can be used to simultaneously perform the on/off test of a plurality of devices under test.
In the embodiment of the present invention, for example, the at least one test interface 130 may be provided with an interface and a corresponding pin, which are connected to the RS232 interface of the signal conversion circuit 110, so that the upper computer can perform communication connection with the device under test, and perform on/off judgment on the device under test. The startup and shutdown test circuit sends the power supply opening instruction and the power supply closing instruction to the tested equipment through the transmission of the control signal of the upper computer, and transmits the communication signal after the tested equipment is opened to the upper computer, so that the automatic test of the startup and shutdown of the tested equipment is realized, and the efficiency of the startup and shutdown test is improved.
Example 2
Fig. 2 is a schematic structural diagram of a power on/off test circuit according to embodiment 2 of the present invention.
The on/off test circuit 200 comprises a signal conversion circuit 210, a control circuit 220 connected with the signal conversion circuit 210, and at least one test interface 230 connected with the control circuit 220;
the signal conversion circuit 210 is used for connecting an upper computer, receiving a control signal sent by the upper computer, and converting the control signal into a preset logic level;
the control circuit 220 is configured to receive the converted control signal, and transmit a power on instruction and a power off instruction to the at least one test interface 230 according to the number of times of power on/off and the power on/off interval in the control signal;
the at least one test interface 230 is used for connecting a device to be tested, sending the power on command and the power off command to the device to be tested, and transmitting a connection signal after the device to be tested is turned on to the upper computer through the signal conversion circuit 210.
The signal conversion circuit 210 comprises a logic level conversion chip 211 and an RS232 interface 212;
a first TTL level output pin 2111 of the logic level conversion chip 211 is connected to a second pin 2121 of the RS232 interface 212;
the first RS232 level input pin 2112 of the logic level conversion chip 211 is connected to the third pin 2122 of the RS232 interface 212;
a second RS232 level input pin 2113 and a second TTL level input pin 2114 of the logic level conversion chip 211 are grounded;
the fifth pin 2123 of the RS232 interface 212 is connected to ground.
Fig. 3 is a schematic structural diagram of another startup and shutdown test circuit provided in embodiment 2 of the present invention.
In the power on/off test circuit 200, the control circuit 220 includes a microcontroller 221;
the first asynchronous receiving and transmitting pin 2211 of the microcontroller 221 is connected to the first TTL level input pin 2114 of the logic level conversion chip 211;
the second asynchronous receiving and transmitting pin 2212 of the microcontroller 221 is connected to the first RS232 level output pin 2115 of the logic level conversion chip 211.
In the embodiment of the present invention, the microcontroller 221 includes a GD32F205xx series single chip microcomputer, for example, a GD32F205RGT6 single chip microcomputer, which is not limited herein.
Fig. 4 is a schematic structural diagram of a third startup and shutdown test circuit provided in embodiment 2 of the present invention.
The power on/off test circuit 200 further includes a clock circuit 240 connected to the control circuit 220;
the clock circuit 240 is used to provide a clock signal to the control circuit 220.
The clock circuit 240 includes an active crystal resonator 241, a resistor 242, and a capacitor 243;
the third pin of the active crystal oscillator 241 is connected to the oscillator pin 2213 of the microcontroller 221 through the resistor 242;
a fourth pin of the active crystal oscillator 241 is connected to a driving power supply and grounded through a capacitor 243;
the second pin of the active crystal resonator 241 is grounded.
Example 3
Fig. 5 is a schematic circuit structure diagram of a signal conversion circuit according to embodiment 3 of the present invention.
The signal conversion circuit 500 includes a logic level conversion chip 510 and an RS232 interface 520;
the model of the logic level shift chip 510 is SM3232AE, and a capacitor C16 is connected between the pin No. 1 and the pin No. 3 of the logic level shift chip 510; a capacitor C15 is connected between the pin No. 4 and the pin No. 5 of the logic level conversion chip 510; the pin 11 of the logic level conversion chip 510 is a first TTL level input pin, and the pin 11 is connected to an asynchronous transceiving pin of the microcontroller through a resistor R35; the No. 10 pin is a second TTL level input pin, and the No. 10 pin is grounded; the pin 12 is a first RS232 level output pin, and the pin 12 is connected to an asynchronous transceiving pin of the microcontroller through a resistor R36; a capacitor C19 is connected between the No. 16 pin and the No. 2 pin of the logic level conversion chip 510, the No. 16 pin is connected with a driving power supply VCC and is grounded through a capacitor C20; the No. 15 pin is grounded; pin No. 6 is grounded through a capacitor C18; pin number 8 is grounded.
The RS232 interface includes 9 pins, and pin 2 is connected to pin 14 of the logic level conversion chip 510 through a resistor R34, that is, the first TTL level output pin of the logic level conversion chip 510; pin 3 of the RS232 interface is connected to pin 13 of the logic level shift chip 510 through a resistor R33, that is, the first RS232 level input pin of the logic level shift chip 510.
Fig. 6 is a schematic circuit structure diagram of a clock circuit according to embodiment 3 of the present invention.
The clock circuit 600 includes an active crystal oscillator 610, wherein the active crystal oscillator 610 is a 12MHz active crystal oscillator. Pin 2 of the active crystal oscillator 610 is grounded; the No. 3 pin is connected to an oscillator pin of the microcontroller through a resistor R10 to provide an oscillation signal for the microcontroller; pin No. 4 of the active crystal oscillator 610 is connected to a driving power VCC and grounded through a capacitor C1222.
Example 4
Fig. 7 is a schematic structural diagram of a startup and shutdown test system according to embodiment 4 of the present invention.
The power on/off test system 700 includes an upper computer 710 and the power on/off test circuit 720 in the above embodiments.
In the embodiment of the present invention, the upper computer 710 generates a corresponding control signal after receiving the input power on/off times and power on/off intervals, and sends the control signal to the power on/off test circuit 720; the power on/off test circuit 720 sends a power on instruction and a power off instruction to the tested device according to the power on/off times and the power on/off intervals in the control signal, and transmits a connection signal after the tested device is turned on to the upper computer 710; the upper computer 710 records the received times of the communication signals, and the times are the successful times of the startup and shutdown of the tested equipment.
In the embodiment of the present invention, the upper computer 710 includes a computer device such as a computer, and an application program may be set in the upper computer 710, and the application program provides the number of times of power on/off and the input interface of the power on/off interval, so as to generate a corresponding control signal and send the control signal to the power on/off test circuit 720. And the communication signal of the tested device can be received through the application program, so that whether the tested device is successfully started or closed when receiving a power supply starting instruction or a power supply closing instruction is judged according to the on-off state of the communication signal, and the on-off times of the tested device is counted. And when a plurality of tested devices are connected, the tested devices to be tested can be selected from the upper computer.
In this embodiment of the present invention, after receiving the connection signal, the upper computer 710 further controls the power on/off test circuit 720 to immediately send the power off command.
In this embodiment of the present invention, the upper computer 710 further controls the power on/off test circuit 720 to stop sending the power on instruction and the power off instruction when the connection signal is not received through the power on/off interval. The on-off interval should be not less than the normal on-off time of the device under test, for example, when the normal on-off time of the device under test is 60 seconds, the on-off interval may be set to 80 seconds, so that the device under test can be normally turned on, and the user may adjust the on-off interval and the on-off frequency through the upper computer 710, which is not limited herein. The upper computer 710 may also be connected to the device under test in a network connection manner, so as to obtain a connection signal after the device under test is turned on, which is not limited herein.
In the embodiment of the present invention, the upper computer includes a memory and a processor, the memory may be used to store a computer program, and the processor runs the computer program. The memory may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the upper computer, and the like. Further, the memory may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
The embodiment also provides a computer storage medium for storing the computer program used in the upper computer.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention or a part of the technical solution that contributes to the prior art in essence can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. The startup and shutdown test circuit is characterized by comprising a signal conversion circuit, a control circuit connected with the signal conversion circuit, and at least one test interface connected with the control circuit;
the signal conversion circuit is used for connecting an upper computer, receiving a control signal sent by the upper computer and converting the control signal into a preset logic level;
the control circuit is used for receiving the converted control signal and transmitting a power supply opening instruction and a power supply closing instruction to at least one test interface according to the switching times and the switching intervals in the control signal;
the at least one test interface is used for connecting tested equipment, sending the power supply opening instruction and the power supply closing instruction to the tested equipment and transmitting a communication signal after the tested equipment is opened to the upper computer through the signal conversion circuit.
2. The on/off test circuit of claim 1, wherein the signal conversion circuit comprises a logic level conversion chip and an RS232 interface;
a first TTL level output pin of the logic level conversion chip is connected with a second pin of the RS232 interface;
a first RS232 level input pin of the logic level conversion chip is connected with a third pin of the RS232 interface;
a second RS232 level input pin and a second TTL level input pin of the logic level conversion chip are grounded;
and a fifth pin of the RS232 interface is grounded.
3. The on/off test circuit of claim 2, wherein the control circuit comprises a microcontroller;
a first asynchronous receiving and transmitting pin of the microcontroller is connected with a first TTL level input pin of the logic level conversion chip;
and a second asynchronous receiving and transmitting pin of the microcontroller is connected with a first RS232 level output pin of the logic level conversion chip.
4. The on/off test circuit of claim 3, wherein the microcontroller comprises a GD32F205xx series single chip microcomputer.
5. The power on/off test circuit of claim 3, further comprising a clock circuit connected to the control circuit;
the clock circuit is used for providing a clock signal for the control circuit.
6. The power on/off test circuit of claim 5, wherein the clock circuit comprises an active crystal oscillator, a resistor, and a capacitor;
a third pin of the active crystal oscillator is connected to an oscillator pin of the microcontroller through the resistor;
a fourth pin of the active crystal oscillator is connected with a driving power supply and is grounded through a capacitor;
and the second pin of the active crystal oscillator is grounded.
7. An on-off test system, comprising an upper computer and the on-off test circuit of any one of claims 1 to 6.
8. The startup and shutdown test system according to claim 7, wherein the upper computer generates a corresponding control signal to be sent to the startup and shutdown test circuit after receiving the input startup and shutdown times and intervals;
the power on/off test circuit sends a power on instruction and a power off instruction to the tested equipment according to the power on/off times and the power on/off intervals in the control signal, and transmits a communication signal after the tested equipment is turned on to the upper computer;
and the upper computer records the received times of the communication signals as the successful times of the startup and shutdown of the tested equipment.
9. The startup and shutdown test system according to claim 8, wherein the upper computer controls the startup and shutdown test circuit to immediately send the power-off instruction after receiving the connection signal.
10. The startup and shutdown test system according to claim 8, wherein the upper computer controls the startup and shutdown test circuit to stop sending the power-on instruction and the power-off instruction when the connection signal is not received through the startup and shutdown interval.
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| CN202011168379.9A CN111999590A (en) | 2020-10-28 | 2020-10-28 | Startup and shutdown test circuit and startup and shutdown test system |
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| CN202011168379.9A CN111999590A (en) | 2020-10-28 | 2020-10-28 | Startup and shutdown test circuit and startup and shutdown test system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113360332A (en) * | 2021-07-15 | 2021-09-07 | 杭州雾联科技有限公司 | Testing device of power supply control system |
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