CN111988115B - ADS-B distributed processing system based on parallel computing on general platform - Google Patents
ADS-B distributed processing system based on parallel computing on general platform Download PDFInfo
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- H—ELECTRICITY
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Abstract
The invention discloses an ADS-B distributed processing system based on parallel computing on a general platform, which adopts a parallel processing architecture, the hardware basis of the system is general, and the functions and the performance are defined by software, so that the real-time performance of the whole system is greatly ensured; aiming at new application requirements of anti-interference, weak signals and the like, the original algorithm is improved and supplemented, a pulse position judgment method is added in the aspect of decoding for accurately detecting pulses so as to improve decoding precision, a comprehensive error correction method is adopted in the aspect of error correction so as to improve the error correction digit and greatly improve the data utilization rate, and in the aspect of algorithm implementation, a parallel computing mode on a general platform is adopted to carry out full software processing on data. The invention can greatly improve the flexibility, reliability and expandability of the system.
Description
Technical Field
The invention relates to the technical field of communication, in particular to an ADS-B distributed processing system based on parallel computing on a general platform.
Background
The ADS-B (Automatic Dependent Surveillance-Broadcast) system obtains air traffic situation information such as the position (longitude and latitude, altitude and the like), the speed, the working state and the like of the airplane through a Global Navigation Satellite System (GNSS), an Inertial Navigation System (INS), an Inertial Reference System (IRS) and other airborne sensors, and forms an ADS-B information frame together with the identity and category information of the airplane according to a fixed format, and then broadcasts through an airborne ADS-B transmitting device at a certain speed.
Since each aircraft transmits broadcasts to the ground independently, this creates the possibility of interleaving two or even more pieces of information; in addition, in recent years, the rapid increase of airspace flow makes the interleaving probability larger and larger, which leads the receiver to be unable to solve correct airplane information, thereby seriously affecting the performance of the whole system, and according to statistics, after the air ADS-B signal passing through the preprocessing process of header detection and the like is decoded by the receiver, all bits are high confidence level, and the verified message only accounts for about 30%. In addition, new technologies such as satellite-based ADS-B have been proposed to solve the problem of aircraft surveillance in oceans, deserts, and other special areas, which puts higher and more demands on the ADS-B system. Firstly, in terms of a processing method, aiming at the situations of interweaving, satellite-based ADS-B weak signals and the like, supplementary measures aiming at the situations need to be provided on the original algorithm; secondly, in terms of processing mode, in order to meet future application requirements, each process of signal and information processing gradually develops to software processing, and the functions and performance of the whole system need to have the characteristics of reconfigurability, expandability, multiple functions and multiple modes.
In the face of increasingly complex application requirements and more severe electromagnetic environments, the following disadvantages and shortcomings are gradually highlighted in the traditional ADS-B signal and information processing system:
a) In the aspect of processing mode, the expandability is poor, which is mainly characterized in that a hardware technology is taken as a core, software is customized along with hardware, the software and the hardware are tightly coupled, functions and performances are solidified after the system is developed, the expandability is poor, the use is not flexible, the algorithm and the functions are difficult to upgrade in the future, and a new hardware module is required to be added every time a new function is added;
b) In the aspect of processing methods, for the situations of interleaving, satellite-based ADS-B weak signals and the like, supplementary measures for the situations need to be provided on the original algorithm, and the processing processes of decoding, error correction and the like need to be supplemented and improved on the basis of digitization and software so as to improve the performance of the whole system.
Disclosure of Invention
The invention aims to provide an ADS-B distributed processing system based on parallel computing on a general platform, which can greatly improve the flexibility, reliability and expandability of the system.
In order to solve the technical problems, the invention adopts the technical scheme that: the ADS-B distributed processing system based on parallel computing on a general platform is provided and comprises a plurality of computers, wherein one computer is used as a control machine, and other computers are connected with the control machine;
the controller is used for receiving the intermediate frequency signal, selecting a computer as a target computer, and sending the intermediate frequency signal to the target computer, wherein the intermediate frequency signal is obtained by processing an ADS-B signal in the air by a receiver;
the sampling unit of the target computer is used for sampling the intermediate frequency signal to obtain an intermediate frequency sampling signal;
the baseband extraction unit is used for extracting a baseband signal from the intermediate frequency sampling signal;
the pulse analysis unit is used for determining the effective pulse position and the leading edge sampling point of the current target in the baseband signal;
the header detection unit is used for detecting 4 header pulses of a current target according to the effective pulse position and the leading edge sampling point;
the power calculation unit is used for extracting 2 sampling points after the rising edge corresponding to the 4 header pulses to obtain 8 sampling points, and taking the maximum value of the 8 sampling points as a re-triggering reference value and the minimum value as a reference power value;
the DF authentication unit is used for judging whether the difference value between the sampling point of the first 5 bit data after the rising edge corresponding to the 4 header pulses and the reference power value is in a preset range;
the power detection unit is used for calculating the power average value of 4 sampling points after the rising edge corresponding to 4 header pulses when the DF authentication unit judges that the power average value is in a preset range, and judging whether the difference value between the power average value corresponding to more than 1 header pulse and the reference power value is within 3 dB;
the retriggering unit is used for continuously searching a new target within preset time when the judgment result of the power detection unit is yes, replacing the current target with the new target and discarding the original target when the new target is searched and the retriggering reference value of the new target exceeds the retriggering reference value of the current target by 3 dB;
the code bit detection unit is used for calculating amplitude reference values of 4 header pulses and obtaining an original message of a current target according to the baseband signal, the 4 header pulses and the amplitude reference values;
the error correction unit is used for carrying out conservative error correction or parallel violent error correction on the original message and then sending the original message to the controller.
Preferably, the sampling rate of the sampling unit is 10MHz, the baseband extraction unit is specifically configured to write the I and Q signals in the intermediate frequency sampling signal into an array I (t) and an array Q (t), respectively, perform square summation on the array I (t) and the array Q (t), and then perform an open-square parallel operation to obtain a baseband signal AMP (t), where a calculation formula of the baseband signal AMP (t) is:
where t represents a sampling point.
Preferably, the baseband extraction unit is further configured to perform parallel comparison and parallel multiplication on the baseband signal AMP (t) and a preset noise floor threshold S to remove noise of the baseband signal AMP (t), where the calculation formula is:
Amp＝Amp*(Amp＞S)。
preferably, the pulse analysis unit is specifically configured to determine whether a current sampling point of the baseband signal and 3 consecutive sampling points after the current sampling point are greater than a noise floor threshold S, and determine that the current sampling point is an effective pulse position of a current target when the current sampling point is greater than the noise floor threshold S; and when the power of the current sampling point exceeds the previous sampling point by 4.8dB and the difference value of the current sampling point with the next sampling point is within 4.8dB, and the current sampling point is a valid pulse position, judging that the current sampling point is a leading edge sampling point of the current target.
Preferably, the preamble detection unit is specifically configured to determine whether or not the current sampling points at 0us,1us,3.5us, and 4.5us of the baseband signal are valid pulse positions, and whether or not at least two of the current sampling points at 0us,1us,3.5us, and 4.5us are leading edge sampling points, and when the determination result is yes, take the current sampling points at 0us,1us,3.5us, and 4.5us of the baseband signal as the 4 preamble pulses.
Preferably, the preamble detection unit is further configured to, before detecting 4 preamble pulses, divide the baseband signal AMP into 4 paths, delay the 2 nd, 3 rd, and 4 th baseband signals AMP by 1us,3.5us, and 4.5us, respectively, multiply the 4 th baseband signal AMP to obtain an optimized baseband signal AMP, and replace the original baseband signal AMP with the optimized baseband signal AMP, where the calculation process of the optimized baseband signal AMP is as follows:
AMP＝AMP1×AMP2×AMP3×AMP4＝A 4 +n 0
AMP1＝A+n 1
AMP2＝A+n 2
AMP3＝A+n 3
AMP4＝A+n 4
wherein AMP1 represents a 1 st base band signal AMP, AMP2 represents a 2 nd base band signal AMP, AMP3 represents a 3 rd base band signal AMP, AMP4 represents a 4 th base band signal AMP, A represents amplitude, n 1 、n 2 、n 3 、n 4 Noise, n, representing 4-baseband signals AMP 0 Representing noise that optimizes the base-band signal AMP.
Preferably, the code bit detection unit is specifically configured to extract 3 sampling points around 4 header pulse peaks to obtain 12 sampling points; for the amplitude of each sampling point, calculating the number of points in the range of 2dB of the amplitude in 12 sampling points, and correspondingly storing the number into an array number [ i ], wherein i =1,2,3.. 12; traversing number [ i ] to find out the maximum number _ max; when there is only one maximum value number _ max in the array number [ i ], the amplitude value corresponding to number _ max is taken as the amplitude reference value.
Preferably, the code bit detection unit is further configured to, when there is more than one maximum value number _ max in the array number [ i ], find these amplitude points with the maximum value and form an array max, find the minimum value min in the array max, eliminate amplitude points greater than 2dB of the minimum value min, calculate an average value of remaining sample points and amplitude values in the array max, and use the average value as the amplitude reference value.
Preferably, the error correction unit is specifically configured to perform conservative error correction on the original packet when the error code bits of the original packet occur to the code bits with low confidence and the code bits with low confidence are within 24 bits continuously.
Preferably, the process of performing parallel brute force error correction by the error correction unit is as follows:
judging the number of the code bits with low confidence, if the number of the code bits exceeds the maximum parallel thread number of the computer, abandoning the message, otherwise, allocating threads, wherein 2n threads are allocated to the code bits with low confidence of n bits;
brute force error correction is performed on each thread.
Different from the prior art, the invention has the beneficial effects that: by adopting a parallel processing architecture, the hardware basis of the system is universal, and the function and the performance are defined by software, so that the real-time performance of the whole system is greatly ensured; aiming at new application requirements of anti-interference, weak signals and the like, the original algorithm is improved and supplemented, a pulse position judgment method is added in the aspect of decoding for accurately detecting pulses so as to improve decoding precision, a comprehensive error correction method is adopted in the aspect of error correction so as to improve the error correction digit and greatly improve the data utilization rate, and in the aspect of algorithm implementation, a parallel computing mode on a general platform is adopted to carry out full software processing on data.
Drawings
FIG. 1 is a schematic diagram of an architecture of an ADS-B distributed processing system based on parallel computing on a general platform according to an embodiment of the present invention;
FIG. 2 is a functional block diagram of a computer of the ADS-B distributed processing system of an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Referring to fig. 1, the ADS-B distributed processing system based on parallel computing on a general platform according to the embodiment of the present invention includes a plurality of computers 10, one of the computers 10 is used as a controller, the other computers 10 are connected to the controller, and all the computers 10 are connected to a high-speed communication network. The computer 10 includes a sampling unit 101, a baseband extraction unit 102, a pulse parsing unit 103, a header detection unit 104, a power calculation unit 105, a DF authentication unit 106, a power detection unit 107, a retriggering unit 108, a code bit detection unit 109, and an error correction unit 110.
The control machine is used for receiving the intermediate frequency signal, selecting one computer 10 as a target computer, and sending the intermediate frequency signal to the target computer, wherein the intermediate frequency signal is obtained by processing an ADS-B signal in the air by a receiver 20. The control unit may select any one of the computers 10 having the smallest CPU utilization as the target computer. It should be noted that the target computer may also comprise the controlling machine itself. The control machine and other computers 10 are provided with communication middleware, the main role of which is communication.
The sampling unit 101 of the target computer is used for sampling the intermediate frequency signal to obtain an intermediate frequency sampling signal; in the present embodiment, the sampling rate of the sampling unit 101 is 10MHz. After sampling, the physical intermediate frequency signal can be converted into data that can be recognized by a computer.
The baseband extraction unit 102 is configured to extract a baseband signal from the intermediate frequency sampling signal;
the pulse analysis unit 103 is configured to determine an effective pulse position and a leading edge sampling point of a current target in the baseband signal;
the header detection unit 104 is used for detecting 4 header pulses of the current target according to the effective pulse position and the leading edge sampling point;
the power calculation unit 105 is configured to extract 2 sampling points after a rising edge corresponding to the 4 header pulses to obtain 8 sampling points, and use a maximum value of the 8 sampling points as a re-trigger reference value and a minimum value as a reference power value;
the DF authenticating unit 106 is configured to determine whether a difference between a sampling point of first 5 bit data after a rising edge corresponding to 4 header pulses and the reference power value is within a predetermined range;
the power detection unit 107 is configured to, when the DF authentication unit 106 determines that the power is within the predetermined range, calculate a power average value of 4 sampling points after a rising edge corresponding to 4 header pulses, and determine whether a difference between the power average value corresponding to 1 or more header pulses and the reference power value is within 3 dB;
the re-triggering unit 108 is configured to, when the determination result of the power detection unit 107 is yes, continue to search for a new target within a preset time, and when the new target is found and the re-triggering reference value of the new target exceeds the re-triggering reference value of the current target by 3dB, replace the current target with the new target and discard the original target;
the code bit detection unit 109 is configured to calculate amplitude reference values of 4 header pulses, and obtain an original packet of a current target according to the baseband signal, the 4 header pulses, and the amplitude reference values;
the error correction unit 110 is configured to perform conservative error correction or parallel violent error correction on the original message, and then send the original message to the controller. After receiving all the original messages sent by the computer 10, the controller collects the original messages and sends the messages to the service terminal 30 for performing route-ending processing.
Specifically, the baseband extraction unit 102 is specifically configured to write the I and Q signals in the intermediate frequency sampling signal into an array I (t) and an array Q (t), respectively, sum the squares of the array I (t) and the array Q (t), and then perform an open-square parallel operation to obtain a baseband signal AMP (t), where a calculation formula of the baseband signal AMP (t) is:
where t represents a sampling point. The baseband signal AMP (t) is an array of baseband signals.
Further, the baseband extraction unit 102 is further configured to perform parallel comparison and parallel multiplication on the baseband signal AMP (t) and a preset noise floor threshold S to remove noise of the baseband signal AMP (t), where the calculation formula is:
Amp＝Amp*(Amp＞S)。
the Amp > S is equivalent to the comparison of corresponding elements of two arrays (array) and returns a new array, the number of elements of the new array is the same as that of the Amp and S, the new array returns 1 at the position of the subscript where ">" holds, and otherwise, the new array returns 0. Then parallel multiplication is performed with Amp and the new array. Subscript refers to an array index, e.g., amp (50) denotes the 50 th element of array Amp, 50 being a subscript.
The pulse analysis unit 103 is specifically configured to determine whether a current sampling point of the baseband signal and subsequent 3 sampling points of the baseband signal are greater than a noise floor threshold S, and determine that the current sampling point is an effective pulse position of a current target when the current sampling point is greater than the noise floor threshold S; and when the power of the current sampling point exceeds the previous sampling point by 4.8dB and the difference value of the current sampling point with the next sampling point is within 4.8dB, and the current sampling point is a valid pulse position, judging that the current sampling point is a leading edge sampling point of the current target.
The preamble detection unit 104 is specifically configured to determine whether the current sampling points at 0us,1us,3.5us, and 4.5us of the baseband signal are valid pulse positions, and whether at least two of the current sampling points at 0us,1us,3.5us, and 4.5us are leading edge sampling points, and when the determination result is yes, take the current sampling points at 0us,1us,3.5us, and 4.5us of the baseband signal as the 4 preamble pulses.
In order to improve the accuracy of preamble detection in the case of low signal-to-noise ratio, in this embodiment, the preamble detection unit 104 is further configured to divide the baseband signal AMP into 4 paths before detecting 4 preamble pulses, delay the 2 nd baseband signal AMP, the 3 rd baseband signal AMP, and the 4 th baseband signal AMP by 1us,3.5us, and 4.5us, respectively, multiply the 4 th baseband signal AMP to obtain an optimized baseband signal AMP, and replace the original baseband signal AMP with the optimized baseband signal AMP, where a calculation process of the optimized baseband signal AMP is as follows:
AMP＝AMP1×AMP2×AMP3×AMP4＝A 4 +n 0
AMP1＝A+n 1
AMP2＝A+n 2
AMP3＝A+n 3
AMP4＝A+n 4
wherein AMP1 represents a 1 st base band signal AMP, AMP2 represents a 2 nd base band signal AMP, AMP3 represents a 3 rd base band signal AMP, AMP4 represents a 4 th base band signal AMP, A represents amplitude, n 1 、n 2 、n 3 、n 4 Representing noise of 4-baseband signal AMP, n 0 Representing the noise of the optimized baseband signal AMP. Since n is 0 An additional term due to impulse noise after multiplication is added, because the larger a is, the higher the signal-to-noise ratio is.
The code bit detection unit 109 is specifically configured to extract 3 sampling points around 4 header pulse peaks to obtain 12 sampling points; for the amplitude of each sampling point, calculating the number of points falling within the range of 2dB of the amplitude in 12 sampling points, and correspondingly storing the points into an array number [ i ], wherein i =1,2,3.. 12; traversing number [ i ] to find out the maximum number _ max; when only one maximum value number _ max in the array number [ i ], the amplitude value corresponding to the number _ max is taken as the amplitude reference value. Further, the code bit detection unit 109 is further configured to, when there is more than one maximum value number _ max in the array number [ i ], find these amplitude points with the maximum value and form an array max, find the minimum value min in the array max, eliminate amplitude points greater than 2dB of the minimum value min, calculate an average value of remaining sample points and amplitude values in the array max, and use the average value as an amplitude reference value.
After the amplitude reference value is determined, the original message of the current target needs to be demodulated. Demodulation of a data bit requires at the same time that the confidence level of each bit, i.e. the pulse following the header pulse, is scaled. Specifically, taking a 10MHz sampling rate as an example, for one bit (chip), 10 points of the bit are divided into two types:
a: points within +/-3dB of the reference amplitude;
b: less than the reference amplitude-6 dB.
The number of samples (weighted) that fall within both decision ranges (type a, B) is then calculated. The principle to be followed is that the weights of the 1 st, 5 th, 6 th and 10 th sampling points are small, and the weights of the other sampling points are large. Then 4 counters are defined to store the number of two types of patterns in the 1/0 part of a chip:
1ChipTypeA is the number of A type samples in the first half of the pulse
1ChipTypeB is the number of B-type samples in the first half of the pulse
0ChipTypeA is the number of A type samples in the second half of the pulse
0ChipTypeB is the number of B-type samples in the second half of the pulse
Then, the bit chip indicates 1 or 0, and the 4 counters obtained above are used to calculate the following formula:
1Score＝1ChipTypeA-0ChipTypeA+0ChipTypeB-1ChipTypeB
0Score＝0ChipTypeA-1ChipTypeA+1ChipTypeB-0ChipTypeB
after the calculation is finished, the bit is judged to be 1 or 0 according to the score, and then the score difference threshold value of 1 score and 0 is set to judge the confidence.
The error correction unit 110 is specifically configured to perform conservative error correction on the original packet when the error code bits of the original packet occur to the code bits with low confidence and the code bits with low confidence are within 24 consecutive bits. Further, the process of performing parallel brute force error correction is as follows:
judging the number of the code bits with low confidence, if the number of the code bits exceeds the maximum parallel thread number of the computer, abandoning the message, otherwise, allocating threads, wherein 2n threads are allocated to the code bits with low confidence of n bits;
error correction is done at each thread.
The principle of conservative error correction is as follows:
according to the CRC checking theory, a generator polynomial is
G(x)＝x 24 +x 23 +x 22 +x 21 +x 20 +x 19 +x 18 +x 17 +x 16 +x 15 +x 14 +x 13 +x 12 +x 10 +x 3 +1
Assuming that the information to be sent is S (x), the last 24 bits (PI field) of the message are determined by the following equation
x r S(x)＝Q(x)G(x)+R(x)
R (x) determines the last 24 positions.
And after receiving the message M (x), performing CRC (cyclic redundancy check) on the message M (x), if the check remainder r (x) is 0, passing the check, otherwise, having an error code and needing error correction.
For the case where r (x) is not 0, i.e., M (x)% G (x) ≠ 0, we derive the relationship of r (x) to r '(x) assuming that the remainder of left-shifting M (x) by one bit is r' (x). The remainder of actually rotating M (x) one bit to the left is the remainder of x r (x), i.e., rotating r (x) one bit to the left. Then the following relationship holds:
x*r(x)＝q(x)G(x)+r’(x)
since r (x) is 23 at most to the highest power and r' (x) is 23 at most to the highest power, q (x) is 0 or 1. It is easy to see that q (x) =1 when the highest power of r (x) is 23, and q (x) is 0 when the highest power of r (x) is less than 23. That is to say that the first and second electrodes,
it can be seen from the above derivation that, M (x) can be obtained from the initial remainder r (x) by circularly shifting left by one bit, and then, the remainders shifted left by two, three, and four bits can be obtained, so that all the code bits with low confidence coefficient are shifted left to the last 24 bits of the message, and then, the remainder at this time is the error code bit, and the correct code bit can be obtained only by flipping the remainder, thereby completing error correction.
When the condition of conservative error correction is not met, namely when the error code bits of the original message do not all occur on the code bits with low confidence coefficient, or the code bits with low confidence coefficient are not within 24 continuous bits, parallel violent error correction is required.
Through the mode, the ADS-B distributed processing system based on parallel computing on the general platform has the following effects:
a) Reliability and performance enhancement
The hardware computer cluster (control machine and other computers) of the system is formed, all processing after the receiver 20 is completed by computer software, the system equipment amount is greatly reduced, and the system has higher reliability obviously from hardware reliable model analysis; on the other hand, for the reliability of the software, the software is constructed by utilizing a mature integrated parallel computing processing software library, the reliability of the software can be continuously improved along with the accumulation of the running time and the iterative upgrade of the version of the software through the full software evaluation of the system, and the signal processing based on the software can adopt a parallel cluster working mode, so that the system can be maintained without shutdown and upgraded without shutdown; in the aspects of algorithm and implementation, a new algorithm module and an implementation method are added in the aspects of detection and error correction to improve the performance of the system.
b) Improvement of economical efficiency
The hardware system mode formed by communication middleware and computers replaces a special hardware module in the traditional scheme, the occupation ratio of special equipment is reduced, the occupation ratio of general equipment and commercial equipment is improved, the software multiplexing cost is low, and the system construction and use cost is low.
c) The functions and performances have openness
The system based on the technology has an open architecture, is decoupled from software and hardware, has functions defined by software, and is reconfigurable, flexible and expandable; the performance is open, and the scale of information processing software and hardware is configured according to application requirements.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, and various media capable of storing program codes.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
Claims (8)
1. An ADS-B distributed processing system based on parallel computing on a general platform is characterized by comprising a plurality of computers, wherein one computer is used as a control machine, and other computers are connected with the control machine, and each computer comprises a sampling unit, a baseband extraction unit, a pulse analysis unit, a header detection unit, a power calculation unit, a DF authentication unit, a power detection unit, a re-triggering unit, a code bit detection unit and an error correction unit;
the controller is used for receiving the intermediate frequency signal, selecting a computer as a target computer, and sending the intermediate frequency signal to the target computer, wherein the intermediate frequency signal is obtained by processing an ADS-B signal in the air by a receiver;
the sampling unit of the target computer is used for sampling the intermediate frequency signal to obtain an intermediate frequency sampling signal;
the baseband extraction unit is used for extracting a baseband signal from the intermediate frequency sampling signal;
the pulse analysis unit is used for determining the effective pulse position and the leading edge sampling point of the current target in the baseband signal;
the header detection unit is used for detecting 4 header pulses of a current target according to the effective pulse position and the leading edge sampling point;
the header detection unit is specifically used for judging whether current sampling points at 0us,1us,3.5us and 4.5us of the baseband signal are effective pulse positions or not, and whether at least two of the current sampling points at 0us,1us,3.5us and 4.5us are front edge sampling points or not, and when the judgment result is yes, taking the current sampling points at 0us,1us,3.5us and 4.5us of the baseband signal as 4 header pulses;
the preamble detection unit is further configured to divide the baseband signal AMP into 4 paths before detecting 4 preamble pulses, delay the 2 nd, 3 rd, and 4 th baseband signals AMP by 1us,3.5us, and 4.5us, respectively, multiply the 4 th baseband signal AMP to obtain an optimized baseband signal AMP, and replace the original baseband signal AMP with the optimized baseband signal AMP, where the calculation process of the optimized baseband signal AMP is as follows:
Amp＝Amp1×Amp2×Amp3×Amp4＝A 4 +n 0
Amp1＝A+n 1
Amp2＝A+n 2
Amp3＝A+n 3
Amp4＝A+n 4
wherein AMP1 represents a 1 st base band signal AMP, AMP2 represents a 2 nd base band signal AMP, AMP3 represents a 3 rd base band signal AMP, AMP4 represents a 4 th base band signal AMP, A represents amplitude, n 1 、n 2 、n 3 、n 4 Noise, n, representing 4-baseband signals AMP 5 Noise representing an optimized baseband signal AMP;
the power calculation unit is used for extracting 2 sampling points after the rising edge corresponding to the 4 header pulses to obtain 8 sampling points, and taking the maximum value of the 8 sampling points as a re-triggering reference value and the minimum value as a reference power value;
the DF authentication unit is used for judging whether the difference value between the sampling point of the first 5 bit data after the rising edge corresponding to the 4 header pulses and the reference power value is in a preset range;
the power detection unit is used for calculating the power average value of 4 sampling points after the rising edge corresponding to 4 header pulses when the DF authentication unit judges that the power average value is in a preset range, and judging whether the difference value between the power average value corresponding to more than 1 header pulse and the reference power value is within 3 dB;
the re-triggering unit is used for continuously searching a new target within a preset time when the judgment result of the power detection unit is yes, replacing the current target with the new target and abandoning the original target when the new target is found and the re-triggering reference value of the new target exceeds the re-triggering reference value of the current target by 3 dB;
the code bit detection unit is used for calculating amplitude reference values of 4 header pulses and obtaining an original message of a current target according to the baseband signal, the 4 header pulses and the amplitude reference values;
the error correction unit is used for carrying out conservative error correction or parallel violent error correction on the original message and then sending the original message to the control machine.
2. The ADS-B distributed processing system according to claim 1, wherein a sampling rate of the sampling unit is 10MHz, the baseband extraction unit is specifically configured to write the I and Q signals in the intermediate frequency sampling signal into an array I (t) and an array Q (t), respectively, perform square summation on the array I (t) and the array Q (t), and then perform an open-square parallel operation to obtain a baseband signal AMP (t), where a calculation formula of the baseband signal AMP (t) is:
where t represents a sampling point.
3. The ADS-B distributed processing system according to claim 2, wherein the baseband extraction unit is further configured to perform parallel comparison and parallel multiplication on the baseband signal AMP (t) and a preset noise floor threshold S to remove noise of the baseband signal AMP (t), and the calculation formula is as follows:
Amp＝Amp*(Amp>S)。
4. the ADS-B distributed processing system according to claim 3, wherein the pulse parsing unit is specifically configured to determine whether a current sampling point of the baseband signal and subsequent consecutive 3 sampling points are greater than a noise floor threshold S, and determine that the current sampling point is an effective pulse position of a current target when the current sampling point is greater than the noise floor threshold S; and when the power of the current sampling point exceeds 4.8dB of the previous sampling point, the difference value of the current sampling point and the next sampling point is within 4.8dB, and the current sampling point is the effective pulse position, judging that the current sampling point is the leading edge sampling point of the current target.
5. The ADS-B distributed processing system according to claim 1, wherein the code bit detection unit is specifically configured to extract 3 sampling points around 4 header pulse peaks to obtain 12 sampling points; for the amplitude of each sampling point, calculating the number of points falling within the range of 2dB of the amplitude in 12 sampling points, and correspondingly storing the points into an array number [ i ], wherein i =1,2,3.. 12; traversing number [ i ] to find out the maximum number _ max; when only one maximum value number _ max in the array number [ i ], the amplitude value corresponding to the number _ max is taken as the amplitude reference value.
6. The ADS-B distributed processing system according to claim 5, wherein the code bit detecting unit is further configured to, when there is more than one maximum value number _ max in the array number [ i ], find the amplitude points having the maximum values and compose an array max, find the minimum value min in the array max, cull amplitude points that are greater than the minimum value min by 2dB, and calculate an average value of remaining sample points and amplitude values in the array max, taking the average value as the amplitude reference value.
7. The ADS-B distributed processing system according to claim 6, wherein the error correction unit is specifically configured to perform conservative error correction on the original packet when the error code bits of the original packet occur on the code bits with low confidence and the code bits with low confidence are within 24 consecutive bits.
8. The ADS-B distributed processing system of claim 7, wherein the error correction unit performs concurrent brute force error correction by:
judging the number of the code bits with low confidence, if the number of the code bits exceeds the maximum parallel thread number of the computer, abandoning the message, otherwise, allocating threads, wherein 2n threads are allocated to the code bits with low confidence of n bits;
brute force error correction is performed on each thread.
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