CN111987100A - Semiconductor structure, manufacturing method thereof and memory - Google Patents
Semiconductor structure, manufacturing method thereof and memory Download PDFInfo
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- CN111987100A CN111987100A CN201910434483.9A CN201910434483A CN111987100A CN 111987100 A CN111987100 A CN 111987100A CN 201910434483 A CN201910434483 A CN 201910434483A CN 111987100 A CN111987100 A CN 111987100A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000003990 capacitor Substances 0.000 claims abstract description 228
- 239000000758 substrate Substances 0.000 claims abstract description 96
- 238000000034 method Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 252
- 230000009286 beneficial effect Effects 0.000 description 13
- 230000008569 process Effects 0.000 description 13
- 238000002955 isolation Methods 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- -1 HfO2 Chemical compound 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
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- Semiconductor Integrated Circuits (AREA)
Abstract
The embodiment of the invention relates to a semiconductor structure, a manufacturing method thereof and a memory, wherein the semiconductor structure comprises: the semiconductor device comprises a substrate, a grid structure, a first source drain doped region and a second source drain doped region; the anti-fuse capacitor is positioned in the substrate, the first source-drain doped region is used as an electrode plate of the anti-fuse capacitor, and the anti-fuse capacitor further comprises: the capacitor comprises a capacitor dielectric layer positioned on the surface of the side wall of the first source-drain doped region and a capacitor conducting layer positioned on the surface of the capacitor dielectric layer. In the embodiment of the invention, the anti-fuse capacitor is arranged in the substrate, and the source electrode or the drain electrode in the control gate transistor is used as the lower electrode plate of the anti-fuse capacitor, so that the semiconductor structure with a brand-new structure is provided.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a manufacturing method of the semiconductor structure and a memory.
Background
In the semiconductor industry, fuse elements are widely used in integrated circuits due to their multiple uses. For example, a plurality of circuit blocks having the same function are designed in an integrated circuit as backups, and when one of the circuit blocks is found to be defective, the circuit block and other functional circuits in the integrated circuit are blown by fuse elements, while the defective circuit block is replaced with another circuit block having the same function.
Anti-fuse (Anti-fuse) technology has the characteristics of small area, low cost and compatibility with semiconductor processes. An antifuse structure is a structure that can change conductive states, and is non-conductive when inactive and conductive when active. The working principle of the antifuse structure is to store data 1 or 0 according to whether the capacitor dielectric layer is broken down, so that the antifuse structure can selectively electrically connect two originally electrically isolated devices or chips.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for manufacturing the same, and provide a semiconductor structure with a novel structure, which is beneficial to reducing the space occupied by an antifuse capacitor while forming an antifuse structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the gate structure is positioned on the surface of the substrate; the first source-drain doped region is positioned in the substrate on one side of the grid structure, and the doping type of the first source-drain doped region is N-type doping or P-type doping; the second source-drain doped region and the first source-drain doped region are respectively positioned at two opposite sides of the grid structure, and the doping type of the second source-drain doped region is the same as that of the first source-drain doped region; the anti-fuse capacitor is positioned in the substrate, the first source-drain doped region is used as an electrode plate of the anti-fuse capacitor, and the anti-fuse capacitor further comprises: the capacitor comprises a capacitor dielectric layer positioned on the surface of the side wall of the first source-drain doped region and a capacitor conducting layer positioned on the surface of the capacitor dielectric layer.
The embodiment of the invention also provides a memory, which comprises the semiconductor structure.
The embodiment of the invention also provides a manufacturing method of the semiconductor structure, which comprises the following steps: providing a substrate; forming a gate structure on the surface of the substrate, wherein a first source-drain doped region is formed in the substrate on one side of the gate structure, the doping type of the first source-drain doped region is N-type doping or P-type doping, a second source-drain doped region is formed in the substrate on the other side of the gate structure, the second source-drain doped region and the first source-drain doped region are respectively positioned on two opposite sides of the gate structure, and the doping type of the second source-drain doped region is the same as that of the first source-drain doped region; forming a groove in the substrate with partial thickness, wherein the substrate exposes the top of the groove; forming a capacitance dielectric layer on the side wall of the groove; forming a capacitor conducting layer filling the groove on the surface of the capacitor dielectric layer; and the capacitance dielectric layer covers the side wall of the first source-drain doped region.
Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:
the embodiment of the invention provides a semiconductor structure with excellent structural performance, wherein a gate structure, a first source-drain doped region and a second source-drain doped region form a control transistor, an anti-fuse capacitor is positioned in a substrate, and a capacitor conducting layer, a capacitor dielectric layer and the first source-drain doped region form the anti-fuse capacitor, namely the first source-drain doped region is used as a source electrode or a drain electrode of the control transistor and also used as a lower electrode plate of the anti-fuse capacitor. The semiconductor structure provided by the embodiment of the invention is beneficial to reducing the space position occupied by the anti-fuse capacitor, thereby reducing the volume of the semiconductor structure.
In addition, the capacitance medium layer is positioned at the bottom of the groove and on the surface of the whole side wall; and the cross section of the groove is U-shaped in the direction vertical to the surface of the substrate. Therefore, a sharp corner area in the groove can be avoided, and the problem of point discharge is avoided; and when the capacitor dielectric layer needs to be punctured, the capacitor dielectric layer area with the puncturing area being centrally located between the first source-drain doped area and the capacitor conducting layer is guaranteed, and the puncturing efficiency is improved.
In addition, the material of the capacitor dielectric layer is the same as that of the gate dielectric layer, and the thickness of the capacitor dielectric layer is smaller than or equal to that of the gate dielectric layer, so that the situation that the gate dielectric layer is not broken down before the capacitor dielectric layer is broken down is favorably ensured, and the performance of the semiconductor structure is further improved.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 to 4 are schematic cross-sectional views of four exemplary semiconductor structures provided in an embodiment of the present invention;
Fig. 5 to 8 are schematic cross-sectional views corresponding to steps of a method for manufacturing a semiconductor structure according to an embodiment of the invention;
fig. 9 to 12 are schematic cross-sectional views corresponding to steps of a method for manufacturing a semiconductor structure according to another embodiment of the invention.
Detailed Description
The embodiment of the invention provides a semiconductor structure, wherein an anti-fuse capacitor is designed to be positioned in a substrate, and the space occupied by the anti-fuse capacitor is reduced while the storage function is ensured.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
Fig. 1 to 4 are schematic cross-sectional structures of four examples of a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 1, the present embodiment provides a semiconductor structure including: a substrate 100 and a gate structure 102 located on a surface of the substrate 100; a first source-drain doped region 103 located in the substrate 100 at one side of the gate structure 102, wherein the doping type of the first source-drain doped region 103 is N-type doping or P-type doping; a second source-drain doped region 113 located in the substrate 100 on the other side of the gate structure 103, wherein the second source-drain doped region 113 and the first source-drain doped region 103 are respectively located on two opposite sides of the gate structure 102, and the doping type of the second source-drain doped region 113 is the same as that of the first source-drain doped region 103; the antifuse capacitor located in the substrate 100, the first source-drain doped region 103 serving as an electrode plate of the antifuse capacitor, the antifuse capacitor further includes: a capacitor dielectric layer 105 located on the sidewall surface of the first source-drain doped region 103, and a capacitor conductive layer 106 located on the surface of the capacitor dielectric layer 105.
The present embodiment provides a semiconductor structure with a novel structure, which can be applied to a memory circuit. The semiconductor structure includes an antifuse structure having a control transistor and an antifuse capacitor located in a substrate 200, and the antifuse capacitor is located in a substrate 100. Specifically, the gate structure 102, the first source-drain doped region 103 and the second source-drain doped region 113 form a control transistor, the capacitor conductive layer 106, the capacitor dielectric layer 105 and the first source-drain doped region 103 form an antifuse capacitor, and the control transistor controls on and off of the antifuse capacitor. Since the antifuse capacitor is located within the substrate 100, it is advantageous to reduce the spatial location occupied by the antifuse capacitor.
The semiconductor structure provided by the embodiment of the invention will be described in detail with reference to the accompanying drawings.
The substrate 100 may be a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon carbide substrate, a III-V substrate, or a sapphire substrate, and the substrate 100 may also be a silicon-on-insulator substrate.
When the semiconductor structure is used in a memory circuit, the gate structure 102 is used to electrically connect to a word line WL (word line), and a control voltage is applied to the gate structure 102 through the word line WL. The gate structure 102 includes a gate dielectric layer 112 and a gate conductive layer 122 on a top surface of the gate dielectric layer 112.
The material of the gate dielectric layer 112 includes one or more of a high-k dielectric material, silicon oxide, silicon nitride or silicon oxynitride, wherein the high-k dielectric material refers to a material having a relative dielectric constant greater than that of silicon oxide, such as HfO2、Al2O3And the like. The gate dielectric layer 112 may be a single-layer structure or a stacked structure; the number of layers of the gate dielectric layer 112 can be set according to the difference of the manufacturing process and the requirement of the thickness of the gate dielectric layer 112.
The material of the gate conductive layer 122 includes polysilicon, copper, aluminum, or tungsten.
In this embodiment, the gate dielectric layer 112 is made of silicon oxide, and the gate conductive layer 122 is made of polysilicon.
The first source drain doped region 103 and the second source drain doped region 113 are used to serve as a source and a drain of a transistor. Specifically, when the first source-drain doped region 103 serves as a source, the second source-drain doped region 113 serves as a drain; when the first source-drain doped region 103 serves as a drain, the second source-drain doped region 113 serves as a source.
In this embodiment, the doping type of the first source-drain doping region 103 is N-type doping, the doping type of the second source-drain doping region 113 is N-type doping, and the doping ion concentrations of the first source-drain doping region 103 and the second source-drain doping region 113 are the same. The N-type doped dopant ions include P, As or Sb. When the semiconductor structure is used in a memory circuit, the second source-drain doped region 113 is electrically connected to a bit line bl (bit line) for applying a voltage to the second source-drain doped region 113.
It should be noted that, in other embodiments, the first source-drain doped region and the second source-drain doped region may also be formed by using an embedded stress technique, that is, the first source-drain doped region and the second source-drain doped region have stress layers. Specifically, the process for forming the first source-drain doped region and the second source-drain doped region comprises the following steps: removing the substrate with partial thickness at two sides of the gate structure to form a groove; forming a stress layer filling the groove; and doping the stress layer to correspondingly form a first source-drain doping region and a second source-drain doping region, wherein the doping treatment can be in-situ doping (in-situ doping) in the process step of forming the stress layer or doping after forming the stress layer. When the control transistor is a PMOS transistor, the stress layer material comprises SiGe; when the control transistor is an NMOS transistor, the material of the stress layer includes SiC.
The semiconductor structure may further include: an isolation structure 101 located within the substrate 100, adjacent isolation structures 101 for electrically isolating adjacent Active Areas (AA). In this embodiment, the transistor and the antifuse capacitor are both located between adjacent isolation structures 101. The semiconductor structure may further include: and a Well region (Well) located in the substrate 100 between the adjacent isolation structures 101, wherein the doping type of the Well region is N-type doping or P-type doping, and the doping type of the Well region is different from the doping types of the first source-drain doping region and the second source-drain doping region.
In this embodiment, the substrate 100 has a trench 104 therein, the trench 104 exposes the sidewall of the first source-drain doped region 103, correspondingly, the capacitor dielectric layer 103 covers the exposed sidewall of the first source-drain doped region 103 of the trench 104, and the capacitor conductive layer 106 fills the trench 104.
The trench 104 is located between the first source-drain doped region 103 and the isolation structure 101. The trench 104 exposes the sidewall of the first source-drain doped region 103, so as to ensure that the capacitor dielectric layer 105 located on the sidewall of the trench 104 is in contact with the sidewall of the first source-drain doped region 103, and therefore, the first source-drain doped region 103 can be used as a lower electrode plate of the antifuse capacitor, the capacitor conductive layer 106 is used as an upper electrode plate of the antifuse capacitor, and the capacitor dielectric layer 105 is used as a middle dielectric layer of the antifuse capacitor.
In this embodiment, the capacitor dielectric layer 105 is located on the bottom surface of the trench 104 and the sidewall surface of the trench 104 away from the first source-drain doped region 103, in addition to the sidewall surface of the trench 104 close to the first source-drain doped region 103, that is, the capacitor dielectric layer 105 is located on the bottom and the entire sidewall of the trench 104.
During the working period of the semiconductor structure, when the capacitor dielectric layer 105 is broken down, the anti-fuse capacitor is in a conducting state, and data 1 can be stored; when the capacitor dielectric layer 105 is not broken down, the anti-fuse capacitor is in a non-conductive state, and data 0 can be stored. It can also be arranged that: data 0 is stored when the antifuse capacitor is in a conductive state, and data 1 is stored when the antifuse capacitor is in a non-conductive state.
When the capacitor dielectric layer 105 is located at the bottom and the entire sidewall surface of the trench 104, in order to ensure that the region where the capacitor dielectric layer 105 is broken down occurs between the capacitor conductive layer 106 and the first source-drain doped region 103 as much as possible, and improve the breakdown efficiency of the antifuse capacitor, in the embodiment, the cross-sectional shape of the trench 104 is U-shaped in a direction perpendicular to the surface of the substrate 100.
It should be noted that the cross-sectional shape of the trench 104 is U-shaped, which is beneficial to avoid having a sharp corner region in the capacitor dielectric layer 105, and is beneficial to avoid the problem of tip discharge generated in the sharp corner region while avoiding breakdown in the sharp corner region.
In this embodiment, the capacitor dielectric layer 105 is located at the bottom and on the entire sidewall surface of the trench 104, which is also beneficial to ensure the electrical insulation between the capacitor conductive layer 106 and the well region, and avoid the occurrence of unnecessary electrical connection between the capacitor conductive layer 106 and the well region.
It should be noted that, in other embodiments, when adverse effects caused by the electrical connection between the capacitor conductive layer and the well region are negligible, the capacitor dielectric layer may only cover the surface of the sidewall of the first source/drain doped region exposed by the trench, or the capacitor dielectric layer may cover the bottom of the trench or the sidewall of the rest of the trench except the surface of the sidewall of the first source/drain doped region exposed by the trench.
It should be noted that, in other embodiments, when the influence caused by the point discharge problem is negligible, the cross-sectional shape of the trench in the direction perpendicular to the substrate surface may also be square or trapezoidal; or, when the capacitor dielectric layer only covers the sidewall surface of the first source-drain doped region exposed by the trench, the cross-sectional shape of the trench may also be square or trapezoidal in the direction perpendicular to the substrate surface.
In this embodiment, as shown in fig. 1, in a direction perpendicular to the surface of the substrate 100, the capacitor dielectric layer 105 covers the entire sidewall surface of the first source-drain doped region 103, that is, in a direction perpendicular to the surface of the substrate 100, the length of the sidewall of the first source-drain doped region 103 covered by the capacitor dielectric layer 105 is equal to the length of the sidewall of the first source-drain doped region 103. In other embodiments, as shown in fig. 2, in a direction perpendicular to the surface of the substrate 100, the capacitor dielectric layer 105 may also cover a portion of the sidewall surface of the first source-drain doped region 103, that is, in a direction perpendicular to the surface of the substrate 100, the length of the sidewall of the first source-drain doped region 103 covered by the capacitor dielectric layer 105 is less than the length of the sidewall of the first source-drain doped region 103.
The contact area between the capacitor dielectric layer 105 and the first source-drain doped region 103 is related to the capacitance of the antifuse capacitor. On the premise that other factors influencing the capacitance value are not changed, the larger the contact area is, the larger the capacitance value of the antifuse capacitor is, and therefore the size of the contact area between the capacitor dielectric layer 105 and the first source drain doped region 103 can be set reasonably based on different requirements for the capacitance value of the antifuse capacitor. Since the first source-drain doped region 103 also serves as a source or a drain of the transistor, if the contact area is too large, the normal operation of the transistor may be affected during the operation of the antifuse capacitor.
Moreover, the contact area is related to the junction depth (junction) of the first source/drain doped region 103, and the larger the junction depth is, the larger the corresponding contact area can be set. In this embodiment, the junction depth of the first source-drain doped region 103 is 20nm to 30nm, for example, 24nm, 26nm, and 28 nm.
It is understood that, for the trench 104, as shown in fig. 1, the bottom of the trench 104 may be higher than, or, as shown in fig. 2, the bottom of the trench 104 may be lower than the bottom of the first source/drain doped region 103, or, as shown in fig. 3, the bottom of the trench 104 may be flush with the bottom of the first source/drain doped region 103.
Referring to fig. 1 and 4, the width of the trench 104 in the direction parallel to the surface of the substrate 100 can be flexibly adjusted. For example, when the thickness of the capacitor dielectric layer 105 needs to be set thicker, the width of the corresponding trench 104 is set wider, which is convenient to improve the formation quality of the capacitor dielectric layer 105 and improve the filling effect of the capacitor conductive layer 106; accordingly, when the thickness of the capacitor dielectric layer 105 is relatively thin, the width of the trench 104 can be set relatively narrow.
The material of the capacitor dielectric layer 105 includes one or more of a high-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride. The material of the capacitor dielectric layer 105 may be the same as the material of the gate dielectric layer 112, and the material of the capacitor dielectric layer 105 may be different from the material of the gate dielectric layer 112. In this embodiment, the material of the capacitor dielectric layer 105 is the same as the material of the gate dielectric layer 112, and is silicon oxide.
The material of capacitor dielectric layer 105 is the same as the material of gate dielectric layer 112, and the thickness of capacitor dielectric layer 105 is less than or equal to the thickness of gate dielectric layer 112. Thus, it is effectively ensured that gate dielectric layer 112 is not broken down before capacitor dielectric layer 105 is not broken down, and thus gate structure 105 can provide effective voltage to the antifuse capacitor, so that the antifuse capacitor can be effectively broken down; if the thickness of the capacitor dielectric layer is greater than that of the gate dielectric layer, the gate dielectric layer is already broken down when the capacitor dielectric layer is not broken down, which may affect the breakdown effect of the antifuse capacitor.
It is understood that when gate dielectric layer 112 includes a first gate dielectric layer and a second gate dielectric layer on a top surface of the first gate dielectric layer, and the thickness of capacitor dielectric layer 105 is less than the thickness of gate dielectric layer 112, capacitor dielectric layer 105 and gate dielectric layer 112 may have the following relationship: the material of the capacitor dielectric layer 105 is the same as that of the first gate dielectric layer, and the thickness of the capacitor dielectric layer 105 is the same as that of the first gate dielectric layer; or the material of the capacitor dielectric layer 105 is the same as that of the second gate dielectric layer, and the thickness of the capacitor dielectric layer 105 is the same as that of the second gate dielectric layer.
When different semiconductor structures are manufactured, the material and thickness relationship between the capacitor dielectric layer 105 and the gate dielectric layer 112 may be different.
It should be noted that the capacitor dielectric layer may have a single-layer structure or a stacked structure, and the number of layers of the capacitor dielectric layer may be the same as the number of layers of the gate dielectric layer.
It should be further noted that, on the premise that other factors affecting the capacitance value are not changed, the larger the thickness of the capacitor dielectric layer 105 is, the smaller the capacitance value of the antifuse capacitor is, and therefore, the thickness of the capacitor dielectric layer 105 can be set reasonably based on different requirements for the capacitance value of the antifuse capacitor. It should be noted that, the thickness of the capacitor dielectric layer 105 refers to the thickness of the capacitor dielectric layer 105 between the first source-drain doped region 103 and the capacitor conductive layer 106 along the direction parallel to the surface of the substrate 100.
The thickness of the capacitor dielectric layer 105 is not suitable to be too small, if the thickness of the capacitor dielectric layer 105 is too small, the voltage required for breakdown of the capacitor dielectric layer 105 is correspondingly small, and the anti-fuse capacitor is prone to premature breakdown; the thickness of the capacitor dielectric layer 105 should not be too large, and if the thickness of the capacitor dielectric layer 105 is too large, the difficulty of breaking down the capacitor dielectric layer 105 is large. Therefore, in the present embodiment, the thickness of the capacitor dielectric layer 105 is 2nm to 5nm, for example, 2.5nm, 3nm, and 4 nm.
The material of the capacitor conductive layer 106 includes polysilicon, copper, aluminum, or tungsten. In this embodiment, the material of the capacitor conductive layer 106 is the same as that of the gate conductive layer 122. In other embodiments, the material of the capacitor conductive layer and the gate conductive layer may be different.
To facilitate electrical connection, the substrate 100 exposes a surface of the capacitive conductive layer 106. In this embodiment, the capacitor conductive layer 106 is located on the surface of the capacitor dielectric layer 105 and fills the trench 104, and the top of the capacitor conductive layer 106 is flush with the top of the capacitor dielectric layer 105. Thus, it is beneficial to avoid unnecessary electrical connection between the capacitor conductive layer 106 and other regions of the substrate 100; in addition, the capacitor conductive layer 106 fills the trench 104, so that the capacitor conductive layer 105 has a relatively large volume, which is beneficial to reducing the resistance of the capacitor conductive layer 106, reducing the signal loss caused by the capacitor conductive layer 106, and further beneficial to improving the breakdown effect of the antifuse capacitor. It should be noted that, in other embodiments, the capacitor conductive layer may also fill a part of the volume of the trench, and it is ensured that the surface of the capacitor dielectric layer in the region corresponding to the sidewall of the first source-drain doped region is covered by the capacitor conductive layer; alternatively, the top surface of the capacitor conductive layer may be higher than the substrate surface.
Referring to fig. 1, in the semiconductor structure with a brand-new structure provided in this embodiment, the anti-fuse capacitor is disposed in the substrate 100, the gate structure 102 is electrically connected to the word line WL, the second source-drain doped region 113 is electrically connected to the bit line BL, and the capacitor conductive layer 106 is electrically connected to the external power supply VCP. A first voltage is applied to the gate structure 102 through the word line WL, a second voltage is applied to the second source-drain doped region 113 through the bit line BL, and a third voltage is applied to the capacitor conductive layer 106 through the external power supply VCP. When the first voltage, the second voltage and the third voltage meet the condition of breaking down the capacitor dielectric layer 105, the capacitor dielectric layer 105 is broken down, and the anti-fuse capacitor is conducted; when the first voltage, the second voltage, and the third voltage do not satisfy the condition for breakdown of the capacitor dielectric layer 105, the capacitor dielectric layer 105 is not broken down, and the corresponding anti-fuse capacitor is not conducted.
Moreover, the anti-fuse capacitor is located in the substrate 100, and the source or the drain of the control transistor is also used as a lower electrode plate of the anti-fuse capacitor, which is beneficial to reducing the space occupied by the anti-fuse capacitor.
Correspondingly, the embodiment of the invention also provides a memory, which comprises the semiconductor structure.
Correspondingly, an embodiment of the present invention further provides a manufacturing method for manufacturing the semiconductor structure, including: providing a substrate; forming a grid structure on the surface of the substrate, wherein a first source-drain doped region is formed in the substrate on one side of the grid structure, the doping type of the first source-drain doped region is N-type doping or P-type doping, a second source-drain doped region is formed in the substrate on the other side of the grid structure, the second source-drain doped region and the first source-drain doped region are respectively positioned on two opposite sides of the grid structure, and the doping type of the second source-drain doped region is the same as that of the first source-drain doped region; forming a groove in the substrate with partial thickness, wherein the top of the groove is exposed out of the substrate; forming a capacitance dielectric layer at the bottom and the side wall of the groove; forming a capacitor conducting layer for filling the groove on the capacitor dielectric layer; and the capacitance dielectric layer covers the side wall of the first source-drain doped region.
It should be noted that the semiconductor structure provided in the previous embodiment is not limited to be manufactured by the following manufacturing methods, and the semiconductor structure may be manufactured by other manufacturing methods. The method for manufacturing a semiconductor structure according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
Fig. 5 to 8 are schematic cross-sectional views corresponding to steps of a method for manufacturing a semiconductor structure according to an embodiment of the invention. In the embodiment, before the gate structure is formed, the trench is formed; in the process step of forming the gate dielectric layer in the gate structure, the capacitor dielectric layer is formed at the same time.
Referring to fig. 5, a substrate 100 is provided; a trench 104 is formed within a portion of the thickness of the substrate 100 and the substrate 100 exposes the top of the trench 104.
The process steps for forming the trench 104 include: forming a patterned photoresist layer on the surface of the substrate 100, wherein the patterned photoresist layer exposes the region of the substrate 100 where the trench 104 is to be formed; etching the substrate 100 by using the patterned photoresist layer as a mask and adopting an anisotropic etching process to form a pre-groove; then, etching the substrate 100 exposed from the bottom and the side wall of the pre-groove by adopting an isotropic etching process to form a groove 104; and removing the patterned photoresist layer.
A well region may also be formed in the substrate 100, the doping type of the well region is N-type doping or P-type doping, and the doping ion type of the well region is different from the doping ion type of the subsequently formed first source-drain doping region and the second source-drain doping region.
Referring to fig. 6, a gate dielectric layer 112 in a gate structure is formed on the surface of the substrate 100; a capacitor dielectric layer 105 is formed on the sidewalls of the trench 104.
The gate dielectric layer 112 and a subsequently formed gate conductive layer jointly form a gate structure; to save process steps, the capacitor dielectric layer 105 is formed simultaneously during the process step of forming the gate dielectric layer 112.
In this embodiment, the gate dielectric layer 112 is a single-layer structure. In the process step of forming gate dielectric layer 112, capacitor dielectric layer 105 is simultaneously formed. Correspondingly, the material of gate dielectric layer 112 is the same as the material of capacitor dielectric layer 105, and the thickness of gate dielectric layer 112 is the same as the thickness of capacitor dielectric layer 105.
In this embodiment, the capacitor dielectric layer 105 covers the bottom and the entire sidewall of the trench 104. In other embodiments, the capacitor dielectric layer may cover only the sidewall of the trench near the gate dielectric layer.
The process steps for forming the gate dielectric layer 112 and the capacitor dielectric layer 105 include: forming a gate dielectric film on the bottom and the side wall of the trench 104 and the surface of the substrate 100; the gate dielectric film is patterned to form a gate dielectric layer 112 and a capacitor dielectric layer 105. The process for forming the gate dielectric film can be chemical vapor deposition, physical vapor deposition or thermal oxidation process.
It should be noted that, in other embodiments, the gate dielectric layer may also be a stacked structure, and accordingly, the process step of forming the gate dielectric layer includes: forming a first gate dielectric layer; forming a second gate dielectric layer on the top surface of the first gate dielectric layer; correspondingly, in the process step of forming the first gate dielectric layer or the second gate dielectric layer, the capacitor dielectric layer is formed at the same time. Or, the capacitor dielectric layers may also be of a stacked structure, and in the process step of forming the first gate dielectric layer and the second gate dielectric layer, the capacitor dielectric layers are formed at the same time, and the number of layers of the corresponding capacitor dielectric layers is the same as the number of layers of the gate dielectric layers.
Before or after forming the gate dielectric layer 112, further comprising: isolation structures 101 are formed within substrate 100 with gate dielectric layer 112 and trenches 104 located between adjacent isolation structures 101.
Referring to fig. 7, a first source drain doped region 103 and a second source drain doped region 113 are formed.
Specifically, a first source-drain doped region 103 is formed in the substrate 100 on one side of the gate structure, and the doping type of the first source-drain doped region 103 is N-type doping or P-type doping; and forming a second source-drain doped region 113 in the substrate 100 on the other side of the gate structure, wherein the second source-drain doped region 113 and the first source-drain doped region 103 are respectively located on two opposite sides of the gate structure, and the doping type of the second source-drain doped region 113 is the same as that of the first source-drain doped region 103. It should be noted that the gate conductive layer in the gate structure is not formed yet, but the gate dielectric layer 112 plays a role in positioning the gate structure.
In this embodiment, in a direction perpendicular to the surface of the substrate 100, the length of the sidewall of the trench 104 exposing the first source-drain doped region 103 is equal to the length of the sidewall of the first source-drain doped region 103. In other embodiments, in the direction perpendicular to the substrate surface, the length of the sidewall of the first source-drain doped region exposed by the trench may also be smaller than the length of the first source-drain doped region.
Referring to fig. 8, a gate conductive layer 122 is formed on the top surface of the gate dielectric layer 112, and the gate conductive layer 122 and the gate dielectric layer 112 together form a gate structure 102; and forming a capacitor conductive layer 106 on the surface of the capacitor dielectric layer 105 to fill the trench 104.
In the process step of forming the gate conductive layer 122, the capacitor conductive layer 106 is simultaneously formed.
In this embodiment, the capacitor conductive layer 106 fills the trench 104. The process steps for forming the gate conductive layer 122 and the capacitor conductive layer 106 include: forming a conductive film covering the gate dielectric layer 112 on the substrate 100, wherein the conductive film fills the trench 104; the conductive film on the surface of substrate 100 is removed, and the conductive film on the top surface of gate dielectric layer 112 and in trench 104 remains.
In other embodiments, the top surface of the capacitor conductive layer may be higher than the substrate surface; alternatively, the capacitor conductive layer may fill only a portion of the trench.
In this embodiment, before the gate conductive layer 122 is formed, the first source-drain doped region 103 and the second source-drain doped region 113 are formed, which is beneficial to avoiding process damage to the gate conductive layer 122 and the capacitor conductive layer 106 caused by the process of forming the first source-drain doped region 103 and the second source-drain doped region 113. In other embodiments, the gate conductive layer and the capacitor conductive layer may be formed first, and then the first source-drain doped region and the second source-drain doped region may be formed.
The method for manufacturing a semiconductor structure provided by the embodiment can manufacture a semiconductor structure with a brand new structure, wherein the anti-fuse capacitor is positioned in the substrate 100; moreover, the manufacturing process of the anti-fuse capacitor is compatible with the manufacturing process of the transistor, namely, the anti-fuse capacitor can be simultaneously manufactured by utilizing the CMOS manufacturing process, so that the manufacturing process of the semiconductor structure with the anti-fuse capacitor is simplified, and the manufacturing cost is reduced.
Fig. 9 to 12 are schematic cross-sectional views corresponding to steps of a method for manufacturing a semiconductor structure according to another embodiment of the invention. Different from the previous embodiment, in the manufacturing method provided in this embodiment, after the first source-drain doped region and the second source-drain doped region are formed, the trench is formed. The following detailed description will be made with reference to the accompanying drawings, and it should be noted that the same or corresponding portions as those of the foregoing embodiments will not be described in detail below.
Referring to fig. 9, a substrate 200 is provided; forming a first gate dielectric layer 212 on the surface of the substrate 200; forming a first source-drain doped region 203 in the substrate 200 on one side of the first gate dielectric layer 212; and forming a second source-drain doped region 213 in the substrate 200 on the other side of the first gate dielectric layer 212.
Further comprising: isolation structures 201 are formed in the substrate 200, and the first gate dielectric layer 212, the first source-drain doped region 203 and the second source-drain doped region 213 are located between adjacent isolation structures 201.
Referring to fig. 10, a trench 204 is formed in a partial thickness of the substrate 200, the substrate 200 exposes the top of the trench 204, and the trench 204 exposes sidewalls of the first source-drain doped region 203.
In this embodiment, after the first source-drain doped region 203 and the second source-drain doped region 213 are formed, the trench 204 is formed, which is beneficial to avoiding process damage to the surface of the trench 204 caused by the process of forming the first source-drain doped region 203 and the second source-drain doped region 213, so as to ensure that a subsequently formed capacitor dielectric layer has a good process interface foundation, thereby improving the quality of the formed capacitor dielectric layer and effectively improving the electrical performance of the antifuse capacitor.
Referring to fig. 11, a second gate dielectric layer 213 is formed on the top surface of the first gate dielectric layer 212; a capacitor dielectric layer 205 is formed on the sidewall of the trench 204, and the capacitor dielectric layer 205 covers the sidewall of the first source-drain doped region 203.
The second gate dielectric layer 213 and the first gate dielectric layer 212 together form a gate dielectric layer, and the material of the second gate dielectric layer 213 and the material of the first gate dielectric layer 212 may be the same or different.
In this embodiment, the capacitor dielectric layer 205 is formed simultaneously during the process step of forming the second gate dielectric layer 213.
Since the trench 204 is formed after the first source-drain doped region 203 and the second source-drain doped region 213 are formed, the surface of the trench 204 is prevented from being damaged, so that the surface performance of the trench 204 is good, the interface performance between the formed capacitor dielectric layer 205 and the trench 204 is excellent, and adverse effects caused by surface defects of the trench 204 are avoided.
Referring to fig. 12, a gate conductive layer 222 is formed on a top surface of the gate dielectric layer; a capacitor conductive layer 206 filling the trench 204 is formed on the capacitor dielectric layer 205.
Specifically, a gate conductive layer 222 is formed on the top surface of the second gate dielectric layer 213, and the capacitor conductive layer 206 is simultaneously formed in the process step of forming the gate conductive layer 222.
It should be noted that, in other embodiments, a gate last process (gate last) may also be used to form the semiconductor structure, and before the first source-drain doped region and the second source-drain doped region are formed, a dummy gate (dummy gate) is used to occupy a spatial position of the gate structure; removing the virtual gate between the first source drain doped region and the second source drain doped region, and forming a groove; and then forming a gate dielectric layer, and simultaneously forming a capacitor dielectric layer in the process step of forming the gate dielectric layer.
In the method for manufacturing the semiconductor structure provided by this embodiment, the first source-drain doped region 203 and the second source-drain doped region 213 are formed first, and then the trench 204 is formed, which is beneficial to ensuring that the surface of the trench 204 has few defects, and correspondingly improves the quality of the formed capacitor dielectric layer 205, so that the capacitor dielectric layer 205 and the trench 204 have good interface performance, thereby being beneficial to improving the electrical performance of the antifuse capacitor, and further improving the electrical performance of the semiconductor structure.
It should be noted that the sequence of the steps in the manufacturing method is not fixed, the sequence of the steps may be adjusted according to actual situations, and each step may also include at least two substeps.
It should be noted that the semiconductor structure provided by the embodiment of the present invention is not limited to be manufactured by the above-mentioned manufacturing method, and the semiconductor structure provided by the embodiment of the present invention may be manufactured by other suitable manufacturing methods.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A semiconductor structure, comprising:
the gate structure is positioned on the surface of the substrate;
the first source-drain doped region is positioned in the substrate on one side of the grid structure, and the doping type of the first source-drain doped region is N-type doping or P-type doping;
the second source-drain doped region and the first source-drain doped region are respectively positioned at two opposite sides of the grid structure, and the doping type of the second source-drain doped region is the same as that of the first source-drain doped region;
the anti-fuse capacitor is positioned in the substrate, the first source-drain doped region is used as an electrode plate of the anti-fuse capacitor, and the anti-fuse capacitor further comprises: the capacitor comprises a capacitor dielectric layer positioned on the surface of the side wall of the first source-drain doped region and a capacitor conducting layer positioned on the surface of the capacitor dielectric layer.
2. The semiconductor structure of claim 1, wherein a trench is formed in the substrate and exposes the first source drain doped region sidewall; the capacitor dielectric layer covers the side wall of the first source drain doped region exposed out of the groove; the capacitor conducting layer fills the groove; and in the direction vertical to the surface of the substrate, the cross section of the groove is square or U-shaped.
3. The semiconductor structure of claim 2, wherein said capacitor dielectric layer is located at the bottom of said trench and over the entire sidewall surface; the cross section of the groove is U-shaped in the direction vertical to the surface of the substrate.
4. The semiconductor structure of claim 2, wherein the capacitor conductive layer fills the trench.
5. The semiconductor structure of claim 1, wherein the length of the sidewall of the first source-drain doped region covered by the capacitor dielectric layer is less than or equal to the length of the sidewall of the first source-drain doped region in a direction perpendicular to the surface of the substrate.
6. The semiconductor structure of claim 1, wherein the gate structure comprises a gate dielectric layer and a gate conductive layer on a top surface of the gate dielectric layer; the material of the capacitor dielectric layer is the same as that of the gate dielectric layer; or the material of the capacitor dielectric layer is different from that of the gate dielectric layer.
7. The semiconductor structure of claim 6, wherein the gate dielectric layer comprises a first gate dielectric layer and a second gate dielectric layer on a top surface of the first gate dielectric layer; the material of the capacitor dielectric layer is the same as that of the first gate dielectric layer, and the thickness of the capacitor dielectric layer is the same as that of the first gate dielectric layer; or the material of the capacitor dielectric layer is the same as that of the second gate dielectric layer, and the thickness of the capacitor dielectric layer is the same as that of the second gate dielectric layer.
8. The semiconductor structure of claim 6, wherein a material of the capacitor dielectric layer is the same as a material of the gate dielectric layer; the thickness of the capacitor dielectric layer is smaller than or equal to that of the gate dielectric layer.
9. The semiconductor structure according to claim 1 or 6, wherein a material of the capacitor conductive layer is the same as a material of the gate conductive layer; alternatively, the material of the capacitor conductive layer is different from the material of the gate electrode layer.
10. The semiconductor structure of claim 1, wherein a material of the capacitance conductive layer comprises one or more of polysilicon, copper, aluminum, or tungsten.
11. A memory comprising the semiconductor structure of any one of claims 1-10.
12. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a gate structure on the surface of the substrate, wherein a first source-drain doped region is formed in the substrate on one side of the gate structure, the doping type of the first source-drain doped region is N-type doping or P-type doping, a second source-drain doped region is formed in the substrate on the other side of the gate structure, the second source-drain doped region and the first source-drain doped region are respectively positioned on two opposite sides of the gate structure, and the doping type of the second source-drain doped region is the same as that of the first source-drain doped region;
Forming a groove in the substrate with partial thickness, wherein the substrate exposes the top of the groove;
forming a capacitance dielectric layer on the side wall of the groove;
forming a capacitor conducting layer filling the groove on the surface of the capacitor dielectric layer;
and the capacitance dielectric layer covers the side wall of the first source-drain doped region.
13. The method of fabricating a semiconductor structure according to claim 12, wherein the trench is formed before the gate structure is formed; and in the process step of forming the gate dielectric layer in the gate structure, the capacitor dielectric layer is formed at the same time.
14. The method of fabricating a semiconductor structure of claim 13, wherein the process step of forming the gate dielectric layer comprises: forming a first gate dielectric layer; forming a second gate dielectric layer on the top surface of the first gate dielectric layer; and in the process step of forming the first gate dielectric layer or the second gate dielectric layer, simultaneously forming the capacitor dielectric layer.
15. The method for manufacturing a semiconductor structure according to claim 13, wherein the first source-drain doped region and the second source-drain doped region are formed before forming the gate conductive layer in the gate structure after forming the gate dielectric layer.
16. The method for manufacturing a semiconductor structure according to claim 12 or 13, wherein the capacitor conductive layer is formed simultaneously in the process step of forming the gate conductive layer in the gate structure.
17. The method for manufacturing a semiconductor structure according to claim 12, wherein the trench is formed after the first source-drain doped region and the second source-drain doped region are formed.
18. The method of fabricating a semiconductor structure of claim 17, wherein the step of forming a gate dielectric layer in the gate structure comprises: forming a first gate dielectric layer; forming a second gate dielectric layer on the top surface of the first gate dielectric layer; after the first gate dielectric layer is formed, forming the first source-drain doped region and the second source-drain doped region; and in the process step of forming the second gate dielectric layer, simultaneously forming the capacitor dielectric layer.
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