CN106653729A - Anti-fuse structure and manufacturing method thereof - Google Patents

Anti-fuse structure and manufacturing method thereof Download PDF

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Publication number
CN106653729A
CN106653729A CN201510733668.1A CN201510733668A CN106653729A CN 106653729 A CN106653729 A CN 106653729A CN 201510733668 A CN201510733668 A CN 201510733668A CN 106653729 A CN106653729 A CN 106653729A
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CN
China
Prior art keywords
fin
grid
area
anti
gate dielectric
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CN201510733668.1A
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Chinese (zh)
Inventor
赵劼
钟汇才
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中国科学院微电子研究所
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Priority to CN201510733668.1A priority Critical patent/CN106653729A/en
Publication of CN106653729A publication Critical patent/CN106653729A/en

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Abstract

The invention provides an anti-fuse structure, which comprises a semiconductor substrate, a fin on the semiconductor substrate, a gate dielectric layer at the surface of the fin and a grid electrode on the gate dielectric layer, wherein the fin is a lower electrode, and the grid electrode is an upper electrode. According to the invention, an anti-fuse is formed by adopting a fin structure, the fin is a lower electrode, the grid electrode on the fin is an upper electrode, the fin-based anti-fuse structure is smaller in area and higher in capacity, and a requirement of high integration degree of a device is met. Meanwhile, the anti-fuse structure can be well compatible with a fin device, and the process compatibility is good.

Description

A kind of anti-fuse structures and its manufacture method

Technical field

The present invention relates to semiconductor devices and manufacture field, more particularly to a kind of anti-fuse structures and its manufacture Method.

Background technology

Antifuse is usually sandwich structure, is made up of the insulative dielectric material of upper/lower electrode and centre. Used as memory, before programming, antifuse upper/lower electrode is in high-impedance state, it will usually have hundreds of million More than Europe, represent a kind of storage state;In programming, program voltage is applied between upper/lower electrode, compiled After journey, middle dielectric substance is breakdown, and antifuse upper/lower electrode is in low resistive state, generally exists Below hundreds of ohm, then another kind of storage state is represented.

At present, antifuse mainly adopts planar structure, and it realizes that area is larger, and with semiconductor work The continuous propulsion of skill process, planar structure cannot realize the jumbo requirement of small area, and device can not have been met The requirement of part Highgrade integration.

The content of the invention

In view of this, it is an object of the invention to provide a kind of anti-fuse structures and its manufacture method, improve The integrated level of antifuse.

For achieving the above object, the present invention has following technical scheme:

A kind of anti-fuse structures, including:

Semiconductor substrate;

Fin in Semiconductor substrate, fin is bottom electrode;

Gate dielectric layer on fin surface;

Grid on gate dielectric layer, grid is Top electrode.

The material of the gate dielectric layer is high K medium material.

Optionally, the grid is sandwich construction, including metal gates and polysilicon layer thereon.

Optionally, the material of the metal gates is Ti, TiAlx、TiN、TaNx、HfN、TiCxOr TaCx

Optionally, also including the doped region in the fin of grid both sides, contact is formed with doped region.

Optionally, also including selector, selector include gate dielectric layer and grid on fin, fin, The source-drain area of grid both sides, source-drain area contact with anti-fuse structures doped region electrical connection of selector.

Additionally, present invention also offers a kind of manufacture method of anti-fuse structures, including:

Semiconductor substrate is provided, there is first area on substrate;

Fin is formed on substrate;

Gate dielectric layer is formed on the surface of fin;

Grid is formed on gate dielectric layer;

First area is used to form anti-fuse structures, and the fin on first area is bottom electrode, and grid is upper electricity Pole.

Optionally, also include:Doped region is formed in the fin of grid both sides, contact is formed with doped region.

Optionally, also there is second area, second area is used to form selector, selector on substrate The contact with anti-fuse structures doped region of the source-drain area of part is electrically connected.

Optionally, the material of the gate dielectric layer is high K medium material, and the grid is sandwich construction, Polysilicon including metal gates and thereon.

Anti-fuse structures provided in an embodiment of the present invention and its manufacture method, form anti-molten using fin structure Silk, fin is bottom electrode, and the grid on fin is Top electrode, and the anti-fuse structures based on fin have less face Product and bigger capacity, meet the requirement of device high integration, meanwhile, can be good with fin device Compatibility, processing compatibility is good.

Description of the drawings

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality Apply the accompanying drawing to be used needed for example or description of the prior art to be briefly described, it should be apparent that, below Accompanying drawing in description is some embodiments of the present invention, for those of ordinary skill in the art, not On the premise of paying creative work, can be with according to these other accompanying drawings of accompanying drawings acquisition.

Fig. 1 shows the structural representation of anti-fuse structures according to embodiments of the present invention;

The flow chart of manufacture method Fig. 2 according to embodiments of the present invention;

Fig. 3-Fig. 7 shows that manufacture method according to embodiments of the present invention forms each mistake of anti-fuse structures Cross-sectional view in journey.

Specific embodiment

It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings The specific embodiment of the present invention is described in detail.

Many details are elaborated in the following description in order to fully understand the present invention, but this Bright to be different from alternate manner described here implementing using other, those skilled in the art can be with Similar popularization, therefore the present invention are done in the case of without prejudice to intension of the present invention not by following public concrete The restriction of embodiment.

Secondly, the present invention is described in detail with reference to schematic diagram, is just when the embodiment of the present invention is described in detail In explanation, represent that the profile of device architecture can disobey general ratio and make partial enlargement, and the signal Figure is example, and its here should not limit the scope of protection of the invention.Additionally, should wrap in actual fabrication Three-dimensional space containing length, width and depth.

As the description of background technology, in order to improve the integrated level of device, the present invention proposes a kind of anti-molten Silk structure, with reference to shown in Fig. 1, including:

Semiconductor substrate 100;

Fin 110 in Semiconductor substrate 100, fin 110 is bottom electrode;

Gate dielectric layer 130 on the surface of fin 110;

Grid 140 on gate dielectric layer 130, grid 140 is Top electrode.

The anti-fuse structures of the present invention, using fin structure antifuse is formed, and fin is bottom electrode, on fin Grid is Top electrode, and the anti-fuse structures based on fin have less area and bigger capacity, meet device The requirement of part high integration, meanwhile, can be good compatible with fin device, processing compatibility is good.

In embodiments of the present invention, the Semiconductor substrate 100 can be Si substrates, Ge substrates etc.. Can also be the substrate for including other elements semiconductor or compound semiconductor in other embodiment, example Such as GaAs, InP or SiC, can also be laminated construction, such as Si/SiGe etc..

The fin 110 is formed on a semiconductor substrate, can in itself be formed by substrate, between fin 110 Isolation 120 is formed with, isolation 120 is formed in the bottom of fin, adjacent device isolation is opened.

The gate dielectric layer 130 and grid 140 are to form the gate dielectric material in fin formula field effect transistor And grid material, it is preferred that the material of gate dielectric layer 130 be high K medium material, high K medium material Compare with silica, the material with high-k, high K medium material such as hafnium base oxide, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc.;More preferably, grid is the structure of multilayer, Polysilicon including metal gates and thereon, metal gates can be single or multiple lift structure, metal gates Material for example can be Ti, TiAlx、TiN、TaNx、HfN、TiCxOr TaCxOr theirs is folded Layer.The anti-fuse structures of the Top electrode of the dielectric layer with high K medium material and metal gates, with height The fin formula field effect transistor of k/ metal gates has good processing compatibility, meanwhile, in programming, polycrystalline Silicon layer loads high voltage, under suitable voltage conditions, what the gate dielectric layer of high-k gate dielectric material punctured Meanwhile, metal gates can also be together breakdown, and gate dielectric has stable material behavior, it is ensured that The reliability after stability and programming before programming, improves the performance of device.

Additionally, the anti-fuse structures can have multi-gate structure, such as three grid structures, a plurality of fin passes through grid Couple together, driving current can be increased, improve the performance of device.

In an embodiment of the present invention, gate dielectric layer 130 and grid 140 can be formed in fin 110 Portion, same fin formula field effect transistor still forms doped region in the fin of the both sides of grid 140, meanwhile, On doped region formed contact, can from the contact at doped region two ends punctured after two ends electric current, So as to verify puncture it is whether effective.

The reading of programming and electric current for the ease of above-mentioned anti-fuse structures, is also formed with choosing on substrate Device is selected, selector can be the fin formula field effect transistor essentially identical with anti-fuse structures, including Gate dielectric layer and grid, the source-drain area of grid both sides on fin, fin, the gate dielectric layer of selector with And grid can have identical or different material, structure with the gate dielectric layer of anti-fuse structures and grid, The contact with anti-fuse structures doped region of the source-drain area of selector is electrically connected, and can be passed through on contact Metal connecting line layer realize the electrical connection of the two.So, when programming or reading electric current, first gating is selected Device, selector source-drain current flows to the source and drain of anti-fuse structures, and the Top electrode of fuse-wires structure applies electricity After pressure, puncturing or turning on for fuse-wires structure is realized, so as to realizing programming or obtaining the electric conduction after programming Stream.

The embodiment of the anti-fuse structures of the present invention is described in detail above, additionally, of the invention The manufacture method of above-mentioned anti-fuse structures is additionally provided, with reference to shown in Fig. 2, including:

Substrate is provided, there is first area on substrate;

Fin is formed on substrate;

Gate dielectric layer is formed on the surface of fin;

Grid on gate dielectric layer;

First area is used to form antifuse, and the fin on first area is bottom electrode, and grid is Top electrode.

In the manufacture method, fin is bottom electrode, and the grid on fin is Top electrode, can be with fin device Well compatible, processing compatibility is good, meanwhile, the anti-fuse structures of formation have less area and more Big capacity, meets the requirement of device high integration.

In order to be better understood from technical solution of the present invention and technique effect, below with reference to flow chart and accompanying drawing Fig. 3-Fig. 7 is described in detail to the manufacture method of specific embodiment, and wherein Fig. 3-Fig. 7 is along grid The cross-sectional view of the area of grid of cross direction, may be referred to Fig. 1, and grid carries out section along Fig. 1, The structural representation of section is carried out to grid with fin vertical direction.

In step S101, there is provided Semiconductor substrate 100, there is first area, with reference to Fig. 2 institutes on substrate Show.

In embodiments of the present invention, the Semiconductor substrate 100 can be Si substrates, Ge substrates etc.. Can also be the substrate for including other elements semiconductor or compound semiconductor in other embodiment, example Such as GaAs, InP or SiC, can also be laminated construction, such as Si/SiGe etc..

In the present embodiment, the substrate is body silicon substrate.First area on substrate is used to form anti-molten Silk structure, it is to be understood that can also further have the area for forming other devices on substrate Domain, such as forms the second area of field-effect transistor, in the present embodiment, field effect is formed on second area Transistor is answered, as the selector of anti-fuse structures.

In step S102, fin 110 is formed on the substrate 100, with reference to shown in Fig. 3.

In the present embodiment, specifically, first, hard mask layer 112 is formed on the substrate 100, firmly Mask layer 112 can be single or multiple lift structure, for example, can be silicon nitride;Then, in hard mask Form photosensitive etching agent on layer 112, and carry out it is exposed and developed, to form etching pattern, then, Hard mask layer 112 is patterned, and removes photosensitive etching agent;Then, with hard mask layer 112 To shelter, the etching of substrate 100 is carried out, so as to form fin 110, as shown in Figure 3.

After fin 110 is formed, the isolation 120 between fin 110 is formed, with reference to shown in Fig. 4.

Specifically, first, the filling of isolated material is carried out, isolated material is dielectric material, for example may be used Think silica, after filling, planarized, such as carry out cmp (CMP) work Skill, with hard mask layer 112 as stop-layer;Then, wet etching, such as high temperature phosphoric acid can be adopted to go The hard mask of silicon nitride;Then, lithographic technique, such as wet etching can be adopted, it is rotten using hydrofluoric acid Etching off remove certain thickness isolated material, the isolated material of member-retaining portion between fin, so as to define every Absciss layer 120, as shown in Figure 3.

In the step, the fin that first area is formed is used for the bottom electrode as anti-fuse structures, the secondth area The fin that domain is formed is used to form field-effect transistor or other devices.

In step S103, gate dielectric layer 130 is formed on the surface of fin 110, as shown in Figure 5.

In embodiments of the present invention, the gate dielectric layer 130 of first area and second area can select phase Same material is formed, and can be selected according to the device to be formed, can be used as the gate medium of device Layer can be with breakdown when programming in anti-fuse structures simultaneously, and so, process integration is higher, and work Skill is more simple.Certainly, the gate dielectric layer 130 of first area and second area can also select difference Dielectric material respectively being formed.

In the present embodiment, more preferably, the material of gate dielectric layer 130 of first area and second area is all High K medium material, high K medium material is compared with silica, the material with high-k, high k Dielectric material such as hafnium base oxide, HFO2、HfSiO、HfSiON、HfTaO、HfTiO.For The thickness of the gate dielectric layer in one region, can be according to the gate medium material of breakdown performance target setting desired thickness The thickness of material, for the thickness of the gate dielectric layer of second area comes true by the performance of FET device Fixed, thickness can be in 1-10nm, and gate dielectric layer can pass through ALD, PLD, MOCVD or other conjunctions Suitable method deposits respectively the gate dielectric layer of desired thickness in first area and second area.In specific device In part design, the thickness of the gate dielectric layer of second area is greater than the thickness of the gate dielectric layer of first area, So, in the gate dielectric layer breakdown process of anti-fuse structures, the gate dielectric layer of FET device Will not puncture, it is ensured that the normal work of device.

Then, in step S104, grid is formed on gate dielectric layer 130, with reference to shown in Fig. 7.

In embodiments of the present invention, the grid of first area and second area can select identical structure Formed with material, can be single or multiple lift structure, can be selected according to the device to be formed, Can be as the grid of device simultaneously in anti-fuse structures as Top electrode, so, process integration is more Height, and technique is more simple.Certainly, the grid of first area and second area can also select difference Grid material respectively being formed.

In the present embodiment, more preferably, the grid of first area and second area can select identical to tie Structure and material are forming respectively.Specifically, first, on gate dielectric layer 130 respectively in first area and Metal gates 1401 are formed on second area, as shown in fig. 6, metal gates 1401 can be individual layer or many Rotating fields, such as include metal work function regulating course, and the material of the metal gates is Ti, TiAlx、TiN、 TaNx、HfN、TiCxOr TaCxOr their combination;Then, respectively in first area and the secondth area Polysilicon layer 1402 is formed on domain metal gates 1402.The thickness of the grid of second area can be more than first The thickness of the grid in region, so that anti-fuse structures can bear higher program voltage.

In this preferred embodiment, the upper electricity of dielectric layer and metal gates with high K medium material The anti-fuse structures of pole, have good processing compatibility with the fin formula field effect transistor of high k/ metal gates, Meanwhile, in programming, polysilicon layer loading high voltage, under suitable voltage conditions, high-k gate dielectric While the gate dielectric layer of material punctures, metal gates can also be together breakdown, can further improve Breakdown performance.

Then, patterned, in first area and second area grid and gate dielectric layer are formed respectively. In patterning, etching pattern can be passed through so that a grid connects a plurality of fin, is formed and has multiple-grid The structure of structure, such as three grid structures, a plurality of fin is coupled together by grid, can increase driving current, Improve the performance of device.

Afterwards, technique can be doped, in the fin of first area grid both sides doped region is formed, Source-drain area is formed in the fin of second area.Then, in the doped region and the source and drain of second area of first area Contact is formed in area, and the metal connecting line layer formed by after realizes the electrical connection of the two.In order to reality Now program or obtain the conducting electric current after programming.

By the field-effect transistor of formation on the second region, can be used as the selection of anti-fuse structures Device, is easy to the programming of above-mentioned anti-fuse structures and the reading of electric current, the selector can be with instead The essentially identical fin formula field effect transistor of fuse-wires structure, source-drain area and the anti-fuse structures of selector are mixed Contact electrical connection in miscellaneous area, can realize the electrical connection of the two by the metal connecting line layer on contact. So, when programming or reading electric current, selector is first gated, selector source-drain current flow direction is anti-molten The source and drain of silk structure, after the Top electrode applied voltage of fuse-wires structure, realizes puncturing or turning on for fuse-wires structure, So as to realizing programming or obtaining the conducting electric current after programming.So far, the anti-of the embodiment of the present invention is defined Fuse-wires structure.

The above is only the preferred embodiment of the present invention, although the present invention is with preferred embodiment disclosure As above, however be not limited to the present invention.Any those of ordinary skill in the art, without departing from this Under inventive technique scheme ambit, all using the methods and techniques content of the disclosure above to skill of the present invention Art scheme makes many possible variations and modification, or the Equivalent embodiments for being revised as equivalent variations.Therefore, Every content without departing from technical solution of the present invention, according to the technical spirit of the present invention to above example institute Any simple modification, equivalent variations and the modification made, still falls within the model of technical solution of the present invention protection In enclosing.

Claims (10)

1. a kind of anti-fuse structures, it is characterised in that include:
Semiconductor substrate;
Fin in Semiconductor substrate, fin is bottom electrode;
Gate dielectric layer on fin surface;
Grid on gate dielectric layer, grid is Top electrode.
2. structure according to claim 1, it is characterised in that the material of the gate dielectric layer is height K dielectric materials.
3. structure according to claim 2, it is characterised in that the grid is sandwich construction, bag Include metal gates and polysilicon layer thereon.
4. structure according to claim 3, it is characterised in that the material of the metal gates be Ti, TiAlx、TiN、TaNx、HfN、TiCxOr TaCx
5. the structure according to any one of claim 1-4, it is characterised in that also including grid two Doped region in the fin of side, is formed with contact on doped region.
6. structure according to claim 5, it is characterised in that also including selector, selector Part includes gate dielectric layer and grid, the source-drain area of grid both sides on fin, fin, the source and drain of selector Area's electrical connection of the contact with anti-fuse structures doped region.
7. a kind of manufacture method of anti-fuse structures, it is characterised in that include:
Semiconductor substrate is provided, there is first area on substrate;
Fin is formed on substrate;
Gate dielectric layer is formed on the surface of fin;
Grid is formed on gate dielectric layer;
First area is used to form anti-fuse structures, and the fin on first area is bottom electrode, and grid is upper electricity Pole.
8. manufacture method according to claim 7, it is characterised in that also include:In grid both sides Fin in form doped region, contact is formed with doped region.
9. manufacture method according to claim 8, it is characterised in that also there is the secondth area on substrate Domain, second area is used to form selector, on the source-drain area and anti-fuse structures doped region of selector Contact electrical connection.
10. the manufacture method according to any one of claim 7-9, it is characterised in that the grid are situated between The material of matter layer is high K medium material, and the grid is sandwich construction, including metal gates and thereon Polysilicon.
CN201510733668.1A 2015-11-02 2015-11-02 Anti-fuse structure and manufacturing method thereof CN106653729A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1577797A (en) * 2003-07-22 2005-02-09 台湾积体电路制造股份有限公司 Structure and producing method of back-fuse type memory assembly
CN103456711A (en) * 2012-06-05 2013-12-18 中芯国际集成电路制造(上海)有限公司 Fin-type anti-fuse structure and manufacturing method thereof
US20140299922A1 (en) * 2013-04-03 2014-10-09 International Business Machines Corporation High-k metal gate device structure for human blood gas sensing
CN104183643A (en) * 2013-05-21 2014-12-03 新加坡商格罗方德半导体私人有限公司 Transistor devices having an anti-fuse configuration and methods of forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1577797A (en) * 2003-07-22 2005-02-09 台湾积体电路制造股份有限公司 Structure and producing method of back-fuse type memory assembly
CN103456711A (en) * 2012-06-05 2013-12-18 中芯国际集成电路制造(上海)有限公司 Fin-type anti-fuse structure and manufacturing method thereof
US20140299922A1 (en) * 2013-04-03 2014-10-09 International Business Machines Corporation High-k metal gate device structure for human blood gas sensing
CN104183643A (en) * 2013-05-21 2014-12-03 新加坡商格罗方德半导体私人有限公司 Transistor devices having an anti-fuse configuration and methods of forming the same

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Application publication date: 20170510