CN111987005A - Method for producing a power semiconductor module and power semiconductor module - Google Patents

Method for producing a power semiconductor module and power semiconductor module Download PDF

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Publication number
CN111987005A
CN111987005A CN202010423273.2A CN202010423273A CN111987005A CN 111987005 A CN111987005 A CN 111987005A CN 202010423273 A CN202010423273 A CN 202010423273A CN 111987005 A CN111987005 A CN 111987005A
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China
Prior art keywords
film
embossed
power semiconductor
connection region
composite
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CN202010423273.2A
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Chinese (zh)
Inventor
斯特凡·赫克斯霍尔德
斯特凡·厄尔林
迈克尔·尤努策尔
马库斯·迪泽尔
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Semikron Electronics Co ltd
Semikron Elektronik GmbH and Co KG
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Semikron Electronics Co ltd
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Publication of CN111987005A publication Critical patent/CN111987005A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73269—Layer and TAB connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/749—Tools for reworking, e.g. for shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention relates to a method for producing a power semiconductor module and a power semiconductor module, comprising the following process steps: a) providing a power semiconductor arrangement having a substrate and a power semiconductor component, b) providing an embossed film composite, wherein the embossed film composite is embossed such that, in a normal direction of a first film connection area of the film composite, the first film connection area is arranged at a first height level and a second film connection area is arranged at a second height level higher than the first height level, c) arranging an electrically conductive adhesive on the first and second film connection areas of the embossed film composite and/or on a first conductor track and a second power terminal, d) arranging the embossed film composite on the substrate such that a first portion of the adhesive is in mechanical contact with the first and second film connection areas and the first conductor track and a second portion of the adhesive is in mechanical contact with the second film connection area and the second power terminal, e) the adhesive is hardened.

Description

Method for producing a power semiconductor module and power semiconductor module
Technical Field
The invention relates to a method for producing a power semiconductor module and a power semiconductor module.
Background
DE 102013104949B 3 discloses a power semiconductor module having a substrate, a power semiconductor component and a film composite, wherein the film composite is connected to the power semiconductor component and the substrate in an electrically conductive manner by a pressure-sintered connection.
The production of pressure-sintered connections is technically complicated, since it requires the application of pressure and temperature to the components to be connected to one another. Furthermore, high pressure loads can damage the power semiconductor components and, for example in the case of DCB substrates or AMB substrates, the ceramic layers of the substrates.
Disclosure of Invention
It is an object of the invention to create an efficient method for producing a power semiconductor module, and a power semiconductor module which can be produced efficiently.
This object is achieved by a method for producing a power semiconductor module, having the following process steps:
a) providing a power semiconductor component having: a substrate having a non-conductive insulating layer with a first conductor track and a second conductor track arranged on a first main side of the non-conductive insulating layer; and a power semiconductor component which is arranged on the second conductor track of the substrate and which has a first power terminal on its first main side facing the second conductor track and a second power terminal on its second main side facing away from the second conductor track, the first power terminal being connected to the second conductor track in an electrically conductive manner,
b) providing an embossed film composite having a first film that is electrically non-conductive and a second structured film that is electrically conductive and disposed on the first film, wherein the second film is structured such that the film has a first film connection region and a second film connection region disposed apart from the first film connection region, wherein the embossed film composite is embossed such that, in a direction normal to the first film connection region, the first film connection region is disposed at a first height level and the second film connection region is disposed at a second height level that is higher than the first height level,
c) disposing a conductive adhesive on the first film connection region and the second film connection region of the embossed film composite, and/or on the first conductor rail and the second power terminal,
d) disposing the embossed film composite on the substrate such that a first portion of the adhesive is in mechanical contact with the first film connection region and the first conductor rail, and a second portion of the adhesive is in mechanical contact with the second film connection region and the second power terminal,
e) the adhesive is hardened.
Furthermore, the object is achieved by a power semiconductor module having: a substrate having a non-conductive insulating layer, a first conductor track and a second conductor track being arranged on a first main side of the non-conductive insulating layer; and a power semiconductor component which is arranged on the second conductor track of the substrate and has a first power terminal on a first main side of the power semiconductor component facing the second conductor track and a second power terminal on a second main side of the power semiconductor component facing away from the second conductor track, wherein the first power terminal is connected to the second conductor track in an electrically conductive manner; and the power semiconductor module has an embossed film composite having a non-conductive first film and a conductive structured second film arranged thereon, wherein the second film is structured such that the film has a first film connection region and a second film connection region arranged separately from the first film connection region, wherein the embossed film composite is embossed such that, in a direction normal to the first film connection region, the first film connection region is arranged at a first height level and the second film connection region is arranged at a second height level higher than the first height level; and the power semiconductor module has a conductive hardened adhesive, wherein a first portion of the adhesive conductively connects the first film connection region to the first conductor track and a second portion of the adhesive conductively connects the film connection region to the second power terminal.
An advantageous design of the method follows in a manner similar to an advantageous design of the power semiconductor module and vice versa.
It has proven to be advantageous if in the further process step f) the at least one cavity arranged between the membrane composite and the power semiconductor component is completely filled with a non-conductive potting compound. This provides a very reliable electrical insulation between certain sections of the film composite and the power semiconductor component.
It has proven to be advantageous if the embossed film composite has an electrically conductive third film which is structured to form the film conductor tracks, and the first film is arranged between the second film and the third film. This enables a simple routing of the conductors for the current flowing through the membrane composite.
In this case, it has proved advantageous if the embossed film composite has electrically conductive vias through the first film, which electrically conductively connect the first and second film connection regions to the third film. This enables simple routing of the conductors of the current flowing through the membrane composite.
Furthermore, it has proven to be advantageous if the embossed film composite is embossed such that, when carrying out the processing step d), the embossed film composite aligned with a peripheral region of the edge of the power semiconductor component has an arched profile above said peripheral region, wherein the apex of the arch formed by the arched profile is arranged on that side of the film composite facing the substrate in the direction of the normal of the first film connection region at a third height level which is higher than the second height level. This reliably prevents the film composite from coming into mechanical contact with the mechanically sensitive edge region of the power semiconductor component. Furthermore, this facilitates the arrangement of potting compound, in particular soft or hard potting compound, between the membrane compound and the edge region of the power semiconductor component.
Furthermore, it has proved advantageous if, in the processing step b) for providing an embossed film composite, a method for producing an embossed film composite is carried out with the following processing steps:
b1) an unembossed film composite is disposed between a first die and a second die of a press,
b2) embossing the unembossed film composite by performing a relative movement of the first stamp and the second stamp towards each other such that the first stamp and the second stamp are pressed against the unembossed film composite, thereby forming an embossed film composite from the unembossed film composite, wherein the first stamp and/or the second stamp has a geometry such that, after embossing, in a direction of a normal of the first film connecting area, the first film connecting area is arranged at a first height level and the second film connecting area is arranged at a second height level higher than the first height level,
b3) the embossed film composite is removed from the press.
In this case, it has proved advantageous if, in the processing step b2), the first stamp and the second stamp have a geometry such that, when the processing step d) is carried out, the embossed film composite aligned with the peripheral region of the edge of the power semiconductor component has an arched profile above said peripheral region, wherein the apex of the arch formed by the arched profile is arranged on that side of the film composite facing the substrate in the direction of the normal to the first film connection region at a third height level which is higher than the second height level. This reliably prevents the film composite from coming into mechanical contact with mechanically sensitive edge regions of the power semiconductor components in the power semiconductor module. Furthermore, this facilitates the arrangement of potting compound, in particular soft or hard potting compound, between the membrane compound and the edge region of the power semiconductor component.
Furthermore, it has proved advantageous if the first die has a rigid geometry and the second die is formed from an elastic material, or if the second die has a rigid geometry and the first die is formed from an elastic material, or if the first die and the second die have a rigid geometry, wherein the first die and the second die have a convex and a concave geometry with respect to each other. This results in efficient embossing of the unembossed film composite.
Drawings
Exemplary embodiments of the present invention are described below with reference to the drawings listed below. In the drawings:
figure 1 shows a power semiconductor component and an embossed film composite,
fig. 2 illustrates a power semiconductor assembly and an embossed film composite, wherein a conductive adhesive is disposed on the embossed film composite,
FIG. 3 shows a power semiconductor module according to the invention, and
figure 4 shows a press and an unembossed film composite arranged in the press for embossing purposes.
Like elements in the drawings are labeled with like reference numerals.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
The following describes a method for producing the power semiconductor module 1 (see fig. 3).
In a process step a), an example of which is shown in fig. 1, a power semiconductor component 2 is provided. In an exemplary embodiment, the power semiconductor component 2 has a substrate 3, which substrate 3 has a non-conductive insulating layer 4, on a first main side 4a of which non-conductive insulating layer 4a first and second electrically conductive conductor tracks 5a, 5b and an electrically conductive third conductor track 5c are arranged. The substrate 3 preferably has a conductive, preferably unstructured, metallization layer 6, and the insulating layer 4 is arranged between the metallization layer 6 and the conductor tracks 5a, 5b and 5 c. The insulating layer 4 is preferably designed as a ceramic plate. The substrate 3 may be implemented as, for example, a direct copper bonding substrate (DCB substrate) or an active metal brazing substrate (AMB substrate). Alternatively, the substrate 3 may also be implemented as an insulated metal substrate (IMS substrate).
The power semiconductor component 2 also has a power semiconductor component 7 which is arranged on the second conductor track 5b of the substrate 3 and has a first power terminal 9a on its first main side 8a facing the second conductor track 5b and a second power terminal 9b on its second main side 8b facing away from the second conductor track 5b, wherein the first power terminal 9a is connected to the second conductor track 5b in an electrically conductive manner, preferably via a soldered or sintered metal layer 21. The power semiconductor components 7 are preferably present in the form of transistors, for example IGBTs (insulated gate bipolar transistors) or MOSFETs (metal oxide semiconductor field effect transistors) or diodes. In an exemplary embodiment, the power semiconductor component 7 is designed as an IGBT, wherein the first power terminal 9a forms a collector terminal of the IGBT and the second power terminal 9b forms an emitter terminal of the IGBT. Alternatively, the second power terminal 9b may also form the gate terminal of the IGBT.
In a process step b), an example of which is additionally shown in fig. 1, an embossed film composite 10 is provided, the embossed film composite 10 having a first electrically non-conductive film 11 and an electrically conductive structured second film 12 arranged on the first film 11, wherein the second film 12 is structured such that it has a first film connection region 12a, a second film connection region 12b arranged separately from the first film connection region 12a, and preferably a third film connection region 12c arranged separately from the first film connection region 12a and the second film connection region 12 b. The film connection regions 12a, 12b and 12c can also be present in the form of film conductor track sections, which can be implemented by structuring the second film 12. The embossed film composite 10 preferably has a conductive third film 13 structured to form film conductor tracks 13a and 13b, the first film 11 being disposed between the second film 12 and the third film 13. The first membrane 11 is connected in a material-bonded manner to the second membrane 12 and the third membrane 13. The second film 12 and the third film 13 are preferably formed of a metal film. The first film is preferably embodied as a plastic film. Of course, the film composite 10 may have one or more further structured or unstructured conductive films (e.g., metal films) with a nonconductive film (e.g., plastic film) disposed between each conductive film. Each metal film may have a single layer or a plurality of metal layers stacked on each other. The embossed film composite 10 preferably has conductive vias 14 through the first film 11 that conductively connect the first film connection region 12a, the second film connection region 12b, and the third film connection region 12c to the third film 13, respectively.
The embossed film composite 10 in the present invention is embossed such that the first film connection region 12a is disposed at a first height level H1 and the second film connection region 12b is disposed at a second height level H2 higher than the first height level H1 in a normal direction N of the first film connection region 12 a. It should be noted that for the purpose of the present invention, the normal direction N of the first film connection region 12a is the normal direction N of the surface of the first film connection region 12a facing away from the first film 11, which extends towards the first film 11.
In a subsequent processing step c), an example of which is shown in fig. 2, the conductive adhesive 15 is arranged on the first film connection region 12a, the second film connection region 12b and the third film connection region 12c of the embossed film composite 10 and/or on the first conductor track 5a, the second power terminal 9b and the third conductor track 5 c. Conductive adhesives are part of the general state of the art. The electrical conductivity of the adhesive is preferably achieved by at least one electrically conductive filler material (e.g. silver particles) which is added to the bonding matrix. The conductive binder may be present, for example, in the form of a sintered binder.
In a subsequent process step d), an example of which is shown in fig. 3, the embossed film composite 10 is arranged on the substrate 3 such that a first portion 15a of the adhesive 15 is in mechanical contact with the first film connection region 12a and the first conductor track 5a, a second portion 15b of the adhesive 15 is in mechanical contact with the second film connection region 12b and the second power terminal 9b, and a third portion 15c of the adhesive 15 is in mechanical contact with the third film connection region 12c and the third conductor track 5 c. The embossed film composite 10 is preferably embossed such that, when the processing step d) is performed, the embossed film composite 10 aligned with the surrounding area U of the edge 7' of the power semiconductor component 7 has an arched profile above said surrounding area U, wherein an apex SP of the arch formed by the arched profile B is arranged on that side 10a of the film composite 10 facing the substrate 3 in the normal direction N of the first film connection area 12a at a third height level H3 which is higher than the second height level H2. The peripheral area U of the edge 7 'of the power semiconductor component 7 extends slightly beyond the edge 7' of the power semiconductor component 7.
In a subsequent processing step e), as shown by way of example in fig. 3, the adhesive 15 is hardened, for example by applying temperature or ultraviolet radiation to the adhesive 15.
In the present invention, efficient production of the power semiconductor module 1 is made possible by forming the film composite as an embossed film composite 10 in conjunction with forming a conductive adhesive bond for electrically contacting the film composite 10 to the power semiconductor assembly 2.
In a preferably subsequently performed process step f), at least one cavity 22 arranged between the membrane composite 10 and the power semiconductor component 2 is completely filled with a non-conductive potting compound, in particular a soft or hard potting compound. The potting compound may be formed as, for example, a silicone potting compound or an epoxy potting compound.
In the simplest case, in process step b), the embossed film composite 10 may be provided by making the embossed film composite 10 available in the form of a prefabricated part.
Alternatively, to provide the embossed film composite 10 in the processing step b) (an example of which is shown in fig. 4), the method for producing the embossed film composite 10 may be performed by the following processing steps.
In a first method step b1), the unembossed film composite 10' is arranged between the first stamp 16 and the second stamp 17 of the press 20. The unembossed film composite 10' is the same as the embossed film composite 10 except for the feature that the unembossed film composite has not been embossed.
In a subsequent process step b2), the unembossed film composite 10 ' is embossed by performing a relative movement of the first stamp 16 and the second stamp 17 towards each other such that the first stamp 16 and the second stamp 17 press against the unembossed film composite 10 ', thereby forming an embossed film composite 10 from the unembossed film composite 10 '. The first stamp 16 and/or the second stamp 17 have a geometry such that, after embossing, in the normal direction N of the first film connecting area 12a, the first film connecting area 12a is arranged at a first height level H1 and the second film connecting area 12b is arranged at a second height level H2 higher than the first height level H1. In the exemplary embodiment, the press 20 has a first press element 18 on which the first stamp 16 is arranged and a second press element 19 on which the second stamp 17 is arranged on the first press element 18. In order to perform a relative movement of the first stamp 16 and the second stamp 17 towards each other, in an exemplary embodiment the first press element 18 is moved towards the second press element 19, which movement is shown by an arrow in fig. 1. Alternatively, the second press element 19 can also be moved towards the first press element 18.
In the processing step B2), the first stamp 16 and/or the second stamp 17 preferably have a geometry such that, when the processing step d) is carried out, the embossed film composite 10 aligned with the surrounding area U of the edge 7' of the power semiconductor component 7 has an arched profile above said surrounding area U, wherein an apex SP of the arch formed by the arched profile B is arranged on that side 10a of the film composite 10 facing the substrate 3 in the normal direction N of the first film connection area 12a at a third height level H3 which is higher than the second height level H2.
The first die 16 may have a rigid geometry and the second die 17 may be made of an elastic material. Alternatively, the second die 17 may have a rigid geometry and the first die 16 may be made of an elastic material. For example, the elastic material may be formed of silicone. Alternatively, the first die 16 and the second die 17 may have a rigid geometry, the first die 16 and the second die 17 having a convex and a concave geometry with respect to each other, which is drawn with dashed lines in fig. 4.
In a subsequent process step b3), the embossed film composite 10 is removed from the press 20.
It should be noted here that the features of the different exemplary embodiments of the invention can of course be freely combined with each other, as long as the features are not mutually exclusive.

Claims (9)

1. Method for manufacturing a power semiconductor module (1), comprising the following process steps:
a) providing a power semiconductor component (2), the power semiconductor component (2) having: a substrate (3) having a non-conductive insulating layer (4) on a first main side (4a) of which a first and a second conductor track (5a, 5b) are arranged; and a power semiconductor component (7) which is arranged on the second conductor track (5b) of the substrate (3) and has a first power terminal (9a) on a first main side (8a) of the power semiconductor component facing the second conductor track (5b) and a second power terminal (9b) on a second main side (8b) of the power semiconductor component facing away from the second conductor track (5b), wherein the first power terminal (9a) is connected to the second conductor track (5b) in an electrically conductive manner,
b) providing an embossed film composite (10), the embossed film composite (10) having a first film (11) which is electrically non-conductive and a second structured film (12) which is electrically conductive and which is arranged on the first film, wherein the second film (12) is structured such that the film has a first film connection region (12a) and a second film connection region (12b) which is arranged separately from the first film connection region (12a), wherein the embossed film composite (10) is embossed such that, in a normal direction (N) of the first film connection region (12a), the first film connection region (12a) is arranged at a first height level (H1) and the second film connection region (12b) is arranged at a second height level (H2) which is higher than the first height level (H1),
c) arranging a conductive adhesive (15) on the first and second film connection areas (12a, 12b) of the embossed film composite (10) and/or on the first conductor track (5a) and the second power terminal (9b),
d) arranging the embossed film composite (10) on the substrate (2) such that a first portion (15a) of the adhesive (15) is in mechanical contact with the first film connection region (12a) and the first conductor track (5a) and a second portion (15b) of the adhesive (15) is in mechanical contact with the second film connection region (12b) and the second power terminal (9b),
e) hardening the adhesive (15).
2. Method according to claim 1, having the following process steps:
f) at least one cavity (22) arranged between the membrane composite (10) and the power semiconductor component (2) is filled with a non-conductive potting compound.
3. The method according to any one of the preceding claims, characterized in that the embossed film composite (10) has a third film (13) which is electrically conductive, which is structured to form film conductor tracks (13a, 13b), and the first film (11) is arranged between the second and third films (12, 13).
4. The method according to claim 3, characterized in that the embossed film composite (10) has conductive vias (14) through the first film (11) which connect the first and second film connection regions (12a, 12b) to the third film (13) in a conductive manner.
5. Method according to any one of claims 1 to 2, characterized in that the embossed film composite (10) is embossed such that, when carrying out the processing step d), the embossed film composite (10) aligned with a surrounding area (U) of an edge (7') of the power semiconductor component (7) has an arched profile above the surrounding area (U), wherein an apex (SP) of an arch formed by the arched profile (B) is arranged on that side (10a) of the film composite (10) facing the substrate (3) in the normal direction (N) of the first film connection area (12a) at a third height level (H3) which is higher than the second height level (H2).
6. The method according to claim 5, characterized in that in the processing step b) for providing the embossed film composite (10), a method for producing the embossed film composite (10) is carried out, which method has the following processing steps:
b1) arranging an unembossed film composite (10') between a first and a second die (16, 17) of a press (20),
b2) -embossing the unembossed film composite (10 ') by performing a relative movement of the first and second stamps (16, 17) towards each other such that the first and second stamps (16, 17) are pressed against the unembossed film composite (10 ') thereby forming the embossed film composite (10) from the unembossed film composite (10 '), wherein the first and/or second stamp (16, 17) has a geometry such that after the embossing the first film connection region (12a) is arranged at a first height level (H1) and the second film connection region (12b) is arranged at a second height level (H2) higher than the first height level (H1) in a normal direction (N) of the first film connection region (12a),
b3) removing the embossed film composite (10) from the press (20).
7. Method according to claim 6, characterized in that in process step B2), the first and/or the second stamp (16, 17) has a geometry such that, when process step d) is performed, the embossed film composite (10) aligned with a surrounding area (U) of the edge (7') of the power semiconductor component (7) has an arched profile above the surrounding area (U), wherein an apex (SP) of an arch formed by the arched profile (B) is arranged on that side (10a) of the film composite (10) facing the substrate (3) in the normal direction (N) of the first film connection area (12a) at a third height level (H3) which is higher than the second height level (H2).
8. Method according to claim 6, characterized in that the first stamp (16) has a rigid geometry and the second stamp (17) is formed of an elastic material, or the second stamp (17) has a rigid geometry and the first stamp (16) is formed of an elastic material, or the first and second stamps (16, 17) have a rigid geometry, wherein the first and second stamps (16, 17) have a convex and concave geometry with respect to each other.
9. A power semiconductor module having: a substrate (3) having a non-conductive insulating layer (4) on a first main side (4a) of which a first and a second conductor track (5a, 5b) are arranged; and a power semiconductor component (7) which is arranged on the second conductor track (5b) of the substrate (3) and has a first power terminal (9a) on a first main side (8a) of the power semiconductor component facing the second conductor track (5b) and a second power terminal (9b) on a second main side (8b) of the power semiconductor component facing away from the second conductor track (5b), wherein the first power terminal (9a) is connected to the second conductor track (5b) in an electrically conductive manner; and the power semiconductor module has an embossed film composite (10), the embossed film composite (10) having a first film (11) which is electrically non-conductive and a second, electrically conductive, structured film (12) which is arranged on the first film, wherein the second film (12) is structured such that the film has a first film connection region (12a) and a second film connection region (12b) which is arranged separately from the first film connection region (12a), wherein the embossed film composite (10) is embossed such that, in a normal direction (N) of the first film connection region (12a), the first film connection region (12a) is arranged at a first height level (H1) and the second film connection region (12b) is arranged at a second height level (H2) which is higher than the first height level (H1); and having an electrically conductive hardened adhesive (15), wherein a first portion (15a) of the adhesive (15) connects the first film connection region (12a) to the first conductor track (5a) in an electrically conductive manner, and a second portion (15b) of the adhesive (15) connects the film connection region (12b) to the second power terminal (9b) in an electrically conductive manner.
CN202010423273.2A 2019-05-23 2020-05-19 Method for producing a power semiconductor module and power semiconductor module Pending CN111987005A (en)

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DE10056854A1 (en) * 2000-11-16 2002-05-23 Rafi Gmbh & Co Kg Elektrotechn Touch-contact switch has switch surface defined between 2 plastics plates provided with electrically-conductive deformable coatings on their opposing surfaces
DE102004041868B3 (en) * 2004-08-27 2006-03-02 Leonhard Kurz Gmbh & Co. Kg Transfer film, its use and process for the production of decorated plastic articles
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DE102013104949B3 (en) * 2013-05-14 2014-04-24 Semikron Elektronik Gmbh & Co. Kg Power electronic switching device and arrangement hereby
DE102015116165A1 (en) * 2015-09-24 2017-03-30 Semikron Elektronik Gmbh & Co. Kg Method for producing a power electronic switching device and power electronic switching device
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