CN111970008B - Turbo code decoder and soft input and soft output method, device and storage medium - Google Patents
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- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
Abstract
The application discloses a turbo code decoder, a soft input and soft output method, an electronic device and a computer readable storage medium, wherein the turbo code decoder comprises: the system buffer is used for receiving a system bit signal and a first address signal output by the bidirectional interleaver; the first parity check buffer is used for receiving the first error detection bit signal and the second address signal output by the bidirectional interleaver; the second parity check buffer is used for receiving a second error detection bit signal and a second address signal; the output signals of the first parity check buffer and the second parity check buffer are selected and output to the soft input soft output unit after passing through the data selector; the output signal of the system buffer and the decoding signal output by the bidirectional interleaver are added and then respectively sent to the first shift register and the soft input and soft output unit; the output signals of the first shift register and the soft input and soft output unit are subjected to difference and then sent to the threshold comparator. The application effectively reduces the product cost and improves the economic benefit of the product.
Description
Technical Field
The present disclosure relates to the field of data encoding and decoding technologies, and in particular, to a turbo decoder, a soft-input and soft-output method, an electronic device, and a computer-readable storage medium.
Background
In general, there are many methods for data transmission in electronic products and different communication protocols, wherein many encoding and decoding functions are used, and different encoding and decoding methods are implemented by different algorithms, so that the improvement and introduction of the algorithm method has become an important research direction.
Turbo codes (Turbo codes) are a kind of forward error correction coding technique in information theory. Turbo codes are the first realistic and feasible codes which can approach the Shannon limit, have excellent performance under the condition of low signal to noise ratio, and are widely applied to the fields of 3G/4G mobile communication (such as UMTS and LTE), deep space satellite communication and the like. The turbo code decoding process is iterated through a feedback loop, which is known for its operation similar to that of a turbocharger in an internal combustion engine.
Fig. 1 is a structural framework diagram of a turbo decoder used in the related art. The turbo decoder shown In fig. 1 mainly includes two SISO units (Soft-In Soft-Out ), an interleaver (interleaver) and an inverse interleaver (de-interleaver). The decoding end uses the recursive idea to repeatedly decode the bit data decoded by two SISO units, thereby achieving the purpose of reducing the error probability (BER) of the decoded bit.
The information decoded by SISO1 is encoded information that has not been processed by the interleaver (systematic is recovered by the interleaver at the encoding end and the deinterleaver at the decoding end), and the information decoded by SISO2 is processed by the interleaver. It is thus ensured that the order of the information decoded by the two SISO units is different. The soft output of SISO2 after decoding is processed by reverse interleaver and then recursion to SISO1, when the recursion times reaches the default upper limit, the output of SISO2 is the decoded output. However, since the cost of SISO units is high, the above turbo decoder has undoubtedly a high product cost due to the need to use two SISO units.
In view of the above, it is an important need for those skilled in the art to provide a solution to the above technical problems.
Disclosure of Invention
An object of the present application is to provide a turbo code decoder, a soft input and soft output method, an electronic device, and a computer readable storage medium, so as to effectively implement turbo code decoding and reduce product costs.
To solve the above technical problem, in a first aspect, the present application discloses a turbo decoder, including a bidirectional interleaver, a systematic buffer, a first parity buffer, a second parity buffer, a soft input soft output unit, a first shift register, and a threshold comparator;
The system buffer is used for receiving a system bit signal and a first address signal output by the bidirectional interleaver;
the first parity check buffer is used for receiving a first error detection bit signal and a second address signal output by the bidirectional interleaver; the second parity check buffer is used for receiving a second error detection bit signal and the second address signal; the output signals of the first parity check buffer and the second parity check buffer are selected and output to the soft input and soft output unit after passing through a data selector;
the output signal of the system buffer and the decoding signal output by the bidirectional interleaver are added and then are respectively sent to the first shift register and the soft input soft output unit; the output signals of the first shift register and the soft input and soft output unit are subjected to difference and then sent to the threshold comparator; the threshold comparator is used for outputting an input signal larger than a preset threshold to the bidirectional interleaver, so that the bidirectional interleaver performs forward and reverse interleaving and outputs the decoding signal.
Optionally, the bidirectional interleaver comprises an address generator, a second shift register, a first memory, a second memory;
A first output end of the address generator is connected with the system buffer and used for outputting the first address signal; a second output terminal of the address generator is connected to the first parity buffer and the second parity buffer, respectively, for outputting the second address signal;
a third output end of the address generator is connected with the second shift register and used for outputting a third address signal; the third address signal and the output signal of the second shift register are selected and output to the first memory after passing through a data selector; the third address signal and the output signal of the second shift register are selected and output to the second memory after passing through a data selector; the input ends of the first memory and the second memory are both connected with the output end of the threshold comparator, and output signals of the first memory and the second memory are selected and output after passing through the data selector so as to serve as the decoding signals.
Optionally, the soft-input soft-output unit is implemented based on a soft-output maintenance ratio algorithm.
Optionally, the soft input and soft output unit includes a first branch path value recording unit, a first addition comparison and selection unit, a survivor path unit, a first input first-out queue, a second branch path value recording unit, a second addition comparison and selection unit, a path comparison unit, and a reliability value measurement unit, which are connected in sequence;
The first branch path value recording unit is connected with the input end of the first-in first-out queue in parallel and is used as the data input end of the soft input and soft output unit; the maximum similar state point signal output by the survivor path unit and the decision bit output by the second addition comparison selection unit are both sent to the path comparison unit, so that the path comparison unit outputs a hard output signal;
the path metering difference value output by the second addition comparison selection unit is selected as a reliability value to be output after passing through the data selector; so that the reliability value measuring unit calculates and outputs a soft output signal according to the reliability value and the associated bit output by the path comparing unit.
In a second aspect, the present application also discloses a soft input and soft output method, applied to the soft input and soft output unit described above, including:
determining a path value of each branch path;
determining a survival path and a competition path in the branch paths;
taking the path value of the survival path as a current path value, and storing a decision bit of the current path value;
outputting a hard output signal based on the current path value and the decision bit;
determining a confidence value of the current path value based on a path difference value of the surviving path and the competing path;
Outputting a soft output signal based on the confidence value.
Optionally, after the determining the surviving path and the competing path in the branch paths and before the outputting the soft output signal based on the confidence value, further comprising:
comparing the binary decoding results of the surviving path and the competing path;
and if the results are different, updating the credibility value.
In a third aspect, the present application also discloses an electronic device, including:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of any of the soft-input soft-output methods described above.
In a fourth aspect, the present application further discloses a computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, is adapted to implement the steps of any one of the soft-input and soft-output methods described above.
The turbo code decoder comprises a bidirectional interleaver, a system buffer, a first parity check buffer, a second parity check buffer, a soft input soft output unit, a first shift register and a threshold comparator; the system buffer is used for receiving a system bit signal and a first address signal output by the bidirectional interleaver; the first parity check buffer is used for receiving a first error detection bit signal and a second address signal output by the bidirectional interleaver; the second parity check buffer is used for receiving a second error detection bit signal and the second address signal; the output signals of the first parity check buffer and the second parity check buffer are selected and output to the soft input soft output unit after passing through a data selector; the output signal of the system buffer and the decoding signal output by the bidirectional interleaver are added and then are respectively sent to the first shift register and the soft input soft output unit; the output signals of the first shift register and the soft input and soft output unit are subjected to difference and then sent to the threshold comparator; the threshold comparator is used for outputting an input signal larger than a preset threshold to the bidirectional interleaver, so that the bidirectional interleaver performs forward and reverse interleaving and outputs the decoding signal.
The turbo code decoder, the soft input and soft output method, the electronic device and the computer readable storage medium provided by the application have the advantages that: the method and the device effectively improve the time utilization rate of a single soft input soft output unit based on the improved circuit structure and the use of other related devices, thereby effectively reducing the use number of the soft input soft output units in the turbo code decoder under the condition of ensuring the same decoding effect and decoding speed, further effectively reducing the product cost and improving the economic benefit of products.
Drawings
In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the drawings used in the description of the prior art and the embodiments of the present application will be briefly described below. Of course, the following description of the drawings related to the embodiments of the present application is only a part of the embodiments of the present application, and it will be apparent to those skilled in the art that other drawings may be obtained from the provided drawings without any creative effort, and the obtained other drawings also belong to the protection scope of the present application.
FIG. 1 is a schematic diagram of a turbo decoder in the related art;
FIG. 2 is a block diagram of a turbo decoder according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of another exemplary turbo decoder according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a soft input soft output unit according to an embodiment of the present disclosure;
FIG. 5 is a flow chart of a soft output and hard output method disclosed in an embodiment of the present application;
fig. 6 is a block diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
The core of the present application is to provide a turbo code decoder and soft input and soft output method, an electronic device and a computer readable storage medium for effectively implementing turbo code decoding and reducing product cost.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In general, there are many methods for data transmission in electronic products and different communication protocols, in which many encoding and decoding functions are used, and different encoding and decoding methods are implemented by different algorithms, so that the improvement and introduction of the algorithm method has become an important research direction.
Turbo codes (Turbo codes) are a kind of forward error correction coding technique in information theory. Turbo codes are the first realistic and feasible codes which can approach the Shannon limit, have excellent performance under the condition of low signal to noise ratio, and are widely applied to the fields of 3G/4G mobile communication (such as UMTS and LTE), deep space satellite communication and the like. The turbo code decoding process is iterated through a feedback loop, which is known for its operation similar to a turbocharger in an internal combustion engine.
Fig. 1 is a structural framework diagram of a turbo decoder used in the related art. The turbo decoder shown In fig. 1 mainly includes two SISOs (Soft-In Soft-Out), an interleaver (interleaver) and an inverse interleaver (de-interleaver). The decoding end uses the recursive idea to repeatedly decode the bit data decoded by two SISO units, thereby achieving the purpose of reducing the error probability (BER) of the decoded bit.
The information decoded by SISO1 is coded information that has not been interleaved (systematic interleaved by the interleaver at the coding end and the deinterleaver at the decoding end, which has been restored), and the information decoded by SISO2 is processed by the interleaver. It can thus be guaranteed that the order of the information decoded by the two SISOs is different. The soft output of SISO2 after decoding is processed by reverse interleaver and recursion to SISO1, when the recursion times reach the default upper limit, the output of SISO2 is the decoding output. However, the turbo decoder described above has undoubtedly a high production cost due to the need to use two SISOs because of their high cost. In view of this, the present application provides a technical solution to effectively solve the above problems.
Referring to fig. 2, an embodiment of the present application discloses a turbo decoder, which mainly includes a bidirectional interleaver 100, a systematic buffer 200, a first parity buffer 300, a second parity buffer 400, a soft input soft output unit 500, a first shift register 600, and a threshold comparator 700;
the system buffer 200 is used for receiving a system bit signal ys and a first address signal addr _1 output by the bidirectional interleaver 100;
The first parity buffer 300 is used for receiving the first error detection bit signal yp1 and the second address signal addr _2 output by the bi-directional interleaver 100; the second parity buffer 400 is used for receiving a second error detection bit signal yp2 and a second address signal addr _ 2; the output signals of the first parity buffer 300 and the second parity buffer 400 pass through the data selector and are selected and output to the soft input soft output unit 500;
the output signal of the system buffer 200 is added with the decoded signal output by the bi-directional interleaver 100 and then sent to the first shift register 600 and the soft input soft output unit 500; the output signals of the first shift register 600 and the soft input/soft output unit 500 are subtracted and then sent to the threshold comparator 700; the threshold comparator 700 is configured to output an input signal greater than a preset threshold to the interleaver 100, so that the interleaver 100 performs forward and backward interleaving to output a decoded signal.
It should be noted that, when the soft input soft output unit 500 is used for turbo decoding, the turbo decoder with the structure provided by the present application only needs to use one SISO, and does not need excessive product cost consumption. According to the hybrid trace-back scheme, the SISO unit used in the present application can achieve faster path search, and the memory capacity requirement of the storage path is reduced by 70% compared to the conventional method.
It is understood by those skilled in the art that in the conventional turbo decoder having the structure shown in fig. 1, the interleaver or the deinterleaver must wait for all data to be interleaved before it is activated, i.e., wait until the decoding of the SISO of the previous stage is completed before the interleaved data can be sent to the SISO of the next stage. Therefore, only one SISO can work in the same time, and the other SISO waits for data, so that the time utilization rate of the SISO hardware is only 50%, and the hardware cost and the hardware layout space are wasted. The circuit structure of the decoder is adjusted, and low-cost devices such as a system buffer, a parity check buffer and the like are used cooperatively, so that the SISO can realize 100% time utilization rate, and the turbo code decoding can be completed under the condition of only using one SISO; and the decoding speed is not affected at all.
Therefore, the turbo code decoder disclosed in the embodiment of the present application effectively improves the time utilization rate of a single soft input/soft output unit based on the improved circuit structure and the use of other related devices, so that the number of soft input/soft output units in the turbo code decoder can be effectively reduced under the condition of ensuring the same decoding effect and decoding speed, the product cost is effectively reduced, and the product economic benefit is improved.
Referring to fig. 3, fig. 3 is a schematic diagram of another turbo decoder disclosed in the embodiment of the present application.
Based on the above, in the turbo decoder disclosed in the embodiment of the present application, in a specific implementation, the bidirectional interleaver 100 includes an address generator 101, a second shift register 102, a first memory 103, and a second memory 104;
a first output terminal of the address generator 101 is connected to the system buffer 200, and is configured to output a first address signal addr _ 1; a second output terminal of the address generator 101 is connected to the first parity buffer 300 and the second parity buffer 400, respectively, for outputting a second address signal addr _ 2;
a third output end of the address generator 101 is connected to the second shift register 102, and is configured to output a third address signal addr _ 3; the third address signal addr _3 and the output signal of the second shift register 102 are selected and output to the first memory 103 after passing through the data selector; the third address signal addr _3 and the output signal of the second shift register 102 are selected and output to the second memory 104 after passing through the data selector; the input ends of the first memory 103 and the second memory 104 are both connected with the output end of the threshold comparator 700, and the output signals of the first memory 103 and the second memory 104 are selected and output after passing through the data selector so as to be used as decoding signals.
Based on the above, in a specific implementation, the turbo code decoder disclosed in the embodiment of the present application uses Soft input Soft Output units, i.e., SISOs, which are specifically implemented based on Soft Output Viterbi decoding algorithm (Soft Output Viterbi decoding algorithm), i.e., SOVDA algorithm.
Specifically, in the architecture of SOVA, in addition to using Trace Back (TB) to reconstruct a survivor path (survivor path), it is necessary to reconstruct a competing path (competing path) of all state points (states) at each Time point (Time step) and update the reliability value of each state point on the competing path.
That is, the process of SISO outputting may roughly include two processes: a first process of calculating a Maximum Likelihood Path (MLP) and a Maximum Likelihood State point (MLS) existing in the Maximum Likelihood Path at each time point; and a second process of calculating and updating the reliability value.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a soft input and soft output unit 500 according to an embodiment of the present disclosure.
On the basis of the above, in a specific implementation manner of the turbo decoder disclosed in the embodiments of the present application, the soft input soft output unit 500 includes a first branch path score unit BMU1, a first addition comparison selection unit acu 1, and a survivor path unit SMU, which are connected in sequence, and a first in first out queue FIFO, a second branch path score unit BMU2, a second addition comparison selection unit acu 2, and a path comparison unit PCU, which are connected in sequence, and a confidence value measurement unit RMU;
Wherein, the first Branch path memory Unit (Branch Metric Unit) BMU1 is connected in parallel with the input end of the FIFO as the data input end of the soft input soft output Unit 500; the maximum similar state point output by the survivor Path Unit (Surviving Path Memory Unit) SMU and the Decision bit (Decision bit) output by the second addition Comparison selection Unit ACSU2 are both sent to the Path Comparison Unit (Path Comparison Unit) PCU, so that the Path Comparison Unit PCU outputs a hard output signal;
the Path metric difference (Path metric difference) output by the second addition comparison selection unit ACSU2 is selected as a confidence value output after passing through the data selector; so that the Reliability Value measurement Unit (Reliability Measure Unit) RMU determines and outputs a soft output signal depending on the Reliability Value (Reliability Value) and the associated bit (relocation bit) output by the path comparison Unit PCU.
Specifically, in the first process of the SOVDA algorithm, the survivor path unit SMU is used to calculate the maximum similarity path and generate the maximum similarity state point. In the second process, the path comparing Unit PCU generates a dependent bit (relocation bit) according to the Decision bit (Decision bit) provided by the add-compare-select Unit ACSU1, and sends the dependent bit (relocation bit) to the Reliability Measuring Unit (RMU) for processing, so as to calculate and generate a Soft-Output value (Soft-Output). The reliability measuring unit stores the initial calculated reliability value, determines whether to update the reliability value according to the associated bit, and outputs the final reliability value as a soft output value.
Further, as a specific embodiment, the present embodiment does not update the reliability values of all the surviving paths, but only calculates and updates the reliability value of the surviving path updated last, so as to further improve the calculation efficiency. In fact, whether the confidence values of other non-last updated surviving paths are updated or not does not affect the final output result, and this embodiment eliminates these redundant actions, thereby increasing the processing rate.
Suitably, the application also discloses a method for soft-input and soft-output of the soft-input and soft-output unit. Specifically, referring to fig. 5, the method mainly includes:
s11: a path value for each branch path is determined.
S12: a surviving path and a competing path of the branching paths are determined.
S13: the path value of the surviving path is taken as the current path value, and the decision bit of the current path value is stored.
S14: a hard output signal is output based on the current path value and the decision bit.
S15: and determining the reliability value of the current path value based on the path difference value of the survival path and the competition path.
S16: outputting a soft output signal based on the confidence value.
On the basis of the foregoing, as a specific embodiment, in the method for soft-input soft-output by a soft-input soft-output unit to perform soft-output hard-output, after determining a surviving path and a contending path in a branch path, and before outputting a soft-output signal based on a reliability value, the method further includes:
Comparing the binary decoding results of the survival path and the competition path;
and if the results are different, updating the reliability value.
The details of the soft output and hard output method can be described in detail with reference to the structure of the soft output and hard output in the turbo decoder, and will not be described herein again.
Further, referring to fig. 5, an embodiment of the present application discloses an electronic device, including:
a memory 21 for storing a computer program;
a processor 22 for executing the computer program to implement the steps of any of the soft-input soft-output methods described above.
Further, the present application discloses a computer readable storage medium, in which a computer program is stored, and the computer program is used for implementing the steps of any one of the soft input and soft output methods described above when being executed by a processor.
For the details of the electronic device and the computer-readable storage medium, reference may be made to the foregoing detailed description of the soft input and soft output method, and further description thereof will be omitted.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the equipment disclosed by the embodiment, the description is relatively simple because the equipment corresponds to the method disclosed by the embodiment, and the relevant parts can be referred to the method part for description.
It is further noted that, throughout this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The technical solutions provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall into the protection scope of the present application.
Claims (8)
1. A turbo code decoder is characterized by comprising a bidirectional interleaver, a system buffer, a first parity check buffer, a second parity check buffer, a soft input soft output unit, a first shift register and a threshold comparator;
the system buffer is used for receiving a system bit signal and a first address signal output by the bidirectional interleaver;
the first parity check buffer is used for receiving a first error detection bit signal and a second address signal output by the bidirectional interleaver; the second parity check buffer is used for receiving a second error detection bit signal and the second address signal; the output signals of the first parity check buffer and the second parity check buffer are selected and output to the soft input soft output unit after passing through a data selector;
the output signal of the system buffer and the decoding signal output by the bidirectional interleaver are added and then are respectively sent to the first shift register and the soft input soft output unit; the output signals of the first shift register and the soft input and soft output unit are subjected to difference and then sent to the threshold comparator; the threshold comparator is used for outputting an input signal larger than a preset threshold to the bidirectional interleaver, so that the bidirectional interleaver performs forward and reverse interleaving and outputs the decoding signal.
2. The turbo decoder of claim 1, wherein the bidirectional interleaver comprises an address generator, a second shift register, a first memory, a second memory;
a first output end of the address generator is connected with the system buffer and used for outputting the first address signal; a second output terminal of the address generator is connected to the first parity buffer and the second parity buffer, respectively, for outputting the second address signal;
a third output end of the address generator is connected with the second shift register and used for outputting a third address signal; the third address signal and the output signal of the second shift register are selected and output to the first memory after passing through a data selector; the third address signal and the output signal of the second shift register are selected and output to the second memory after passing through a data selector; the input ends of the first memory and the second memory are both connected with the output end of the threshold comparator, and output signals of the first memory and the second memory are selected and output after passing through the data selector so as to serve as the decoding signals.
3. Turbo code decoder according to claim 1 or 2, wherein said soft input soft output unit is implemented based on a soft output maintenance ratio algorithm.
4. The turbo code decoder of claim 3, wherein the soft input soft output unit comprises a first branch path score unit, a first addition comparison selection unit and a survivor path unit which are connected in sequence, and a first-in-first-out queue, a second branch path score unit, a second addition comparison selection unit and a path comparison unit which are connected in sequence, and a confidence value measurement unit;
the first branch path value recording unit is connected in parallel with the input end of the first-in first-out queue and is used as the data input end of the soft input and soft output unit; the maximum similar state point signal output by the survivor path unit and the decision bit output by the second addition comparison selection unit are both sent to the path comparison unit, so that the path comparison unit outputs a hard output signal;
the path metering difference value output by the second addition comparison selection unit is selected as a reliability value to be output after passing through the data selector; so that the reliability value measuring unit calculates and outputs a soft output signal according to the reliability value and the associated bit output by the path comparing unit.
5. A soft-input soft-output method applied to the soft-input soft-output unit of claim 1, comprising:
determining a path value of each branch path;
determining a survival path and a competition path in the branch paths;
taking the path value of the survival path as a current path value, and storing a decision bit of the current path value;
outputting a hard output signal based on the current path value and the decision bit;
determining a confidence value of the current path value based on a path difference value of the surviving path and the competing path;
outputting a soft output signal based on the confidence value.
6. A soft-input soft-output method according to claim 5, further comprising, after determining surviving and competing ones of the branch paths and before outputting a soft-output signal based on the confidence value:
comparing the binary decoding results of the surviving path and the competing path;
and if the results are different, updating the reliability value.
7. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the soft-input soft-output method as claimed in claim 5 or 6.
8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the soft-input soft-output method according to claim 4 or 5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010887260.0A CN111970008B (en) | 2020-08-28 | 2020-08-28 | Turbo code decoder and soft input and soft output method, device and storage medium |
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| CN1332905A (en) * | 1998-12-31 | 2002-01-23 | 三星电子株式会社 | An iterative decoder and iterative decoding method for communication system |
| CN1494770A (en) * | 2001-02-28 | 2004-05-05 | �����ɷ� | Interleaver for TURBO decoder |
| CN102034555A (en) * | 2011-01-19 | 2011-04-27 | 哈尔滨工业大学 | On-line error correcting device for fault by parity check code and method thereof |
| CN102130696A (en) * | 2010-01-14 | 2011-07-20 | 联发科技股份有限公司 | Interleaving/de-interleaving method, soft-in/soft-out decoding method and error correction code encoder and decoder utilizing the same |
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| CN1332905A (en) * | 1998-12-31 | 2002-01-23 | 三星电子株式会社 | An iterative decoder and iterative decoding method for communication system |
| CN1494770A (en) * | 2001-02-28 | 2004-05-05 | �����ɷ� | Interleaver for TURBO decoder |
| CN102130696A (en) * | 2010-01-14 | 2011-07-20 | 联发科技股份有限公司 | Interleaving/de-interleaving method, soft-in/soft-out decoding method and error correction code encoder and decoder utilizing the same |
| CN102034555A (en) * | 2011-01-19 | 2011-04-27 | 哈尔滨工业大学 | On-line error correcting device for fault by parity check code and method thereof |
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