CN111968954B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN111968954B CN111968954B CN202010879913.0A CN202010879913A CN111968954B CN 111968954 B CN111968954 B CN 111968954B CN 202010879913 A CN202010879913 A CN 202010879913A CN 111968954 B CN111968954 B CN 111968954B
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 188
- 239000002184 metal Substances 0.000 claims abstract description 188
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof.A groove isolation ring is formed in a pad area on the back side of a first wafer and comprises a first metal layer and a first insulating material layer; forming an insulating medium layer on the back surface of the first wafer and the groove isolation ring; forming a through hole plug structure in the bonding pad area on the back surface of the first wafer, wherein the through hole plug structure is surrounded by the groove isolation ring; and forming a bonding pad on the insulating medium layer, wherein the bottom of the bonding pad is electrically connected with the top of the through hole plug structure, so that the total parasitic capacitance of the device can be reduced while the subsequent bonding pad process is realized, and the performance of the semiconductor device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor device and a method for fabricating the same.
Background
For semiconductor technology, parasitic capacitance has been one of the limiting factors for some device performance enhancements. Particularly, for a semiconductor device that needs to operate at a high frequency, the parasitic Capacitance (Pad CIO) of the metal plate structure of the Input/Output (I/O) may seriously affect the transmission rate.
For the subsequent pad process, a through silicon via (TSC) structure and a process are introduced on the back surface of the wafer, however, a corresponding parasitic capacitance is inevitably generated among the silicon substrate, the tsv structure and the pad on the top of the tsv structure, and further the parasitic capacitance of the metal plate structure at the I/O end of the optical device is increased, thereby seriously affecting the signal transmission rate at the I/O end.
Taking optical devices developed by applying 3D IC (three-dimensional integrated circuit package) technology, such as CMOS image sensors and 3D Depth sensors (3D Depth sensors), for example, the silicon substrate thickness of pixel wafers has reached a range from several micrometers to tens of micrometers in order to satisfy absorption of light waves of different frequencies or wavelengths. Then, with the increasing thickness of the silicon substrate of the pixel wafer, in order to implement a subsequent pad process after the pixel wafer and the logic wafer are bonded, so that the pad on the back side of the pixel wafer is electrically connected to the conductive plug and the metal interconnection structure on the front side of the pixel wafer, and the introduction of the through silicon via structure and process may generate corresponding parasitic capacitances among the silicon substrate, the through silicon via structure, and the pad on the top of the through silicon via structure, thereby causing the parasitic capacitance of the metal plate structure at the I/O end of the optical devices to increase, and thus seriously affecting the signal transmission rate at the I/O end thereof.
Therefore, how to reduce the total parasitic capacitance of the semiconductor device to improve the device performance while implementing the subsequent bonding pad process is a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which can reduce the total parasitic capacitance of the semiconductor device while realizing the subsequent bonding pad process, thereby improving the performance of the semiconductor device.
To achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising:
providing a first wafer with a pad area on the back surface, wherein a first device layer is formed in the first wafer, and a metal interconnection structure is arranged in the first device layer;
forming a trench isolation ring in the pad area on the back side of the first wafer, wherein the trench isolation ring comprises a first metal layer and a first insulating material layer, the first insulating material layer is located on the side wall and the bottom surface of the annular trench of the pad area on the back side of the first wafer, and the annular trench is filled with the first metal layer;
forming an insulating medium layer on the back surface of the first wafer and the groove isolation ring;
forming a through hole plug structure in a pad area on the back side of the first wafer, wherein the through hole plug structure penetrates through the insulating medium layer and the first wafer and is electrically connected with the metal interconnection structure in the first device layer, and the through hole plug structure is surrounded by the trench isolation ring; and the number of the first and second groups,
and forming a bonding pad on the insulating medium layer, wherein the bottom of the bonding pad is electrically connected with the top of the through hole plug structure.
Optionally, the step of forming the trench isolation ring includes:
etching the back surface of the first wafer until the first device layer is exposed, so as to form an annular groove in the pad area;
forming a first insulating material layer to cover the side wall and the bottom surface of the annular groove;
depositing a first metal layer on the first insulating material layer, wherein the first metal layer at least fills the annular groove; and
and carrying out top planarization or back etching on the first metal layer and the first insulating material layer, and removing redundant first metal layer and first insulating material layer on the back surface of the first wafer around the annular groove so as to form the groove isolation ring in the annular groove.
Optionally, the back surface of the first wafer further has a pixel region; and forming a trench isolation structure in the pixel region on the back surface of the first wafer while forming the trench isolation ring in the pad region on the back surface of the first wafer, wherein the depth of the bottom of the trench isolation structure is the same as that of the bottom of the trench isolation ring.
Optionally, an adhesive layer is further sandwiched between the first insulating material layer and the first metal layer; the material of the first insulating material layer comprises at least one of silicon oxide and a high-K medium with a dielectric constant K larger than 3.9, the material of the first metal layer comprises at least one of tungsten, aluminum, copper, silver and gold, and the material of the bonding layer comprises at least one of titanium, tantalum and metal nitride.
Optionally, the manufacturing method of the semiconductor device further includes forming a metal grid layer above the trench isolation structure, and electrically connecting or insulating between the bottom of the metal grid layer and the top of the trench isolation structure.
Optionally, after the bonding pad is formed, a passivation layer is further formed to cover the surface of the insulating dielectric layer, and the passivation layer exposes at least a portion of the top surface of the bonding pad.
Optionally, before forming the trench isolation ring, bonding layers are respectively formed on the surfaces of the first wafer and a second wafer, and then the first wafer is bonded to the second wafer through the bonding layers.
Optionally, after the first wafer is bonded to the second wafer and before the trench isolation ring is formed, the back surface of the first wafer is thinned.
The present invention also provides a semiconductor device comprising:
the semiconductor device comprises a first wafer, a second wafer and a third wafer, wherein the back surface of the first wafer is provided with a bonding pad area, a first device layer is formed in the first wafer, and a metal interconnection structure is arranged in the first device layer;
the groove isolation ring is formed in the pad area of the first wafer and comprises a first metal layer and a first insulating material layer, wherein the first insulating material layer is positioned on the side wall and the bottom surface of the annular groove of the pad area on the back side of the first wafer, and the annular groove is filled with the first metal layer;
the insulating medium layer is formed on the back surface of the first wafer and covers the groove isolation ring;
the through hole plug structure is formed in a bonding pad area on the back surface of the first wafer, penetrates through the insulating medium layer and the first wafer, is electrically connected with the metal interconnection structure in the first device layer, and is surrounded by the groove isolation ring; and (c) a second step of,
and the bonding pad is formed on the insulating medium layer, and the bottom of the bonding pad is electrically connected with the top of the through hole plug structure.
Optionally, the back surface of the first wafer further has a pixel region; the semiconductor device further comprises a trench isolation structure formed in the pixel region on the back side of the first wafer, and the depth of the bottom of the trench isolation structure is the same as that of the bottom of the trench isolation ring.
Optionally, an adhesive layer is further sandwiched between the first insulating material layer and the first metal layer; the through hole plug structure comprises a second insulating material layer formed on the side wall of the through hole and a second metal layer filled in the through hole, and the bottom of the second metal layer is electrically connected with the metal interconnection structure in the first device layer; the first insulating material layer and the second insulating material layer are made of at least one of silicon oxide and a high-K medium with a dielectric constant K larger than 3.9, the first metal layer and the second metal layer are made of at least one of tungsten, aluminum, copper, silver and gold, and the bonding layer is made of at least one of titanium, tantalum and metal nitride.
Optionally, the semiconductor device further includes a metal grid layer located in the pixel region, the metal grid layer is formed above the trench isolation structure, and the bottom of the metal grid layer is electrically connected or insulated with the top of the trench isolation structure.
Optionally, the semiconductor device further includes a passivation layer covering the surface of the insulating dielectric layer, and the passivation layer exposes at least a portion of the top surface of the pad.
Optionally, the semiconductor device further includes a second wafer bonded to the first wafer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the manufacturing method of the semiconductor device comprises the steps that a groove isolation ring is formed in a pad area on the back side of a first wafer, and the groove isolation ring comprises a first metal layer and a first insulating material layer; forming an insulating medium layer on the back surface of the first wafer and the groove isolation ring; forming a through hole plug structure in the pad area on the back side of the first wafer, wherein the through hole plug structure is surrounded by the groove isolation ring; and forming a bonding pad on the insulating medium layer, wherein the bottom of the bonding pad is electrically connected with the top of the through hole plug structure, so that the total parasitic capacitance of the device can be reduced while the subsequent bonding pad process is realized, and the performance of the semiconductor device is improved.
2. The semiconductor device of the present invention comprises: the groove isolation ring is formed in a bonding pad area of a first wafer and comprises a first metal layer and a first insulating material layer; the insulating medium layer is formed on the back face of the first wafer and covers the groove isolation ring; the through hole plug structure is formed in the bonding pad area on the back side of the first wafer and is surrounded by the groove isolation ring; and the bottom of the bonding pad is electrically connected with the top of the through hole plug structure, so that the total parasitic capacitance of the device can be reduced while the subsequent bonding pad process is realized, and the performance of the semiconductor device is improved.
Drawings
FIG. 1 is a schematic view of a semiconductor device including a through silicon via structure;
FIG. 2 is a schematic illustration of a distribution of through silicon via structures and bonding pads in the semiconductor device shown in FIG. 1 including a through silicon via structure;
fig. 3 is a circuit schematic of parasitic capacitance in the semiconductor device shown in fig. 1 including a through silicon via structure;
fig. 4 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 5a to 5h are device diagrams in the method of manufacturing the semiconductor device shown in fig. 4;
fig. 6 is a schematic top view of a semiconductor device of an embodiment of the invention;
fig. 7 is a circuit diagram illustrating parasitic capacitance in a semiconductor device according to an embodiment of the present invention.
Wherein the reference numerals of figures 1 to 7 are as follows:
11-a first wafer; 110-a first substrate; 111-a first device layer; 112-deep trench isolation structures; 1121-first oxide layer; 1122-first metal layer; 113-via plug configuration; 1131 — a second oxide layer; 1132 — a second metal layer; 114-insulating dielectric layer; 115-conductive plugs; 116-a metal interconnect structure; 117-metal grid layer; 118-a pad; 120-a second substrate; 121-a second device layer; 21-a first wafer; 211-a first device layer; 2111-metal interconnect structure; 2112-conductive plug; 212-trench isolation ring; 2121-a first trench; 2122-first layer of insulating material; 2123-first metal layer; 213-trench isolation structure; 2131-a second groove; 2132-a first layer of insulating material; 2133-a first metal layer; 214-an insulating dielectric layer; 215-via plug configuration; 2151-via; 2152-a second layer of insulating material; 2153-a second metal layer; 216-a pad; 217-metal grid layer; 2171-opening; 218-a passivation layer; 22-a second wafer; 221-second device layer.
Detailed Description
The following will take the structure of a conventional semiconductor device including a through silicon via structure as shown in fig. 1 as an example, and with reference to fig. 2 and fig. 3, describe in detail the defects in the prior art and the principle of the present invention.
Referring to fig. 1, a conventional process for manufacturing a through silicon via structure and a bonding pad (i.e., a metal plate) in 3D IC technology includes:
step S11, providing a first wafer 11 and a second wafer 12, where the first wafer 11 includes a first substrate 110 and a first device layer 111 formed on a front surface of the first substrate 110, the second wafer 12 includes a second substrate 120 and a second device layer 121 formed on a front surface of the second substrate 120, and a bonding layer (not shown) is formed on each of the first device layer 111 and the second device layer 121;
step S12, bonding the first wafer 11 and the second wafer 12 through the bonding layer;
step S13, thinning the first substrate 110 on the back side of the first wafer 11;
in step S14, a plurality of deep trench isolation structures 112 are formed in the first substrate 110 of the pixel region a1 on the back side of the first wafer 11, and the forming steps include: first, performing photolithography and etching on the first substrate 110 on the back side of the first wafer 11 to form a plurality of deep trenches (not shown) in the first substrate 110 in the pixel region a1, then depositing a first oxide layer 1121 on the sidewalls and bottom walls of the deep trenches, then depositing a high-K dielectric layer (not shown) on the first oxide layer 1121, then depositing an adhesive layer (not shown) on the high-K dielectric layer, then depositing a first metal layer 1122 on the adhesive layer, and the deep trenches are filled with the first metal layer 1122, and finally planarizing the top of the first metal layer 1122 until the surface of the first substrate 110 is exposed to form the deep trench isolation structure 112;
in step S15, a via plug structure 113 (i.e., a through silicon via structure) is formed in the first substrate 110 of the pad region B1 on the back side of the first wafer 11, and the forming step includes: firstly, forming an insulating dielectric layer 114 to cover the first substrate 110 on the back of the first wafer 11, and burying the deep trench isolation structure 112 in the insulating dielectric layer 114, then, performing photolithography and etching on the insulating dielectric layer 114 and the first substrate 110 to form a through hole (not shown) located in the insulating dielectric layer 114 and the first substrate 110, the through hole penetrating through the first substrate 110 to expose the top surface of the first device layer 111, then depositing a second oxide layer 1131 on the sidewall of the through hole, then depositing a second metal layer 1132 on the second oxide layer 1131, and the through hole is filled up by the second metal layer 1132, finally, planarizing the top of the second metal layer 1132 until the surface of the insulating dielectric layer 114 is exposed to form a via plug structure 113, and the bottom of the via plug structure 113 is electrically connected with the conductive plug 115 and the metal interconnection structure 116 in the first device layer 111;
step S16, forming a metal grid layer 117 and a pad 118 on the insulating dielectric layer 114, where the metal grid layer 117 is located above each deep trench isolation structure 112, the metal grid layer 117 and the deep trench isolation structures 112 may be electrically connected or may be insulated from each other, and the bottom of the pad 118 covers the top of the via plug structure 113 to be electrically connected to the top of the via plug structure 113, as shown in fig. 2, the bottom of the pad 118 covers 16 via plug structures 113 to be electrically connected to the 16 via plug structures 113.
As is apparent from fig. 1 and fig. 3, in the semiconductor device formed in steps S11 to S16, two parasitic capacitances are formed in the pad region B1, that is, the first parasitic capacitance C1 formed by the first substrate 110, the insulating dielectric layer 114 and the pad 118, and the second parasitic capacitance C2 formed by the first substrate 110, the second oxide layer 1131 and the second metal layer 1132, and the first parasitic capacitance C1 is connected in parallel with the second parasitic capacitance C2, so that the parasitic capacitance of the semiconductor device is the sum of the first parasitic capacitance C1 and the second parasitic capacitance C2, and the parasitic capacitance of the semiconductor device increases. Therefore, in the process of manufacturing a semiconductor device by using the 3D IC technology, the introduction of the through-silicon-via structure and the technology can realize the subsequent bonding pad process after wafer bonding, but leads to an increase in parasitic capacitance.
Based on this, the present invention provides a semiconductor device and a method for manufacturing the same, in which a trench isolation ring structure filled with metal is surrounded on the periphery of each pad 118 to connect a new capacitor in series to the first parasitic capacitor C1 and the second parasitic capacitor C2 connected in parallel, so that the total parasitic capacitance introduced by the subsequent pad process is reduced, thereby not only realizing the subsequent pad process, but also improving the device performance by reducing the total parasitic capacitance of the device.
To make the objects, advantages and features of the present invention more apparent, the semiconductor device and the method for manufacturing the same proposed by the present invention are described in further detail below. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. As used herein, "and/or" means either or both.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, and referring to fig. 4, fig. 4 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, where the method for manufacturing a semiconductor device includes:
step S21, providing a first wafer with a pad area on the back surface, wherein a first device layer is formed on the front surface of the first wafer, and a metal interconnection structure is arranged in the first device layer;
step S22, forming a trench isolation ring in the pad area on the back side of the first wafer, where the trench isolation ring includes a first metal layer and a first insulating material layer, where the first insulating material layer is located on the sidewall and the bottom of the annular trench in the pad area on the back side of the first wafer, and the annular trench is filled with the first metal layer;
step S23, forming an insulating medium layer on the back surface of the first wafer and the trench isolation ring;
step S24, forming a via plug structure in the pad region on the back side of the first wafer, where the via plug structure penetrates through the insulating dielectric layer and the first wafer and is electrically connected to the metal interconnection structure in the first device layer, and the via plug structure is surrounded by the trench isolation ring;
and step S25, forming a pad on the insulating medium layer, wherein the bottom of the pad is electrically connected with the top of the through hole plug structure.
The method for manufacturing the semiconductor device according to the present embodiment is described in more detail with reference to fig. 5a to 7, and fig. 5a to 5h are schematic longitudinal cross-sectional views of the semiconductor device. The embodiment of the invention takes an image sensor applying a 3D IC as an example, but not limited thereto, and the invention can be applied to other subsequent bonding pad processes.
Providing a first wafer 21 with a pad area B2 on the back side, wherein a first device layer 211 is formed on the front side of the first wafer 21, and the first device layer 211 has a metal interconnection structure 2111 therein. The first device layer 211 may further include a conductive plug 2112 located above the metal interconnect structure 2111, and a bottom of the conductive plug 2112 is electrically connected to the metal interconnect structure 2111. The first device layer 211 may also include other functional structures, such as a pixel array, a transistor, or a MEMS microstructure (e.g., a diaphragm, an electrode, etc.).
The first wafer 21 may be a device wafer, for example a pixel wafer comprising an array of pixels of an image sensor, the kind of the first wafer 21 depending on the function of the device to be finally fabricated. The first wafer 21 may be a single-layer wafer structure, or a multi-layer wafer bonded structure, as shown in fig. 5a to 7, the first wafer is a single-layer wafer structure.
The back side of the first wafer 21 further has a pixel area a2, and the pad area B2 is located at the periphery of the pixel area a 2.
A second wafer 22 is provided and the first device layer 211 is bonded to the second wafer 22.
A second device layer 221 may also be formed on the surface of the second wafer 22; before bonding the first device layer 211 to the second wafer 22, bonding layers (not shown) are formed on the surfaces of the first device layer 211 and the second device layer 221, respectively, and bury the first device layer 211 and the second device layer 221 therein, respectively; the first device layer 211 is then bonded to the second device layer 221 through the bonding layer to bond the first device layer 211 to the second wafer 22.
And, after bonding the first device layer 211 to the second wafer 22 and before forming the trench isolation ring 212 in the pad region B2 on the back side of the first wafer 21, thinning the back side of the first wafer 21 so that the substrate thickness on the back side of the first wafer 21 is thinned to a desired thickness.
The second wafer 22 may be a logic wafer, and a CMOS circuit is formed therein; the second device layer 221 may include MOS transistors, resistors, capacitors, metal interconnection structures, and the like. The second wafer 22 may be a single-layer wafer structure or a multi-layer wafer bonded structure. When the first wafer 21 and the second wafer 22 are single-layer wafers, the first wafer 21 and the second wafer 22 may be understood as substrates.
The second wafer 22 may also be a carrier wafer without a device function, and the second device layer 221 is not formed on the second wafer 22, but a bonding layer is directly formed thereon to be bonded with the bonding layer on the first wafer 21.
Forming a trench isolation ring 212 in the pad region B2 on the back side of the first wafer 21, where the trench isolation ring 212 includes a first metal layer and a first insulating material layer, where the first insulating material layer is located on the sidewall and the bottom surface of the annular trench of the pad region B2 on the back side of the first wafer 21, and the first metal layer fills the annular trench.
And, while forming the trench isolation ring 212 in the pad region B2 on the back side of the first wafer 21, a trench isolation structure 213 is also formed in the pixel region a2 on the back side of the first wafer 21, wherein the bottom of the trench isolation structure 213 and the bottom of the trench isolation ring 212 have the same depth.
Referring to fig. 5a to 5b, the step of forming the trench isolation ring 212 and the trench isolation structure 213 includes: first, as shown in fig. 5a, the back surface of the first wafer 21 is etched until the top of the first device layer 211 is exposed, so as to form a first trench 2121 in the pad region B2 and a second trench 2131 in the pixel region a2, where the first trench 2121 is an annular trench, and both the first trench 2121 and the second trench 2131 penetrate through the first wafer 21; then, a first insulating material layer is formed to cover the side walls and the bottom walls of the first groove 2121 and the second groove 2131 and the back surface of the first wafer 21; then, depositing a first metal layer on the first insulating material layer, wherein the first metal layer at least fills the first trench 2121 and the second trench 2131; next, the first metal layer and the first insulating material layer are top planarized or etched back, and excess first metal layer and first insulating material layer on the back surface of the first wafer 21 around the first trench 2121 and the second trench 2131 are removed to form the trench isolation ring 212 in the first trench 2121, and simultaneously form the trench isolation structure 213 in the second trench 2131, the top surfaces of the trench isolation ring 212 and the trench isolation structure 213 are flush, and the top surfaces of the trench isolation ring 212 and the trench isolation structure 213 may be flush with the back surface of the first wafer 21 or higher than the back surface of the first wafer 21. For the sake of convenience of distinction, the first insulating material layer in the first trench 2121 is denoted by reference numeral 2122, the first insulating material layer in the second trench 2131 is denoted by reference numeral 2132, and different filling patterns are adopted; the first metal layer in the first trench 2121 is denoted by 2123, and the first metal layer in the second trench 2131 is denoted by 2133, and different filling patterns are also used for the two. Then, as shown in fig. 5b, the trench isolation ring 212 includes a first insulating material layer 2122 formed on the sidewall and the bottom wall of the first trench 2121 and a first metal layer 2123 filling the first trench 2121, and the trench isolation structure 213 includes a first insulating material layer 2132 formed on the sidewall and the bottom wall of the second trench 2131 and a first metal layer 2133 filling the second trench 2131.
The trench isolation ring 212 and the trench isolation structure 213 are formed simultaneously, and the forming processes of the trench isolation ring 212 and the trench isolation structure 213 are integrated, so that the forming process of the trench isolation ring 212 can be simplified, and further, the cost is saved.
Moreover, the first trench 2121 and the second trench 2131 both penetrate through the first wafer 21 to expose a surface of the first device layer 211 facing away from the second wafer 22, so that bottoms of the trench isolation ring 212 and the trench isolation structure 213 are both in contact with the surface of the first device layer 211 facing away from the second wafer 22, thereby improving an isolation effect between the trench isolation ring 212 and the trench isolation structure 213.
In addition, in the above step of forming the trench isolation ring 212 and the trench isolation structure 213, when the first metal layer and the first insulating material layer are subjected to top planarization or back etching, only the first metal layer on the back surface of the first wafer 21 may be removed, the first insulating material layer on the back surface of the first wafer 21 is retained, and the retained first insulating material layer and a subsequently formed insulating medium layer 214 are used together as an insulating material to cover the back surface of the first wafer 21.
An adhesive layer (not shown) is further interposed between the first insulating material layer and the first metal layer; the material of the first insulating material layer includes at least one of silicon oxide and a high-K dielectric having a dielectric constant K greater than 3.9, and the first insulating material layer may have a single-layer or multi-layer structure (e.g., a layer of silicon oxide and a layer of high-K dielectric). The material of the first metal layer comprises at least one of tungsten, aluminum, copper, silver, gold and metal oxide, and the material of the adhesion layer comprises at least one of titanium, tantalum and metal nitride.
Referring to fig. 5c, an insulating dielectric layer 214 is formed on the back surface of the first wafer 21 and the trench isolation ring 212, the insulating dielectric layer 214 covers the back surface of the first wafer 21, and the insulating dielectric layer 214 further buries the trench isolation structure 213 therein.
The material of the insulating dielectric layer 214 includes at least one of silicon oxide and a high-K dielectric having a dielectric constant K greater than 3.9, and the insulating dielectric layer 214 may have a single-layer or multi-layer structure (e.g., a layer of silicon oxide and a layer of high-K dielectric).
Forming a via plug structure 215 in the pad region B2 on the back side of the first wafer 21, wherein the via plug structure 215 penetrates through the insulating dielectric layer 214 and the first wafer 21 and is electrically connected to the metal interconnection structure 2111 in the first device layer 211, and the via plug structure 215 is surrounded by the trench isolation ring 212. A portion of the first wafer 21 is sandwiched between the trench isolation ring 212 and the via plug structure 215 surrounded by the trench isolation ring, so that two portions of parasitic capacitance are formed, one is the parasitic capacitance formed by the first wafer 21, the first insulating material layer 2122 and the first metal layer 2123, and the other is the parasitic capacitance formed by the first wafer 21, the second insulating material layer 2152 and the second metal layer 2153.
The step of forming the via plug structure 215 in the pad region B2 on the back side of the first wafer 21 includes: first, as shown in fig. 5d, the insulating dielectric layer 214 and the first wafer 21 on the pad region B2 are etched until the top of the metal interconnect structure 2111 in the first device layer 211 is exposed, so as to form a through hole 2151 in the pad region B2 surrounded by the trench isolation ring 212, and if a conductive plug 2112 is further formed above the metal interconnect structure 2111, the through hole 2151 exposes the top of the conductive plug 2112; then, forming a second insulating material layer 2152 covering the sidewalls of the through holes 2151 and the insulating dielectric layer 214; next, depositing a second metal layer 2153 on the second insulating material layer 2152, wherein the second metal layer 2153 at least fills the via 2151 and is in electrical contact with the metal interconnect structure 2111 or the conductive plug 2112; next, the second metal layer 2153 and the second insulating material layer 2152 are top planarized or etched back, and excess second metal layer 2153 and second insulating material layer 2152 on the insulating dielectric layer 214 around the via 2151 are removed to form the via plug structure 215 in the via 2151, as shown in fig. 5 e.
An adhesive layer (not shown) is further interposed between the second insulating material layer 2152 and the second metal layer 2153; the material of the second insulating material layer 2152 includes at least one of silicon oxide and a high-K dielectric having a dielectric constant K greater than 3.9, and the second insulating material layer 2152 may have a single-layer or multi-layer structure (e.g., a layer of silicon oxide and a layer of high-K dielectric). The material of the second metal layer 2153 includes at least one of tungsten, aluminum, copper, silver, gold, and metal oxide, and the material of the adhesion layer includes at least one of titanium, tantalum, and metal nitride.
A bonding pad 216 is formed on the insulating dielectric layer 214, and the bottom of the bonding pad 216 is electrically connected to the top of the via plug structure 215. Since the trench isolation ring 212 surrounds the via plug structure 215, the bottom of the pad 216 is electrically connected to the top of the via plug structure 215 surrounded by the trench isolation ring 212. The bonding pad 216 forms a parasitic capacitance with the insulating medium layer 214 and the first wafer 21 covered by the bonding pad.
The method for manufacturing the semiconductor device further includes forming a metal grid layer 217 above the trench isolation structure 213, and electrically connecting or insulating between the bottom of the metal grid layer 217 and the top of the trench isolation structure 213. The metal grid layer 217 may be formed on the insulating dielectric layer 214 simultaneously with the pad 216.
The step of forming the pad 216 and the metal grid layer 217 includes: first, a third metal layer (not shown) is covered on the insulating dielectric layer 214, and the third metal layer buries the via plug structure 215 therein; then, the third metal layer is etched to form the pad 216 and the metal grid layer 217 on the insulating dielectric layer 214, and the metal grid layer 217 is insulated from the trench isolation structure 213 by the insulating dielectric layer 214.
Alternatively, the step of forming the pad 216 and the metal grid layer 217 includes: first, as shown in fig. 5f, the insulating dielectric layer 214 on the pixel area a2 is etched to form an opening 2171, where the opening 2171 exposes at least a portion of the top of the trench isolation structure 213 or exposes a portion of the top surface of the first wafer 21 around the trench isolation structure 213; then, a third metal layer is covered on the insulating dielectric layer 214, and the third metal layer buries the via plug structure 215 therein and fills the opening 2171; next, as shown in fig. 5g, the third metal layer is etched to form the pad 216 and the metal grid layer 217 on the insulating dielectric layer 214, and when the opening 2171 exposes the metal material (i.e., the first metal layer 2133) in the trench isolation structure 213, the metal grid layer 217 is electrically connected to the trench isolation structure 213, and when the opening 2171 does not expose the metal material (i.e., the first metal layer 2133) of the trench isolation structure 213, the metal grid layer 217 is insulated from the trench isolation structure 213.
In addition, as shown in fig. 5h, after the pad 216 and the metal grid layer 217 are formed, a passivation layer 218 is further formed to cover the surfaces of the insulating dielectric layer 214 and the metal grid layer 217, the passivation layer 218 buries the metal grid layer 217 therein, and the passivation layer 218 exposes at least a portion of the top surface of the pad 216, so that the pad 216 is externally connected to a power supply, and further, a circuit in the pad region B2 is extracted through the pad 216 and the via plug structure 215, so as to perform an external pressure electrical test and operation on the pad region B2.
As shown in fig. 5g or fig. 5h and fig. 6, compared with the structure of the semiconductor device shown in fig. 1 and fig. 2, the structure of the semiconductor device formed in steps S21 to S25 is introduced with the structure of the trench isolation ring 212, so that three portions of parasitic capacitance are formed in the pad region B2, and in combination with fig. 7, the three portions of parasitic capacitance include the first parasitic capacitance C1 composed of the first wafer 21, the insulating dielectric layer 214 and the pad 216, the second parasitic capacitance C2 composed of the first wafer 21, the second insulating material layer 2152 and the second metal layer 2153, and the third parasitic capacitance C3 composed of the first wafer 21, the first insulating material layer 2122 and the first metal layer 2123, and the first parasitic capacitance C1 and the second parasitic capacitance C2 are connected in parallel and then connected in series with the third parasitic capacitance C3. Then, according to the capacitance calculation formula 1/C ═ 1/(C1+ C2) +1/C3, where C is the total parasitic capacitance, in the structure of the semiconductor device of the present invention, since the third parasitic capacitance C3 is connected in series to the first parasitic capacitance C1 and the second parasitic capacitance C2 which are connected in parallel, the total parasitic capacitance C is reduced, and therefore, not only the subsequent pad process can be implemented, but also the device performance can be improved (for example, the signal transmission rate of the input/output terminal can be improved) by reducing the total parasitic capacitance of the device. Particularly, for a semiconductor device operating at a high frequency, the effect of reducing the parasitic capacitance on the performance improvement of the semiconductor device is more remarkable. In addition, an element such as a resistor R can be incorporated in a circuit of a parasitic capacitance in the semiconductor device shown in fig. 7.
As shown in fig. 6, one trench isolation ring 212 is correspondingly formed below each of the pads 216, and the via plug structure 215 surrounded by the trench isolation ring 212 is correspondingly formed below each of the pads 216; the area of the bonding pad 216 may be smaller than the area surrounded by the trench isolation ring 212, or equal to or larger than the area surrounded by the trench isolation ring 212, however, the area of the bonding pad 216 is preferably as small as possible to minimize the first parasitic capacitance C1, thereby reducing the total parasitic capacitance C.
Moreover, since the via plug structure 215 penetrates through the insulating dielectric layer 214 and the first wafer 21 from the back surface of the first wafer 21, and the trench isolation ring 212 also penetrates through the first wafer 21, the trench isolation ring 212 can completely isolate the portion of the wafer 21 surrounded by the trench isolation ring 212 and the via plug structure 215, and thus the trench isolation ring 212 can reduce the total parasitic capacitance.
In addition, since there is no circuit in the pixel region a2, the pixel region a2 will not perform external stress electrical test and operation, and thus, even though the trench isolation structure 213 and the trench isolation ring 212 are formed at the same time, and the first insulating material layer 2132 and the first metal layer 2133 in the trench isolation structure 213 and the first wafer 21 in the pixel region a2 form a parasitic capacitance structure, the parasitic capacitance formed therein will not affect the total parasitic capacitance of the semiconductor device.
In addition, the steps in the method for manufacturing a semiconductor device are not limited to the above formation order, and the order of the steps can be adaptively adjusted.
In summary, in the manufacturing method of the semiconductor device provided by the present invention, the trench isolation ring is formed in the pad region on the back side of the first wafer, and the trench isolation ring includes the first metal layer and the first insulating material layer; forming an insulating medium layer on the back surface of the first wafer and the groove isolation ring; forming a through hole plug structure in the bonding pad area on the back surface of the first wafer, wherein the through hole plug structure is surrounded by the groove isolation ring; and forming a bonding pad on the insulating medium layer, wherein the bottom of the bonding pad is electrically connected with the top of the through hole plug structure, so that the total parasitic capacitance of the device can be reduced while the subsequent bonding pad process is realized, and the performance of the semiconductor device is improved.
An embodiment of the invention provides a semiconductor device, which comprises a first wafer, a trench isolation ring, an insulating medium layer, a through hole plug structure and a bonding pad, wherein the back surface of the first wafer is provided with a bonding pad area, the front surface of the first wafer is provided with a first device layer, and the first device layer is provided with a metal interconnection structure; the groove isolation ring is formed in a pad area of the first wafer and comprises a first metal layer and a first insulating material layer, wherein the first insulating material layer is positioned on the side wall and the bottom surface of an annular groove of the pad area on the back side of the first wafer, and the annular groove is filled with the first metal layer; the insulating medium layer is formed on the back surface of the first wafer and covers the groove isolation ring; the through hole plug structure is formed in a bonding pad area on the back surface of the first wafer, penetrates through the insulating medium layer and the first wafer, is electrically connected with the metal interconnection structure in the first device layer, and is surrounded by the groove isolation ring; the bonding pad is formed on the insulating medium layer, and the bottom of the bonding pad is electrically connected with the top of the through hole plug structure.
The semiconductor device provided in this embodiment will be described in detail with reference to fig. 5h, 6, and 7, taking an image sensor of a 3D IC as an example. The invention is not limited thereto, and can be applied to other subsequent bonding pad processes.
The first wafer 21 is bonded to a second wafer 22, a back surface (i.e., a surface facing away from the second wafer 22) of the first wafer 21 has a pad region B2, a surface of the first wafer 21 facing the second wafer 22 has a first device layer 211 formed thereon, and the first device layer 211 has a metal interconnection structure 2111 therein.
The first device layer 211 may further include a conductive plug 2112 located on a side of the metal interconnect structure 2111 facing away from the second wafer 22, where a bottom of the conductive plug 2112 is electrically connected to the metal interconnect structure 2111. Other functional structures, such as a pixel array, may also be included in the first device layer 211.
The first wafer 21 may be a device wafer, for example a pixel wafer comprising an array of pixels of an image sensor, the kind of the first wafer 21 depending on the function of the device to be finally fabricated. The first wafer 21 may be a single-layer wafer structure or a multi-layer wafer bonded structure.
The back side of the first wafer 21 further has a pixel region a2, and the pad region B2 is located at the periphery of the pixel region a 2.
A second device layer 221 is formed on a surface of the second wafer 22 facing the first wafer 21. The semiconductor device further includes bonding layers (not shown) respectively formed on the first device layer 211 and the second device layer 221, burying the first device layer 211 and the second device layer 221 therein, respectively, and bonding the first device layer 211 to the second device layer 221 to bond the first device layer 211 to the second wafer 22.
The second wafer 22 may be a logic wafer, in which CMOS circuits are formed; the second device layer 221 may include MOS transistors, resistors, capacitors, metal interconnection structures, and the like. The second wafer 22 may be a single-layer wafer structure or a multi-layer wafer bonded structure. When the first wafer 21 and the second wafer 22 are single-layer wafers, the first wafer 21 and the second wafer 22 may be understood as substrates.
The second wafer 22 may also be a carrier wafer without a device function, and the second device layer 221 is not formed on the second wafer 22, but a bonding layer is directly formed thereon to be bonded with the bonding layer on the first wafer 21.
The trench isolation ring 212 is formed in the pad region B2 of the first wafer 21 and located on a side of the first wafer 21 facing away from the second wafer 22, and the trench isolation ring 212 includes a first metal layer and a first insulating material layer, where the first insulating material layer is located on a sidewall and a bottom surface of an annular trench of the pad region B2 on the back side of the first wafer 21, and the annular trench is filled with the first metal layer.
The semiconductor device further comprises a trench isolation structure 213 formed in the pixel area a2 on the back side of the first wafer 21, wherein the bottom of the trench isolation structure 213 and the bottom of the trench isolation ring 212 have the same depth.
Trenches for forming the trench isolation ring 212 and the trench isolation structure 213 may penetrate through the first wafer 21, so that bottoms of the trench isolation ring 212 and the trench isolation structure 213 may contact a surface of the first device layer 211 facing away from the second wafer 22, thereby improving an isolation effect of the trench isolation ring 212 and the trench isolation structure 213.
The trench isolation ring 212 and the trench isolation structure 213 are formed by the same process, and each of the trench isolation ring and the trench isolation structure includes a first insulating material layer formed on the sidewall and the bottom wall of the trench and a first metal layer filled in the trench, and an adhesive layer is further sandwiched between the first insulating material layer and the first metal layer. For the sake of convenience of distinction, the trench isolation ring 212 is defined to include a first insulating material layer 2122 formed on the sidewall and the bottom wall of the corresponding annular trench and a first metal layer 2123 filling the corresponding trench, and the trench isolation structure 213 includes a first insulating material layer 2132 formed on the sidewall and the bottom wall of the corresponding trench and a first metal layer 2133 filling the corresponding trench.
The top surfaces of the trench isolation ring 212 and the trench isolation structure 213 are flush, and the top surfaces of the trench isolation ring 212 and the trench isolation structure 213 may be flush with the back surface of the first wafer 21 or higher than the back surface of the first wafer 21.
The trench isolation ring 212 and the trench isolation structure 213 are formed by the same process, and the forming processes of the trench isolation ring 212 and the trench isolation structure 213 are integrated, so that the forming process of the trench isolation ring 212 can be simplified, and further, the cost is saved.
In addition, during the process of forming the trench isolation ring 212 and the trench isolation structure 213, a first insulating material layer on a surface of the first wafer 21 facing away from the second wafer 22 may be retained, and the retained first insulating material layer and a subsequently formed insulating dielectric layer 214 together serve as an insulating material to cover a surface of the first wafer 21 facing away from the second wafer 22.
The material of the first insulating material layer includes at least one of silicon oxide and a high-K dielectric having a dielectric constant K greater than 3.9, and the first insulating material layer may have a single-layer or multi-layer structure (e.g., a layer of silicon oxide and a layer of high-K dielectric). The material of the first metal layer comprises at least one of tungsten, aluminum, copper, silver, gold and metal oxide, and the material of the adhesion layer comprises at least one of titanium, tantalum and metal nitride.
The insulating medium layer 214 is formed on a surface of the first wafer 21 facing away from the second wafer 22, and covers the trench isolation ring 212; the insulating dielectric layer 214 also buries the trench isolation structure 213 therein.
The material of the insulating dielectric layer 214 includes at least one of silicon oxide and a high-K dielectric having a dielectric constant K greater than 3.9, and the insulating dielectric layer 214 may have a single-layer or multi-layer structure (e.g., a layer of silicon oxide and a layer of high-K dielectric).
The via plug structure 215 is formed in the pad region B2 on the back side of the first wafer 21, the via plug structure 215 penetrates through the insulating dielectric layer 214 and the first wafer 21 and is electrically connected to the metal interconnection structure 2111 in the first device layer 211, and the via plug structure 215 is surrounded by the trench isolation ring 212. A portion of the first wafer 21 is sandwiched between the trench isolation ring 212 and the via plug structure 215 surrounded by the trench isolation ring, so that two portions of parasitic capacitance are formed, one is the parasitic capacitance formed by the first wafer 21, the first insulating material layer 2122 and the first metal layer 2123, and the other is the parasitic capacitance formed by the first wafer 21, the second insulating material layer 2152 and the second metal layer 2153.
The via plug structure 215 includes a second insulating material layer 2152 formed on the sidewall of the via hole and a second metal layer 2153 filling the via hole, and the bottom of the second metal layer 2153 is electrically connected to the metal interconnect structure 2111 and the conductive plug 2112 in the first device layer 211.
An adhesive layer (not shown) is further interposed between the second insulating material layer 2152 and the second metal layer 2153; the material of the second insulating material layer 2152 includes at least one of silicon oxide and a high-K dielectric having a dielectric constant K greater than 3.9, and the second insulating material layer 2152 may have a single-layer or multi-layer structure (e.g., a layer of silicon oxide and a layer of high-K dielectric). The material of the second metal layer 2153 includes at least one of tungsten, aluminum, copper, silver, gold, and metal oxide, and the material of the adhesion layer includes at least one of titanium, tantalum, and metal nitride.
The bonding pad 216 is formed on the insulating dielectric layer 214, and the bottom of the bonding pad 216 is electrically connected to the top of the via plug structure 215 surrounded by the trench isolation ring 212.
Since the trench isolation ring 212 surrounds the via plug structure 215, the bottom of the pad 216 is electrically connected to the top of the via plug structure 215 surrounded by the trench isolation ring 212. The bonding pad 216 forms a parasitic capacitance with the insulating medium layer 214 and the first wafer 21 covered by the bonding pad.
The semiconductor device further comprises a metal grid layer 217 located in the pixel area a2, wherein the metal grid layer 217 is formed above the trench isolation structure 213, and the bottom of the metal grid layer 217 is electrically connected or insulated with the top of the trench isolation structure 213.
The metal grid layer 217 may be electrically connected to the first metal layer 2133 in the trench isolation structure 213; the metal grid layer 217 and the trench isolation structure 213 may be insulated from each other by the insulating dielectric layer 214 (that is, the metal grid layer 217 does not penetrate through the insulating dielectric layer 214), or the metal grid layer 217 may be insulated from the trench isolation structure 213 after penetrating through the insulating dielectric layer 214.
The semiconductor device further comprises a passivation layer 218, wherein the passivation layer 218 covers the insulating dielectric layer 214 and the surface of the metal grid layer 217, and the passivation layer 218 buries the metal grid layer 217 inside; and the passivation layer 218 exposes at least a portion of the top surface of the pad 216 such that the pad 216 is externally connected to a power source, thereby drawing electrical circuitry in the pad region B2 through the pad 216 and the via plug structure 215 for external pressure electrical testing and operation of the pad region B2.
Compared with the structure of the semiconductor device shown in fig. 1 and 2, the structure of the semiconductor device in fig. 5h and 6 introduces the structure of the trench isolation ring 212, so that three parts of parasitic capacitance are formed in the pad region B2, and in conjunction with fig. 7, the three parts of parasitic capacitance include a first parasitic capacitance C1 composed of the first wafer 21, the insulating dielectric layer 214 and the pad 216, a second parasitic capacitance C2 composed of the first wafer 21, the second insulating material layer 2152 and the second metal layer 2153, and a third parasitic capacitance C3 composed of the first wafer 21, the first insulating material layer 2122 and the first metal layer 2123, and the first parasitic capacitance C1 and the second parasitic capacitance C2 are connected in parallel and then connected in series with the third parasitic capacitance C3. Then, according to the capacitance calculation formula 1/C ═ 1/(C1+ C2) +1/C3, where C is the total parasitic capacitance, in the structure of the semiconductor device of the present invention, since a third parasitic capacitance C3 is connected in series to the first parasitic capacitance C1 and the second parasitic capacitance C2 which are connected in parallel, the total parasitic capacitance C is reduced, and therefore, not only the subsequent pad process after wafer bonding in the 3D IC technology can be realized, but also the device performance can be improved (for example, the signal transmission rate at the input/output end is improved) by reducing the total parasitic capacitance of the device. Particularly, for a semiconductor device operating at a high frequency, the effect of reducing the parasitic capacitance on the performance improvement of the semiconductor device is more remarkable. In addition, an element such as a resistor R can be incorporated in a circuit of a parasitic capacitance in the semiconductor device shown in fig. 7.
As shown in fig. 6, one trench isolation ring 212 is correspondingly formed below each of the pads 216, and the via plug structure 215 surrounded by the trench isolation ring 212 is correspondingly formed below each of the pads 216; the area of the bonding pad 216 may be smaller than the area surrounded by the trench isolation ring 212, or equal to or larger than the area surrounded by the trench isolation ring 212, however, the area of the bonding pad 216 is preferably as small as possible to minimize the first parasitic capacitance C1, thereby reducing the total parasitic capacitance C.
Moreover, since the via plug structure 215 penetrates through the insulating dielectric layer 214 and the first wafer 21 from the back surface of the first wafer 21, and the trench isolation ring 212 also penetrates through the first wafer 21, the trench isolation ring 212 can completely isolate the portion of the wafer 21 surrounded by the trench isolation ring 212 and the via plug structure 215, and thus the trench isolation ring 212 can reduce the total parasitic capacitance.
In addition, since there is no circuit in the pixel region a2, the pixel region a2 does not perform external stress electrical test and operation, and even if the trench isolation structure 213 and the trench isolation ring 212 are formed at the same time, and the first insulating material layer 2132 and the first metal layer 2133 in the trench isolation structure 213 and the first wafer 21 in the pixel region a2 form a parasitic capacitance structure, the parasitic capacitance formed here does not affect the total parasitic capacitance of the semiconductor device.
In summary, the semiconductor device provided by the present invention includes: the groove isolation ring is formed in a bonding pad area of a first wafer and comprises a first metal layer and a first insulating material layer; the insulating medium layer is formed on the back surface of the first wafer and covers the groove isolation ring; the through hole plug structure is formed in the bonding pad area on the back side of the first wafer and is surrounded by the groove isolation ring; and the bottom of the bonding pad is electrically connected with the top of the through hole plug structure, so that the total parasitic capacitance of the device can be reduced while the subsequent bonding pad process is realized, and the performance of the semiconductor device is improved.
According to the semiconductor device and the manufacturing method of the semiconductor device provided by the embodiment of the invention, the groove isolation ring is added in the pad area on the back side of the first wafer, so that three parts of parasitic capacitance are formed in the pad area. The first parasitic capacitor C1 and the second parasitic capacitor C2 are connected in parallel, and then connected in series with the third parasitic capacitor C3, according to the calculation formula 1/C of the capacitors, which is 1/(C1+ C2) +1/C3, the embodiment of the invention enables the total parasitic capacitor C to be reduced. The embodiment of the invention can be applied to a semiconductor device using a pad region, and is not limited to an image sensor and a depth sensor.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (14)
1. A method of manufacturing a semiconductor device, comprising:
providing a first wafer with a pad area on the back surface, wherein a first device layer is formed in the first wafer, and a metal interconnection structure is arranged in the first device layer;
forming a trench isolation ring in the pad area on the back side of the first wafer, wherein the trench isolation ring comprises a first metal layer and a first insulating material layer, the first insulating material layer is located on the side wall and the bottom surface of the annular trench of the pad area on the back side of the first wafer, and the annular trench is filled with the first metal layer;
forming an insulating medium layer on the back surface of the first wafer and the groove isolation ring;
forming a through hole plug structure in a pad area on the back side of the first wafer, wherein the through hole plug structure penetrates through the insulating medium layer and the first wafer, the through hole plug structure comprises a second insulating material layer formed on the side wall of a through hole and a second metal layer filling the through hole, the bottom of the second metal layer is electrically connected with a metal interconnection structure in the first device layer, and the through hole plug structure is surrounded by the groove isolation ring; and the number of the first and second groups,
forming a bonding pad on the insulating medium layer, wherein the bottom of the bonding pad is electrically connected with the top of the through hole plug structure; the first wafer, the insulating medium layer and the bonding pad form a first parasitic capacitor, the first wafer, the second insulating material layer and the second metal layer form a second parasitic capacitor, the first wafer, the first insulating material layer and the first metal layer form a third parasitic capacitor, and the first parasitic capacitor is connected with the second parasitic capacitor in parallel and then connected with the third parasitic capacitor in series.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the trench isolation ring comprises:
etching the back surface of the first wafer until the first device layer is exposed, so as to form an annular groove in the pad area;
forming a first insulating material layer to cover the side wall and the bottom surface of the annular groove;
depositing a first metal layer on the first insulating material layer, wherein the first metal layer at least fills the annular groove; and
and carrying out top planarization or back etching on the first metal layer and the first insulating material layer, and removing redundant first metal layer and first insulating material layer on the back surface of the first wafer around the annular groove so as to form the groove isolation ring in the annular groove.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the back surface of the first wafer further has a pixel region; and forming a trench isolation structure in the pixel region on the back surface of the first wafer while forming the trench isolation ring in the pad region on the back surface of the first wafer, wherein the depth of the bottom of the trench isolation structure is the same as that of the bottom of the trench isolation ring.
4. A method for manufacturing a semiconductor device according to claim 1, wherein an adhesive layer is further interposed between the first insulating material layer and the first metal layer; the material of the first insulating material layer comprises at least one of silicon oxide and a high-K medium with a dielectric constant K larger than 3.9, the material of the first metal layer comprises at least one of tungsten, aluminum, copper, silver and gold, and the material of the bonding layer comprises at least one of titanium, tantalum and metal nitride.
5. The method of claim 3, further comprising forming a metal grid layer over the trench isolation structure, wherein a bottom of the metal grid layer is electrically connected or insulated from a top of the trench isolation structure.
6. The method for manufacturing a semiconductor device according to claim 1, wherein after the pad is formed, a passivation layer is further formed to cover a surface of the insulating dielectric layer, and the passivation layer exposes at least a portion of a top surface of the pad.
7. The method for manufacturing a semiconductor device according to claim 1, wherein bonding layers are formed on surfaces of the first wafer and a second wafer, respectively, before the trench isolation ring is formed, and then the first wafer is bonded to the second wafer through the bonding layers.
8. The method of manufacturing the semiconductor device according to claim 7, wherein a back side of the first wafer is thinned after the first wafer is bonded to the second wafer and before the trench isolation ring is formed.
9. A semiconductor device, comprising:
the semiconductor device comprises a first wafer, a second wafer and a third wafer, wherein the back surface of the first wafer is provided with a bonding pad area, a first device layer is formed in the first wafer, and a metal interconnection structure is arranged in the first device layer;
the groove isolation ring is formed in the pad area of the first wafer and comprises a first metal layer and a first insulating material layer, wherein the first insulating material layer is positioned on the side wall and the bottom surface of the annular groove of the pad area on the back side of the first wafer, and the annular groove is filled with the first metal layer;
the insulating medium layer is formed on the back surface of the first wafer and covers the groove isolation ring;
the through hole plug structure is formed in a pad area on the back surface of the first wafer, penetrates through the insulating medium layer and the first wafer, comprises a second insulating material layer formed on the side wall of the through hole and a second metal layer filling the through hole, the bottom of the second metal layer is electrically connected with the metal interconnection structure in the first device layer, and the through hole plug structure is surrounded by the groove isolation ring; and the number of the first and second groups,
the bonding pad is formed on the insulating medium layer, and the bottom of the bonding pad is electrically connected with the top of the through hole plug structure; the first wafer, the insulating medium layer and the bonding pad form a first parasitic capacitor, the first wafer, the second insulating material layer and the second metal layer form a second parasitic capacitor, the first wafer, the first insulating material layer and the first metal layer form a third parasitic capacitor, and the first parasitic capacitor is connected with the second parasitic capacitor in parallel and then connected with the third parasitic capacitor in series.
10. The semiconductor device of claim 9, wherein the back side of the first wafer further has a pixel region; the semiconductor device further comprises a trench isolation structure formed in the pixel region on the back side of the first wafer, and the depth of the bottom of the trench isolation structure is the same as that of the bottom of the trench isolation ring.
11. The semiconductor device according to claim 9, wherein an adhesive layer is further interposed between the first insulating material layer and the first metal layer; the first insulating material layer and the second insulating material layer are made of at least one of silicon oxide and a high-K medium with a dielectric constant K larger than 3.9, the first metal layer and the second metal layer are made of at least one of tungsten, aluminum, copper, silver and gold, and the bonding layer is made of at least one of titanium, tantalum and metal nitride.
12. The semiconductor device according to claim 10, further comprising a metal grid layer in the pixel region, wherein the metal grid layer is formed over the trench isolation structure, and wherein a bottom of the metal grid layer is electrically connected or insulated from a top of the trench isolation structure.
13. The semiconductor device of claim 12, further comprising a passivation layer overlying a surface of the insulating dielectric layer and exposing at least a portion of the top surface of the pad.
14. The semiconductor device of claim 9, further comprising a second wafer bonded to the first wafer.
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| CN117995795A (en) * | 2022-10-31 | 2024-05-07 | 华为技术有限公司 | Chip, chip stacking structure, chip packaging structure and electronic equipment |
| CN116417487A (en) * | 2023-06-09 | 2023-07-11 | 湖北江城芯片中试服务有限公司 | Method for forming semiconductor structure and semiconductor structure |
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