CN117995795A - Chip, chip stacking structure, chip packaging structure and electronic equipment - Google Patents

Chip, chip stacking structure, chip packaging structure and electronic equipment Download PDF

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Publication number
CN117995795A
CN117995795A CN202211345283.4A CN202211345283A CN117995795A CN 117995795 A CN117995795 A CN 117995795A CN 202211345283 A CN202211345283 A CN 202211345283A CN 117995795 A CN117995795 A CN 117995795A
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China
Prior art keywords
chip
dielectric layer
wafer
metal
electrically connected
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CN202211345283.4A
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Chinese (zh)
Inventor
董金文
朱继锋
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN202211345283.4A priority Critical patent/CN117995795A/en
Priority to PCT/CN2023/103154 priority patent/WO2024093288A1/en
Publication of CN117995795A publication Critical patent/CN117995795A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The embodiment of the application provides a chip, a chip stacking structure, a chip packaging structure and electronic equipment, and relates to the technical field of semiconductors, wherein a through hole in the chip, such as a through silicon via (through silicon via, TSV), generates smaller parasitic capacitance when an alternating current signal passes through, so that the signal transmission performance of the chip is improved. The chip includes a wafer; the wafer is provided with a via hole, a metal circuit is arranged in the via hole, a first dielectric layer is arranged between the metal circuit and the wafer, the wafer also comprises a first isolating ring which surrounds the via hole, and the dielectric constant of the first isolating ring is smaller than that of the material of the first dielectric layer.

Description

Chip, chip stacking structure, chip packaging structure and electronic equipment
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a chip, a chip stacking structure, a chip packaging structure, and an electronic device.
Background
Electronic devices are currently moving toward smaller and more powerful electronic devices, the size of which depends on the size of the chip in the electronic device. In recent years, the planar dimensions of chips have been reduced to a limit, and three-dimensional (three dimensional, 3D) stacked packaging technology has provided new solutions for chip size reduction. One of the 3D stacked package technologies is to construct a chip stacked structure using through silicon vias (through silicon via, TSVs), where two or more vertically stacked chips are included, any two of the two or more vertically stacked chips may be electrically connected through the through silicon vias, for example, the through silicon vias may be disposed in a first chip, and a second chip is electrically connected to the through silicon vias, so that signals may be transmitted between the first chip and the second chip through the through silicon vias.
However, when the ac signal passes through the through-silicon via, a larger parasitic capacitance is generated between the through-silicon via and other electronic components disposed in the first chip, and the parasitic capacitance increases the resistance-capacitance delay (RESISTANCE CAPACITANCE DELAY, RC delay) of the first chip, thereby reducing the signal transmission performance of the first chip.
Disclosure of Invention
The embodiment of the application provides a chip, a chip stacking structure, a chip packaging structure and electronic equipment, wherein a through hole in the chip, such as a through silicon via (through silicon via, TSV), generates smaller parasitic capacitance when an alternating current signal passes through the through silicon via, so that the signal transmission performance of the chip is improved.
In a first aspect, a chip is provided, comprising a wafer; the wafer is provided with a via hole, a metal circuit is arranged in the via hole, and a first dielectric layer is arranged between the metal circuit and the wafer; the wafer also comprises a first isolation ring surrounding the via hole, and the dielectric constant of the first isolation ring is smaller than that of the material of the first dielectric layer. In the chip, when the through hole enables the chip and other chips to realize signal communication through signals, a first dielectric layer is arranged between a metal line in the through hole and a wafer, so that the metal line in the through hole, the wafer and the first dielectric layer form a capacitor C1, one electrode of the capacitor C1 is the metal line in the through hole, the other electrode of the capacitor C1 is the wafer, a dielectric material between two electrodes of the capacitor C1 is the first dielectric layer, in addition, as the first isolating ring surrounds the through hole, the first isolating ring and the wafers at two sides of the first isolating ring form a capacitor C2, one electrode of the capacitor C2 is the wafer at one side of the first isolating ring, the other electrode of the capacitor C2 is the wafer at the other side of the first isolating ring, the dielectric material between the two electrodes of the capacitor C2 is a first isolating ring, where, since the dielectric constant of the first isolating ring is smaller than that of the material of the first dielectric layer, the capacitance value of the capacitor C2 will be smaller than that of the capacitor C1, and then, when the signal is transmitted through the via hole, it is equivalent to connecting the capacitor C1 and the capacitor C2 in series between the via hole and the electronic component disposed in the wafer in the chip, and the equivalent capacitance after the series is C, c= (c1×c2)/(c1+c2), that is, 1/c= (1/C1) + (1/C2), it is seen that, after connecting the capacitor C1 and the capacitor C2 in series, the parasitic capacitance between the via hole and the electronic component disposed in the wafer in the chip can be reduced, so that the signal transmission performance of the chip is improved.
Optionally, an air gap is included in the first spacer ring. In this alternative, when the first isolation ring includes an air gap, the dielectric constant of the air gap is lower, so that the capacitance value of the capacitor C2 is further reduced, so that the parasitic capacitance between the via hole and the electronic component disposed in the wafer in the chip is also further reduced, and thus, the signal transmission performance of the chip is improved.
Optionally, the wafer further includes a second spacer surrounding the first spacer, wherein a dielectric constant of the second spacer is less than a dielectric constant of a material of the first dielectric layer. In this alternative, since the second spacer surrounds the first spacer, the second spacer, and the wafers on both sides of the second spacer will also constitute a capacitor C3, wherein one electrode of the capacitor C3 is a wafer on one side of the second spacer, the other electrode of the capacitor C3 is a wafer on the other side of the second spacer, and the dielectric material between the two electrodes of the capacitor C3 is the second spacer, wherein, since the dielectric constant of the second spacer is smaller than the dielectric constant of the material of the first dielectric layer, the capacitance value of the capacitor C3 will be smaller than the capacitance value of the capacitor C1, and then, when a signal is transmitted through the via, the equivalent capacitance after the series connection is reduced again, such that the parasitic capacitance between the via and the electronic components disposed in the wafer in the chip is reduced again, so that the signal transmission performance of the chip is higher.
Optionally, an air gap is included in the second spacer ring. In this alternative, when the second isolation ring includes an air gap, the dielectric constant of the air gap is lower, so that the capacitance value of the capacitor C3 is further reduced, so that the parasitic capacitance between the via hole and the electronic component disposed in the wafer in the chip is also further reduced, and thus, the signal transmission performance of the chip is improved.
Optionally, a distance between the first spacer ring and the via is greater than or equal to 0.5 micrometers.
Optionally, the ring width of the first isolation ring is greater than or equal to 0.1 micrometer and less than or equal to 1 micrometer.
Optionally, the diameter of the first via hole is greater than or equal to 1 micrometer.
Optionally, the material of the metal line includes copper and tungsten.
Optionally, the chip further includes a second dielectric layer, the second dielectric layer is disposed on one side of the wafer, and the metal circuit is electrically connected to the metal wiring in the second dielectric layer.
In a second aspect, a chip stack structure is provided, the chip stack structure comprising a plurality of stacked chips, the plurality of stacked chips comprising the chip according to any one of the first aspects.
Optionally, the plurality of stacked chips includes a first chip and a second chip; the first chip and the second chip both comprise a second dielectric layer arranged on one side of the wafer; in the plurality of stacked chips, a wafer of a first chip is arranged between a second dielectric layer of the first chip and a second dielectric layer of a second chip, and the second dielectric layer of the first chip is arranged between the wafer of the first chip and the wafer of the second chip; one end of the metal line of the first chip is electrically connected with the metal wiring in the second dielectric layer of the first chip, and the other end of the metal line of the first chip is electrically connected with the metal wiring in the second dielectric layer of the second chip. In the alternative mode, one or more metal wires are arranged in the second dielectric layer of the first chip, and the metal wires in the second dielectric layer of the first chip are electrically connected with electronic components arranged in the wafer in the first chip to form a circuit structure, so that the active surface of the first chip is positioned on one surface, far away from the wafer of the first chip, of the second dielectric layer of the first chip; one or more metal wirings are arranged in the second dielectric layer of the second chip, and the metal wirings in the second dielectric layer of the second chip are electrically connected with electronic components arranged in the wafer in the second chip to form a circuit structure, so that the active surface of the second chip is positioned on one surface of the second dielectric layer of the second chip, which is far away from the wafer of the second chip. In addition, the wafer of the first chip is disposed between the second dielectric layer of the first chip and the second dielectric layer of the second chip, and the second dielectric layer of the first chip is disposed between the wafer of the first chip and the wafer of the second chip, so that the active surface of the second chip is bonded to the passive surface of the first chip, which bonding method is also called face-to-back bonding. One end of the metal line of the first chip is electrically connected with the metal wiring in the second dielectric layer of the first chip, and the other end of the metal line of the first chip is electrically connected with the metal wiring in the second dielectric layer of the second chip, so that signals received by the active surface of the first chip can be transmitted to the active surface of the second chip through the metal wiring of the second dielectric layer of the first chip and the metal wiring in the via hole of the first chip, and further transmitted to electronic components arranged in the wafer of the second chip through the metal wiring of the second dielectric layer of the second chip; or the signal received by the active surface of the second chip can be transmitted to the active surface of the first chip through the metal wiring of the second dielectric layer of the second chip and the metal wiring in the via hole of the first chip, and then transmitted to the electronic component arranged in the wafer of the first chip through the metal wiring of the second dielectric layer of the first chip. That is, by providing metal lines in the via holes of the first chip, signal communication between the second chip and the first chip can be achieved.
Optionally, the plurality of stacked chips includes a first chip and a second chip; the first chip and the second chip both comprise a second dielectric layer arranged on one side of the wafer; in the plurality of chips which are stacked, a second dielectric layer of a second chip and a second dielectric layer of a first chip are arranged between a wafer of the first chip and a wafer of the second chip; one end of the metal wire of the first chip is electrically connected with the metal wire in the second dielectric layer of the first chip, and the metal wire in the second dielectric layer of the first chip is electrically connected with the metal wire in the second dielectric layer of the second chip. In the alternative mode, one or more metal wires are arranged in the second dielectric layer of the first chip, and the metal wires in the second dielectric layer of the first chip are electrically connected with electronic components arranged in the wafer in the first chip to form a circuit structure, so that the active surface of the first chip is positioned on one surface, far away from the wafer of the first chip, of the second dielectric layer of the first chip; one or more metal wirings are arranged in the second dielectric layer of the second chip, and the metal wirings in the second dielectric layer of the second chip are electrically connected with electronic components arranged in the wafer in the second chip to form a circuit structure, so that the active surface of the second chip is positioned on one surface of the second dielectric layer of the second chip, which is far away from the wafer of the second chip. In addition, the second dielectric layer of the second chip and the second dielectric layer of the first chip are disposed between the wafer of the first chip and the wafer of the second chip, and therefore, the active surface of the second chip is bonded to the active surface of the first chip, and this bonding method is also called face-to-face bonding. One end of the metal wire of the first chip is electrically connected with the metal wire in the second dielectric layer of the first chip, and the metal wire in the second dielectric layer of the first chip is electrically connected with the metal wire in the second dielectric layer of the second chip, so that a signal received by the active surface of the first chip can be transmitted to the active surface of the second chip through the metal wire of the second dielectric layer of the first chip, and further transmitted to an electronic component arranged in a wafer of the second chip through the metal wire of the second dielectric layer of the second chip; or the signal received by the active surface of the second chip can be transmitted to the active surface of the first chip through the metal wiring of the second dielectric layer of the second chip, and then transmitted to the electronic component arranged in the wafer of the first chip through the metal wiring of the second dielectric layer of the first chip, namely, the signal intercommunication can be realized between the second chip and the first chip. When some signals are transmitted to the active surface of the first chip through the passive surface of the first chip, the signals are transmitted to the active surface of the first chip through metal lines in the via holes of the first chip, and then are transmitted to electronic components arranged in the wafer of the first chip through metal wiring in the second dielectric layer of the first chip, and as signal intercommunication can be realized between the first chip and the second chip, the signals transmitted to the active surface of the first chip through the passive surface of the first chip can also be transmitted to the active surface of the second chip.
Optionally, the plurality of stacked chips includes a first chip and a second chip; the first chip and the second chip both comprise a second dielectric layer arranged on one side of the wafer; in the plurality of chips which are stacked, a wafer of a second chip and a wafer of a first chip are arranged between a second dielectric layer of the first chip and a second dielectric layer of the second chip; one end of the metal line of the first chip is electrically connected with the metal wiring in the second dielectric layer of the first chip, one end of the metal line of the second chip is electrically connected with the metal wiring in the second dielectric layer of the second chip, and the other end of the metal line of the first chip is electrically connected with the other end of the metal line of the second chip. In the alternative mode, one or more metal wires are arranged in the second dielectric layer of the first chip, and the metal wires in the second dielectric layer of the first chip are electrically connected with electronic components arranged in the wafer in the first chip to form a circuit structure, so that the active surface of the first chip is positioned on one surface, far away from the wafer of the first chip, of the second dielectric layer of the first chip; one or more metal wirings are arranged in the second dielectric layer of the second chip, and the metal wirings in the second dielectric layer of the second chip are electrically connected with electronic components arranged in the wafer in the second chip to form a circuit structure, so that the active surface of the second chip is positioned on one surface of the second dielectric layer of the second chip, which is far away from the wafer of the second chip. In addition, the wafer of the second chip and the wafer of the first chip are disposed between the second dielectric layer of the first chip and the second dielectric layer of the second chip, and therefore, the passive surface of the second chip is bonded to the passive surface of the first chip, which is also called back-to-back bonding. One end of the metal line of the first chip is electrically connected with the metal wiring in the second dielectric layer of the first chip, one end of the metal line of the second chip is electrically connected with the metal wiring in the second dielectric layer of the second chip, and the other end of the metal line of the first chip is electrically connected with the other end of the metal line of the second chip, so that signals received by the active surface of the first chip can be transmitted to the active surface of the second chip through the metal wiring of the second dielectric layer of the first chip, the metal line in the via hole of the first chip and the metal line in the via hole of the second chip, and then transmitted to electronic components arranged in the wafer of the second chip through the metal wiring of the second dielectric layer of the second chip; or the signal received by the active surface of the second chip can be transmitted to the active surface of the first chip through the metal wiring of the second dielectric layer of the second chip, the metal circuit in the via hole of the second chip and the metal circuit in the via hole of the first chip, and then transmitted to the circuit structure formed by the electronic components arranged in the wafer of the first chip through the metal wiring of the second dielectric layer of the first chip, namely, the signal intercommunication can be realized between the second chip and the first chip through the metal circuit in the via hole of the first chip and the metal circuit in the via hole of the second chip.
In a third aspect, a chip package structure is provided, including a package substrate and the chip stack structure according to any one of the second aspects above; the chip stacking structure is electrically connected with the packaging substrate.
In a fourth aspect, there is provided an electronic device comprising a printed circuit board and a chip package structure as described in the second aspect above; the package substrate in the chip package structure is electrically connected with the printed circuit board.
In a fifth aspect, a method for manufacturing a chip is provided, including: forming a via hole in the wafer, and forming a metal circuit and a first dielectric layer in the via hole, wherein the first dielectric layer is positioned between the metal circuit and the wafer; and forming a first isolation ring, wherein the first isolation ring surrounds the via hole, and the dielectric constant of the first isolation ring is smaller than that of the material of the first dielectric layer.
The technical effects brought about by any one of the possible implementation manners of the third aspect and the fourth aspect may be referred to the technical effects brought about by the different implementation manners of the second aspect and the first aspect, and the technical effects brought about by the fifth aspect may be referred to the technical effects brought about by the different implementation manners of the first aspect, which are not described herein.
Drawings
Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
Fig. 2 is a schematic structural diagram of a chip package structure according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a chip stacking structure according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a chip according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a chip according to another embodiment of the present application;
FIG. 6 is a schematic diagram of a chip according to another embodiment of the present application;
FIG. 7 is a schematic diagram of a chip according to still another embodiment of the present application;
Fig. 8 is a schematic structural diagram of a chip stacking structure according to another embodiment of the present application;
fig. 9 is a schematic structural view of a chip stacking structure according to still another embodiment of the present application;
fig. 10 is a schematic structural view of a chip stacking structure according to still another embodiment of the present application;
FIG. 11 is a flowchart of a method for fabricating a chip according to an embodiment of the present application;
Fig. 12 is a schematic diagram of a chip in a method for manufacturing a chip according to another embodiment of the present application;
Fig. 13 is a schematic diagram of a second chip in a method for manufacturing a chip according to another embodiment of the present application;
fig. 14 is a schematic diagram of a chip in a method for manufacturing a chip according to another embodiment of the present application;
Fig. 15 is a schematic diagram of a chip in a method for manufacturing a chip according to another embodiment of the present application;
fig. 16 is a schematic diagram of a chip in a method for manufacturing a chip according to another embodiment of the present application;
Fig. 17 is a schematic diagram of a chip in a method for manufacturing a chip according to another embodiment of the present application;
Fig. 18 is a schematic diagram of a second chip in the method for manufacturing a chip according to another embodiment of the present application;
fig. 19 is a schematic diagram of a chip in a method for manufacturing a chip according to another embodiment of the present application;
Fig. 20 is a schematic diagram of a chip in a method for manufacturing a chip according to another embodiment of the present application;
Fig. 21 is a schematic diagram of a chip in a method for manufacturing a chip according to another embodiment of the present application;
Fig. 22 is a schematic diagram of a second chip in the method for manufacturing a chip according to another embodiment of the present application;
Fig. 23 is a schematic diagram of a chip in a method for manufacturing a chip according to still another embodiment of the present application;
Fig. 24 is a schematic diagram of a chip in a method for manufacturing a chip according to still another embodiment of the present application;
Fig. 25 is a schematic diagram showing a chip structure in a method for manufacturing a chip according to still another embodiment of the present application;
Fig. 26 is a schematic diagram of a chip in a method for manufacturing a chip according to another embodiment of the present application.
Detailed Description
The technical solutions of the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be single or multiple. In addition, in the embodiments of the present application, the words "first", "second", and the like do not limit the number and order.
Furthermore, in the embodiments of the present application, the terms "upper," "lower," and the like, are defined with respect to the orientation in which the components in the drawings are schematically disposed, and it should be understood that these directional terms are relative concepts, which are used for description and clarity with respect thereto, and which may be correspondingly varied according to the variation in the orientation in which the components in the drawings are disposed.
In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment of the present application is not to be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
The technical scheme in the embodiment of the present application will be described below with reference to the accompanying drawings.
The embodiment of the application provides electronic equipment. The electronic device may include a mobile phone (mobile phone), a tablet computer (pad), a television, an intelligent wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (vitual reality, VR) device, an augmented reality (augmented reality, AR) device, etc., and the embodiment of the present application does not limit the specific form of the electronic device.
As an example, referring to fig. 1, an embodiment of the present application provides a schematic structural diagram of the electronic device, where the electronic device 10 includes a printed circuit board (printed circuit board, PCB) 12 and a chip package structure 11, and the chip package structure 11 is electrically connected to the PCB12, so that the chip package structure 11 can be interconnected with other chips or other modules on the PCB 12. For example, referring to fig. 1, an electrical connection structure c1 is further disposed between the chip package structure 11 and the PCB12, and the electrical connection structure c1 may be a ball array (ball GRID ARRAY, BGA), where the chip package structure 11 is specifically electrically connected to the PCB12 through the electrical connection structure c 1.
Referring to fig. 2, fig. 2 illustrates a chip package structure 11, where the chip package structure 11 includes a package substrate 30 and a chip stack structure 20 configured based on a three-dimensional (three dimensional, 3D) stack package technology, the chip package structure 11 is electrically connected to a PCB12, specifically, the package substrate 30 in the chip package structure 11 is electrically connected to the PCB12, and the chip stack structure 20 includes two or more vertically stacked chips, and the chip stack structure 20 is electrically connected to the package substrate 30. For example, referring to fig. 2, an electrical connection structure C2 is further disposed between the chip stacking structure 20 and the package substrate 30, where the electrical connection structure C2 may be a micro bump (uBump), or may be a controllable collapse chip connection pad (controlled collapse chip connection, abbreviated as C4), and the chip stacking structure 20 is specifically electrically connected to the package substrate 30 through the electrical connection structure C2.
As an example, referring to fig. 3, an embodiment of the present application provides a cross-sectional view of a chip stacking structure 20, referring to fig. 3, the chip stacking structure 20 includes a plurality of stacked chips, including a chip 21 and a chip 22, the chip 22 is disposed above the chip 21 according to the placement position of the chip stacking structure 20 shown in fig. 3, the chip 21 includes a wafer 210 and a dielectric layer 211 disposed on one side of the wafer 210, and specifically, the dielectric layer 211 is disposed below the wafer 210. The chip 22 includes a wafer 220 and a dielectric layer 221 disposed on one side of the wafer 220, specifically, the dielectric layer 221 is disposed below the wafer 220, the wafer 210 is disposed between the dielectric layer 211 and the dielectric layer 221, and the dielectric layer 221 is disposed between the wafer 210 and the wafer 220. The wafer 210 is further provided with a through silicon via (through silicon via, TSV) 213, a metal line 214 and a dielectric layer 215 disposed between the metal line 214 and the wafer 210 are disposed in the through silicon via 213, one end of the metal line 214 is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21, and the other end of the metal line 214 is electrically connected to the metal wiring 222 in the dielectric layer 221 of the chip 22.
For example, taking the chip 21 as an illustration, some electronic components are typically disposed in the wafer 210 in the chip 21, for example, one electronic component EC is shown in fig. 3, where the electronic components disposed in the wafer 210 include a capacitor, a resistor, a diode (diode), a triode (bipolar junction transistor, BJT), a metal-oxide-semiconductor field effect transistor (MOSFET), and the like. One or more metal wires are often disposed in the dielectric layer 211 disposed on one side of the wafer 210, and the one or more metal wires are electrically connected with electronic components disposed in the wafer 210 in the chip 21 to form a circuit structure, and generally, the active surface of the chip 21 is a surface of the dielectric layer 211 of the chip 21 away from the wafer 210, and the passive surface of the chip 21 is a surface of the wafer 210 of the chip 21 away from the dielectric layer 211. In some embodiments, the dielectric layer 211 of the chip 21 and the one or more metal wires disposed in the dielectric layer 211 are also referred to as a redistribution layer (redistribution layer, RDL).
For example, referring to fig. 3, according to the placement position of the chip stacking structure 20 shown in fig. 3, in which the metal wiring 212 in the dielectric layer 211 is electrically connected to the electronic component disposed in the wafer 210 in the chip 21, and the dielectric layer 211 is located below the wafer 210, then the active surface of the chip 21 is located below the dielectric layer 211, and the passive surface of the chip 21 is located above the wafer 210; since the metal wiring in the dielectric layer 221 is electrically connected to the electronic components provided in the wafer 220 in the chip 22, and the dielectric layer 221 is located under the wafer 220, the active surface of the chip 22 is located under the dielectric layer 211, and the passive surface of the chip 22 is located above the wafer 210. In addition, since wafer 210 is disposed between dielectric layer 211 and dielectric layer 221 is disposed between wafer 210 and wafer 220, the active surface of chip 22 is bonded to the passive surface of chip 21, which is also referred to as a face-to-back bond. Since the through-silicon via 213 penetrating the wafer 210 is further disposed in the wafer 210, and one end of the metal line 214 in the through-silicon via 213 is electrically connected to the metal line 212 in the dielectric layer 211 of the chip 21, and the other end of the metal line 214 in the through-silicon via 213 is electrically connected to the metal line 222 in the dielectric layer 221 of the chip 22, the signal received by the active surface of the chip 21 may be transmitted to the active surface of the chip 22 through the metal line 212 and the metal line 214 in the through-silicon via 213, and then transmitted to the electronic component disposed in the wafer 220 of the chip 22 through the metal line 222 in the dielectric layer 221 of the chip 22, or the signal received by the active surface of the chip 22 may be transmitted to the active surface of the chip 21 through the metal line 222 and the metal line 214 in the through-silicon via 213, and then transmitted to the circuit structure formed by the electronic component disposed in the wafer 210 of the chip 21 through the metal line 212 in the dielectric layer 211 of the chip 21. That is, by providing the metal line 214 in the through silicon via 213, the chip 21 and the chip 22 can communicate signals.
In the chip stacking structure 20 shown in fig. 3, when the metal line 214 in the through silicon via 213 enables the chip 21 and the chip 22 to communicate with each other through signals, since the dielectric layer 215 is further disposed between the metal line 214 and the wafer 210, the metal line 214 and the dielectric layer 215 form a capacitor C, one electrode of the capacitor C is the metal line 214, the other electrode of the capacitor C is the wafer 210, and the dielectric material of the capacitor C is the dielectric layer 215. The existence of the capacitor C causes a larger parasitic capacitance between the metal line 214 in the through silicon via 213 and the electronic component EC disposed in the wafer 210 of the chip 21, and the parasitic capacitance may affect the normal operation of the electronic component EC, where the parasitic capacitance may increase the resistive-capacitive delay (RESISTANCE CAPACITANCE DELAY, RC delay) of the chip 21, thereby affecting the signal transmission performance of the chip 21.
Therefore, as shown in fig. 4, the embodiment of the present application provides a chip, and when the via hole in the chip 21 passes through the ac signal, parasitic capacitance generated between the metal line in the via hole and the electronic component disposed in the wafer of the chip 21 is smaller, so that the signal transmission performance of the chip 21 is improved. Fig. 4 (a) is a top view of the chip 21, and fig. 4 (b) is a cross-sectional view of the chip 21 along AA' shown in fig. 4 (a).
In the chip 21 shown in fig. 4, a wafer 210 is included. The chip 21 further includes a dielectric layer 211 disposed on one side of the wafer 210, where one or more metal wires are disposed in the dielectric layer 211, only one metal wire 212 is shown in fig. 4, the metal wires in the dielectric layer 211 are electrically connected with electronic components disposed in the wafer 210 of the chip 21 to form a circuit structure, the active surface of the chip 21 is a surface of the dielectric layer 211 of the chip 21 away from the wafer 210, and the passive surface of the chip 21 is a surface of the wafer 210 of the chip 21 away from the dielectric layer 211. Specifically, according to the placement position of the chip 21 shown in fig. 4, the dielectric layer 211 is located below the wafer 210, so that the active surface of the chip 21 is located below the dielectric layer 211.
The wafer 210 is provided with a via 213, a metal line 214 is provided in the via 213, and a dielectric layer 215 is provided between the metal line 214 and the wafer 210. Illustratively, referring to fig. 4, the metal line 214 in the via 213 is electrically connected to the metal line 212 in the dielectric layer 211, and the via 213 penetrates the wafer 210, in which case, when the chip 21 shown in fig. 4 and the chip 22 shown in fig. 3 are bonded in a face-to-back bonding manner, one end of the metal line 214 in the via 213 is electrically connected to the metal line 212 in the dielectric layer 211, and the other end of the metal line 214 in the via 213 is electrically connected to the metal line 222 in the dielectric layer 221. In other embodiments, the via 213 shown in fig. 4 may not extend through the wafer 210, and for example, when one electronic component is disposed in the wafer 210, one end of the metal line 214 in the via 213 may be electrically connected to the metal wiring 212 in the dielectric layer 211, and the other end of the metal line 214 in the via 213 may be electrically connected to the electronic component disposed in the wafer 210.
Illustratively, the material of the metal line 214 includes copper, tungsten, and the material of the metal line 214 is a conductive material, and signals can only be transmitted through the metal line 214 in the via 213 when the material of the metal line 214 is a conductive material. The via 213 is generally configured as a cylinder, and the diameter of the cylindrical via 213 is 1 micron or more. In other embodiments, the via 213 may be further configured as a prism, and the bottom surface of the via 213 configured as a prism may be any polygon, and the side length of the any polygon may be 1 micrometer or more. In some embodiments, the bottom surface of the metal line 214 in the via 213 is circular. In other embodiments, the bottom surface of the metal line 214 in the via 213 is annular.
Illustratively, when the material of wafer 210 includes silicon, vias 213 are also commonly referred to as through-silicon vias. In other embodiments, the material of wafer 210 may further include: gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), embodiments of the present application are not limited to the material of wafer 210. Illustratively, dielectric layer 215 typically uses an insulating material, and in some embodiments, the material of dielectric layer 215 includes silicon dioxide, silicon nitride, etc., and dielectric layer 215 may insulate metal line 214 from wafer 210 as metal line 214 in via 213 passes a signal.
Also included in wafer 210 is spacer 216 surrounding via 213, spacer 216 having a dielectric constant less than the dielectric constant of the material of dielectric layer 215. Illustratively, referring to fig. 4, the bottom surface of spacer 216 is annular, for example, may be annular or polygonal, spacer 216 surrounds via 213, and spacer 216 is not in contact with via 213.
Illustratively, referring to fig. 4, when via 213 penetrates wafer 210, spacer 216 surrounds via 213, and spacer 216 also penetrates wafer 210, wherein wafer 210 may be separated into wafer region 210a and wafer region 210b by providing spacer 216, wherein via 213 is provided in wafer region 210a and electronic component is provided in wafer region 210b, illustratively, electronic component EC is illustrated in fig. 4, wherein electronic component EC may be separated from via 213 by providing spacer 216. In some embodiments, the distance between spacer 216 and via 213 is 0.5 microns or greater and the ring width of the bottom surface of spacer 216 is 0.1 microns or greater and 1 micron or less. That is, when the width of the wafer region 210a between the spacer 216 and the via hole 213 is sufficiently small, it is possible to ensure that the wafer region 210a has no electronic component EC therein, and to minimize the waste of the effective area of the wafer.
In some embodiments, when wafer 210 includes two or more vias 213, then the wafer also includes a plurality of spacer rings, one surrounding each via 213. In other embodiments, when wafer 210 includes two or more vias 213, then one or more spacer rings may be included in the wafer, wherein one spacer ring surrounds two or more vias 213.
In some embodiments, the material of the dielectric layer 215 is silicon dioxide or silicon nitride, wherein the dielectric constant of silicon dioxide is approximately equal to 3.9. The dielectric constant of spacer 216 is less than the dielectric constant of the material of dielectric layer 215, wherein spacer 216 may be made from one or more of the following materials: siLK, carbon doped silica, hydrogen Silses Quioxane (HSQ), METHYL SILSES Quinone (MSQ), and Nanoglass. Wherein SiLK is a low dielectric constant material, and is widely used in chip production at present, siLK is a high molecular material with a dielectric constant of 2.6; carbon doped silicon oxide has a dielectric constant of about 2.4 to 2.7; the dielectric constant of HSQ can reach 2.9; MSQ is a silicon-based high polymer material, and the dielectric constant can reach 2.2; the dielectric constant of Nanoglass can reach 1.3.
In the case of the via hole in the chip 21 shown in fig. 4 passing an ac signal, since the dielectric layer 215 is disposed between the metal line 214 in the via hole 213 and the wafer 210, the metal line 214 in the via hole 213, the wafer 210 and the dielectric layer 215 form a capacitor C1, wherein one electrode of the capacitor C1 is the metal line 214 in the via hole 213, the other electrode of the capacitor C1 is the wafer 210, specifically the wafer region 210a, the dielectric material between the two electrodes of the capacitor C1 is the dielectric layer 215, and in addition, since the isolating ring 216 surrounds the via hole 213, the isolating ring 216 and the wafer 210 on both sides of the isolating ring 216 form a capacitor C2, wherein one electrode of the capacitor C2 is the wafer 210 on one side of the isolating ring 216, specifically the wafer region 210a, and the other electrode of the capacitor C2 is the wafer 210 on the other side of the isolating ring 216, in particular, in the wafer region 210b, the dielectric material between the two electrodes of the capacitor C2 is the spacer 216, where, since the dielectric constant of the spacer 216 is smaller than that of the material of the dielectric layer 215, the capacitance value of the capacitor C2 will be smaller than that of the capacitor C1, and then, when the signal is transmitted through the via 213, it is equivalent to connecting the capacitor C1 and the capacitor C2 in series between the metal line 214 of the via 213 and the electronic component EC provided in the wafer 210 of the chip 21, and the equivalent capacitance after the series is C, c= (C1 x C2)/(c1+c2), that is, 1/c= (1/C1) + (1/C2), it is seen that after connecting the capacitor C1 and the capacitor C2 in series, the parasitic capacitance between the metal line 214 of the via 213 and the electronic component EC provided in the wafer 210 of the chip 21 can be reduced, and further, the signal transmission performance of the chip 21 is improved.
Referring to fig. 5, based on the chip 21 shown in fig. 4, in the chip 21 shown in fig. 5, the spacer 216 further includes an air gap 217, where, for example, when the spacer is manufactured, the spacer trench is etched by an etching process, the spacer material is deposited by chemical vapor deposition (chemical vapor deposition, CVD) in the trench in the spacer, and since the bottom surface of the spacer 216 is in a circular shape, the circular ring has a ring width of 0.1 μm or more and 1 μm or less, and therefore, the spacer trench has a ring width of 0.1 μm or more and 1 μm or less, when the spacer material is deposited by chemical vapor deposition in the spacer trench with such a size, the deposited spacer material is attached to the bottom and the sidewall of the spacer trench, and the opening of the spacer trench is sealed, and thus, the spacer 216 includes the air gap 217. Since the dielectric constant of air in the air gap 217 is 1, the capacitance of the capacitor C2 will be smaller, further reducing the parasitic capacitance between the metal line 214 in the via 213 and the electronic component EC disposed in the wafer 210 of the chip 21.
Where air gap 217 is also included in spacer 216, spacer 216 may also be made of silicon dioxide or silicon nitride. Since the spacer 216 made of silicon dioxide or silicon nitride has the air gap 217 formed therein, the dielectric constant of the spacer 216 is also lower than that of silicon dioxide or silicon nitride.
Illustratively, the material of dielectric layer 211 includes silicon dioxide, silicon nitride. The material of dielectric layer 215 includes silicon dioxide, nitridation. The material of the dielectric layer 211 may be the same as that of the dielectric layer 215, or the material of the dielectric layer 211 may be different from that of the dielectric layer 215, which is not limited in the embodiment of the present application.
In other embodiments, the material of spacer 216, the material of dielectric layer 215, and the material of dielectric layer 211 may all be the same and use silicon dioxide, which is not limited in embodiments of the present application.
Illustratively, referring to fig. 6, in addition to the chip 21 shown in fig. 5, in the chip 21 shown in fig. 6, the wafer 210 further includes: the spacer ring 218 surrounding the spacer ring 216 has a dielectric constant that is less than the dielectric constant of the material of the dielectric layer 215. Illustratively, referring to FIG. 6, when via 213 extends through wafer 210, spacer 216 surrounds via 213, and spacer 216 also extends through wafer 210, spacer 218 extends around spacer 216, and spacer 218 also extends through wafer 210, wherein electronic component EC may be separated from via 213 by providing spacer 216 and spacer 218.
In some embodiments, the material of dielectric layer 215 is silicon dioxide, which has a dielectric constant equal to about 3.9. The dielectric constant of the spacer 218 is less than the dielectric constant of the material of the dielectric layer 215, wherein the spacer 218 may be made of one or more of the following materials: siLK, carbon doped silica, hydrogen Silses Quioxane (HSQ), METHYL SILSES Quinone (MSQ), and Nanoglass.
Since the spacer ring 218 surrounds the spacer ring 216, the spacer ring 218 and the wafers 210 on both sides of the spacer ring 218 will also form a capacitor C3, wherein one electrode of the capacitor C3 is the wafer 210 on one side of the spacer ring 218, the other electrode of the capacitor C3 is the wafer 210 on the other side of the spacer ring 218, and the dielectric material between the two electrodes of the capacitor C3 is the spacer ring 218, wherein the dielectric constant of the spacer ring 218 is smaller than that of the dielectric layer 215, so the capacitance value of the capacitor C3 will be smaller than that of the capacitor C1, and then, when the signal is transmitted through the metal line 214 in the via 213, the equivalent capacitance between the metal line 214 of the via 213 and the electronic component EC provided in the wafer 210 of the chip 21 is reduced again, so that the parasitic capacitance between the metal line 214 of the via 213 and the electronic component EC provided in the wafer 210 of the chip 21 is reduced, and the signal transmission performance of the chip 21 is higher.
Referring to fig. 7, based on the chip 21 shown in fig. 6, the spacer ring 218 further includes an air gap 219 in the chip 21 shown in fig. 7, wherein, for example, when the spacer ring is manufactured, the spacer ring trench is etched by an etching process, the spacer ring material is deposited in the spacer ring trench by chemical vapor deposition (chemical vapor deposition, CVD), and the bottom surface of the spacer ring 218 is in a circular ring shape, and the ring width of the circular ring is 0.1 μm or more and 1 μm or less, so that the ring width of the spacer ring trench is 0.1 μm or more and 1 μm or less, and when the spacer ring material is deposited in the spacer ring trench with such a size by chemical vapor deposition, the deposited spacer ring material is attached to the bottom and the side wall of the spacer ring trench, and the opening of the spacer ring trench is sealed, so that the spacer ring 218 includes the air gap 219. Since the dielectric constant of air in the air gap 219 is 1, the capacitance of the capacitor C3 will be smaller, further reducing the equivalent capacitance between the metal line 214 in the via 213 and the electronic component EC disposed in the wafer 210 of the chip 21.
Where the spacer 218 also includes an air gap 219, the spacer 218 may also be made of silicon dioxide or silicon nitride. Since the spacer 218 made of silicon dioxide or silicon nitride has the air gap 219 formed therein, the dielectric constant of the spacer 218 is also lower than that of silicon dioxide or silicon nitride.
The embodiment of the present application further provides a chip stacking structure, for example, may be the chip stacking structure 20 shown in fig. 3, where the chip stacking structure 20 includes a plurality of chips disposed in a stacked manner, and the plurality of chips disposed in a stacked manner include the chip 21 shown in any one of fig. 4 to 7, for example, the chip 21 in the chip stacking structure 20 shown in fig. 3 may be replaced with the chip 21 shown in any one of fig. 4 to 7.
Exemplarily, referring to the chip stack structure 20 shown in fig. 8, in the chip stack structure 20 shown in fig. 8, a plurality of chips stacked and disposed include a chip 21 and a chip 22; the chip 21 includes a dielectric layer 211 disposed on one side of the wafer 210; the chip 22 includes a dielectric layer 221 disposed on one side of the wafer 220; among the plurality of stacked chips, the wafer 210 of the chip 21 is disposed between the dielectric layer 211 of the chip 21 and the dielectric layer 221 of the chip 22, and the dielectric layer 211 of the chip 21 is disposed between the wafer 210 of the chip 21 and the wafer 220 of the chip 22; one end of the metal line 214 of the chip 21 is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21, and the other end of the metal line 214 of the chip 21 is electrically connected to the metal wiring 222 in the dielectric layer 221 of the chip 22.
By way of example, the chip stack structure 20 shown in fig. 8 may be applied to a high bandwidth memory (high bandwidth memory, HBM), or to a dynamic random access memory (dynamic random access memory, DRAM), or to a complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) image sensor (CMOS image sensor, CIS), or to a NAND flash (NANDFlash), etc., to which embodiments of the present application are not limited.
The chip 21 shown in fig. 8 is exemplified by the chip 21 shown in fig. 5, however, the chip 21 in the chip stack structure 20 shown in fig. 8 may be the chip 21 shown in fig. 4, fig. 6 or fig. 7, and the embodiment of the present application is not limited thereto.
In other embodiments, the chip 22 in the chip stacking structure 20 shown in fig. 8 may be the chip 21 shown in any one of fig. 4 to 7, which is not limited by the embodiment of the present application.
For example, referring to fig. 8, according to the placement position of the chip stacking structure 20 shown in fig. 8, in which one or more metal wires are disposed in the dielectric layer 211, only one metal wire 212 is shown in fig. 8, and the metal wires in the dielectric layer 211 are electrically connected to the electronic components disposed in the wafer 210 in the chip 21 to form a circuit structure, then, when the dielectric layer 211 is located under the wafer 210, the active surface of the chip 21 is located under the dielectric layer 211; one or more metal wirings are provided in the dielectric layer 221, only one metal wiring 222 is shown in fig. 8, and the metal wiring in the dielectric layer 221 is electrically connected with an electronic component provided in the wafer 210 in the chip 22 to form a circuit structure, so that when the dielectric layer 221 is located under the wafer 220, the active surface of the chip 22 is located under the dielectric layer 221. In addition, since the wafer 210 of the chip 21 is disposed between the dielectric layer 211 of the chip 21 and the dielectric layer 221 of the chip 22 and the dielectric layer 211 of the chip 21 is disposed between the wafer 210 of the chip 21 and the wafer 220 of the chip 22, the active surface of the chip 22 is bonded to the passive surface of the chip 21, and this bonding method is also called face-to-back bonding. One end of the metal line 214 in the via 213 is electrically connected to the metal line 212 in the dielectric layer 211 in the chip 21, and the other end of the metal line 214 in the via 213 is electrically connected to the metal line 222 in the dielectric layer 221 in the chip 22, so that the signal received by the active surface of the chip 21 can be transmitted to the active surface of the chip 22 through the metal line 212 and the metal line 214 in the via 213, and further transmitted to the electronic component disposed in the wafer 220 of the chip 22 through the metal line 222 in the dielectric layer 221 of the chip 22; or the signal received by the active surface of the chip 22 can be transmitted to the active surface of the chip 21 through the metal wiring 222 and the metal line 214 in the via hole 213, and then transmitted to the electronic component arranged in the wafer 210 of the chip 21 through the metal wiring 212 in the dielectric layer 211 of the chip 21. That is, by providing the metal wiring 214 in the via hole 213, signal communication between the chip 21 and the chip 22 can be achieved.
For example, referring to fig. 8, in some embodiments, in order to enable face-to-back bonding between the chip 22 and the chip 21, a dielectric layer 100 is often further disposed between the active surface of the chip 22 and the passive surface of the chip 21, where the dielectric layer 100 is used as a bonding layer of a fusion bonding (fusion bonding) process to achieve a fixed connection between the chip 22 and the chip 21, and metal lines 214 in vias 213 penetrate through the dielectric layer 100 and electrically connect with metal wires 222.
For example, in other embodiments, a dielectric layer may be disposed on the passive surface of the chip 21, where the dielectric layer is used to protect the wafer 210 on the passive surface of the chip 21, and then, when the active surface of the chip 22 is bonded to the passive surface face-to-back of the chip 21, the metal line 214 in the via 213 is electrically connected to the metal line 222 through the dielectric layer disposed on the passive surface of the chip 21. In other embodiments, when a dielectric layer is disposed on the passive surface of the chip 21, a metal wire may be disposed in the dielectric layer, and the metal wire 214 in the via 213 may or may not be electrically connected to the metal wire in the dielectric layer, which is not limited in the embodiment of the present application.
The chips 21 in the chip stack structure 20 shown in fig. 8 may be, for example, die (die) or chip wafer; the chips 22 in the chip stack 20 may be die (also referred to as particles or bare chips) or chip wafers. Illustratively, after epitaxial layers are grown on wafers (die), chip wafers may be formed and diced to obtain die (die). Referring to fig. 8, the chip 21 may be a die, the chip 22 may be a die, and such a structure may be referred to as die-to-die bonding (D2 Dbonding); alternatively, referring to fig. 8, the chip 21 may be a chip wafer, the chip 22 may be a chip wafer, and such a structure may be referred to as wafer-to-wafer bonding (W2W bonding); alternatively, as shown in fig. 8, the chip 21 may be a chip wafer, the chip 22 may be a die, and such a structure may be referred to as die-to-wafer bonding (D2W bonding). The embodiments of the present application are not limited in this regard.
In other embodiments, reference is made to fig. 9, wherein in the chip stack structure 20 shown in fig. 9, a plurality of chips arranged in a stack include a chip 21 and a chip 22; the chip 21 includes a dielectric layer 211 disposed on one side of the wafer 210; the chip 22 includes a dielectric layer 221 disposed on one side of the wafer 220; among the plurality of stacked chips, the dielectric layer 221 of the chip 22 and the dielectric layer 211 of the chip 21 are disposed between the wafer 210 of the chip 21 and the wafer 220 of the chip 22; one end of the metal wiring 214 of the chip 21 is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21, and the metal wiring 212 in the dielectric layer 211 of the chip 21 is electrically connected to the metal wiring 222 in the dielectric layer 221 of the chip 22.
The chip 21 shown in fig. 9 is exemplified by the chip 21 shown in fig. 5, however, the chip 21 in the chip stack structure 20 shown in fig. 9 may be the chip 21 shown in fig. 4, fig. 6 or fig. 7, and the embodiment of the present application is not limited thereto.
In other embodiments, the chip 22 in the chip stacking structure 20 shown in fig. 9 may also be the chip 21 shown in any one of fig. 4 to 7, which is not limited by the embodiment of the present application.
As an example, referring to fig. 9, according to the placement position of the chip stacking structure 20 shown in fig. 9, in which one or more metal wires are disposed in the dielectric layer 211, only one metal wire 212 is shown in fig. 9, and the metal wires in the dielectric layer 211 are electrically connected to the electronic components disposed in the wafer 210 in the chip 21 to form a circuit structure, then, when the dielectric layer 211 is located above the wafer 210, the active surface of the chip 21 is located above the dielectric layer 211; one or more metal wirings are provided in the dielectric layer 221, only one metal wiring 222 is shown in fig. 9, and the metal wiring 222 in the dielectric layer 221 is electrically connected with an electronic component provided in the wafer 220 in the chip 22 to form a circuit structure, so that when the dielectric layer 221 is located under the wafer 220, the active surface of the chip 22 is located under the dielectric layer 221. Since the dielectric layer 221 of the chip 22 and the dielectric layer 211 of the chip 21 are disposed between the wafer 210 of the chip 21 and the wafer 220 of the chip 22, the active surface of the chip 22 is bonded to the active surface of the chip 21, and the bonding method is also called face-to-face bonding. One end of the metal line 214 in the via 213 is electrically connected to the metal wire 212 in the dielectric layer 211, and the metal wire 212 in the dielectric layer 211 is electrically connected to the metal wire 222 in the dielectric layer 221, so that a signal received by the active surface of the chip 21 may be transmitted to the active surface of the chip 22 through the metal wire 212, and then transmitted to an electronic component disposed in the wafer 220 of the chip 22 through the metal wire 222 in the dielectric layer 221 of the chip 22, or a signal received by the active surface of the chip 22 may be transmitted to the active surface of the chip 21 through the metal wire 222, and then transmitted to a circuit structure formed by the electronic component disposed in the wafer 210 of the chip 21 through the metal wire 212 in the dielectric layer 211 of the chip 21. That is, it means that signal communication can be achieved between the chip 21 and the chip 22. When some signals are transmitted to the active surface of the chip 21 through the passive surface of the chip 21, the signals are transmitted to the active surface of the chip 21 through the metal lines 214 in the vias 213, and then transmitted to the electronic components arranged in the wafer 210 of the chip 21 through the metal wires 212 in the dielectric layer 211 of the chip 21, and as the signals can be communicated with the chip 22, the signals transmitted to the active surface of the chip 21 through the passive surface of the chip 21 can also be transmitted to the active surface of the chip 22.
For example, referring to fig. 9, in some embodiments, in order to enable face-to-face bonding between the chip 22 and the chip 21, a dielectric layer 100 is often further disposed between the active surface of the chip 22 and the active surface of the chip 21, where the dielectric layer 100 is used as a bonding layer of a fusion bonding (fusion bonding) process to achieve a fixed connection between the chip 22 and the chip 21, and the metal wiring 212 in the dielectric layer 211 and the metal wiring 222 in the dielectric layer 221 are electrically connected through the dielectric layer 100.
In other embodiments, referring to fig. 10, in which a plurality of chips are stacked in the chip stack structure 20 shown in fig. 10, the chips 21a and 21b are included; the chip 21a includes a dielectric layer 211 disposed on one side of the wafer 210; the chip 22b includes a dielectric layer 211 disposed on one side of the wafer 210; among the plurality of stacked chips, the wafer 220 of the chip 22 and the wafer 210 of the chip 21 are disposed between the dielectric layer 211 of the chip 21 and the dielectric layer 221 of the chip 22; one end of the metal wiring 214 of the chip 21a is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21a, one end of the metal wiring 214 of the chip 21b is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21b, and the other end of the metal wiring 214 of the chip 21a is electrically connected to the other end of the metal wiring 214 of the chip 21 b.
The chip 21a shown in fig. 10 is exemplified by the chip 21 shown in fig. 5, however, the chip 21a in the chip stack structure 20 shown in fig. 10 may be the chip 21 shown in fig. 4, fig. 6 or fig. 7, and the embodiment of the present application is not limited thereto. The chip 21b shown in fig. 10 is described by taking the chip 21 shown in fig. 5 as an example, however, the chip 21b in the chip stack structure 20 shown in fig. 10 may be the chip 21 shown in fig. 4, fig. 6 or fig. 7, and the embodiment of the present application is not limited thereto.
As an example, referring to fig. 10, according to the placement position of the chip stacking structure 20 shown in fig. 10, in which one or more metal wirings are disposed in the dielectric layer 211 of the chip 21a, only one metal wiring 212 is shown in fig. 10, and the metal wiring 212 in the dielectric layer 211 of the chip 21a is electrically connected to an electronic component disposed in the wafer 210 in the chip 21a to form a circuit structure, then, when the dielectric layer 211 of the chip 21a is located under the wafer 210 of the chip 21a, the active surface of the chip 21a is located under the dielectric layer 211 of the chip 21 a; one or more metal wirings are provided in the dielectric layer 221 of the chip 21b, only one metal wiring 212 is shown in fig. 10, and the metal wiring in the dielectric layer 211 of the chip 21b is electrically connected to an electronic component provided in the wafer 210 of the chip 21b to form a circuit structure, so that when the dielectric layer 211 of the chip 21b is located above the wafer 210 of the chip 21b, the active surface of the chip 21b is located above the dielectric layer 211 of the chip 21 b. Since wafer 220 of chip 22 and wafer 210 of chip 21 are disposed between dielectric layer 211 of chip 21 and dielectric layer 221 of chip 22, the passive surface of chip 21b is bonded to the passive surface of chip 21a, which is also referred to as back-to-back bonding. One end of the metal line 214 of the chip 21a is electrically connected to the metal line 212 in the dielectric layer 211 of the chip 21a, one end of the metal line 214 of the chip 21b is electrically connected to the metal line 212 in the dielectric layer 211 of the chip 21b, and the other end of the metal line 214 of the chip 21a is electrically connected to the other end of the metal line 214 of the chip 21b, so that the signal received by the active surface of the chip 21a may be transmitted to the active surface of the chip 21b through the metal line 212 of the chip 21a, the metal line 214 in the via 213 of the chip 21a, and the metal line 214 in the via 213 of the chip 21b, and further transmitted to the circuit structure formed by the electronic component provided in the wafer 210 of the chip 21b through the metal line 212 in the dielectric layer 211 of the chip 21b, or the signal received by the active surface of the chip 21b may be transmitted to the active surface of the chip 21a through the metal line 212 of the metal line 214 in the via 213 of the chip 21b, and further transmitted to the electronic component provided in the wafer 210 of the chip 21 b. That is, it means that the signal communication between the chip 21a and the chip 21b can be achieved by the metal line 214 in the via 213 of the chip 21a and the metal line 214 in the via 213 of the chip 21 b.
For example, referring to fig. 10, in some embodiments, in order to enable back-to-back bonding between the chip 21a and the chip 21b, a dielectric layer 100 is often further disposed between the passive surface of the chip 21b and the passive surface of the chip 21a, where the dielectric layer 100 is used as a bonding layer in a fusion bonding (fusion bonding) process to achieve a fixed connection between the chip 21b and the chip 21 a. The metal line 214 in the via 213 of the chip 21b is electrically connected to the metal line 214 in the via 213 of the chip 21a through the dielectric layer 100, and/or the metal line 214 in the via 213 of the chip 21a is electrically connected to the metal line 214 in the via 213 of the chip 21b through the dielectric layer 100.
For example, in the chip stacking structure 20 shown in any one of fig. 8 to fig. 10, the chip stacking structure 20 may include a plurality of chips arranged in a stacked manner, where a face-to-back bond, a face-to-face bond, or a back-to-back bond may be used between two adjacent chips in the plurality of chips arranged in a stacked manner, which is not limited in the embodiments of the present application.
Exemplary, referring to fig. 11, an embodiment of the present application provides a method for manufacturing a chip, including:
s101, forming a via hole in the wafer.
For example, referring to fig. 12, a dielectric layer 211 may be formed on one side of a wafer 210, one or more metal wirings may be formed in the dielectric layer 211, and fig. 12 illustrates only one metal wiring 212, wherein the metal wirings in the dielectric layer 211 are electrically connected with electronic components disposed in the wafer 210 of a chip 21 to form a circuit structure. Specifically, the active surface of the chip 21 is the surface of the dielectric layer 211 of the chip 21 away from the wafer 210, and the passive surface of the chip 21 is the surface of the wafer 210 of the chip 21 away from the dielectric layer 211.
Illustratively, in some embodiments, the active surface of the chip 21 may be used as a working surface, and the via hole is formed in the wafer 210 of the chip 21; in other embodiments, the passive surface of the chip 21 may be used as a working surface, and the via hole may be formed in the wafer 210 of the chip 21. When the bonding mode between the chip 21 and the chip adjacent to the chip 21 is determined to be a face-to-back bonding, a face-to-face bonding or a back-to-back bonding, when the chip 21 and other chips are stacked, it is determined whether the active surface of the chip 21 is used as a working surface, the via hole is formed in the wafer 210 of the chip 21, or the passive surface of the chip 21 is used as a working surface, and the via hole is formed in the wafer 210 of the chip 21. The embodiments of the present application are not limited in this regard.
In other embodiments, vias may be formed on the chip 21, and then the bonding manner between the chip 21 and the chip adjacent to the chip 21 may be determined, and then the bonding step between the chip 21 and the chip adjacent to the chip 21 may be performed. For example, referring to fig. 12, fig. 12 illustrates that a passive surface of a chip 21 is used as a working surface, and a via hole is formed in a wafer 210 of the chip 21.
For example, when forming the via hole, firstly, the substrate portion of the wafer 210 of the chip 21 exposed on the passive surface of the chip 21 needs to be thinned to a required thickness to facilitate subsequent operations, and secondly, the dielectric layer 61 needs to be deposited on the passive surface of the chip 21 to protect the substrate of the wafer 210 exposed on the passive surface of the chip 21, to avoid electrically connecting the wafer 210 with the metal line when the material of the metal line is deposited subsequently, or to avoid etching through the electronic component disposed in the wafer 210 when the isolation ring trench or the via hole trench is etched, so as to cause failure of the electronic component.
Again, on the passive side of the chip 21, a photoresist 62 is fabricated covering the passive side of the chip 21, which photoresist 62 may be a positive photoresist or a negative photoresist. Specifically, when the dielectric layer 61 is deposited on the passive surface of the chip 21, it is necessary to fabricate the photoresist 62 covering the dielectric layer 61 on the passive surface of the chip 21.
Subsequently, the photoresist 62 is subjected to photolithography to form a via opening 63, wherein the via opening 63 is specifically circular.
As shown in fig. 13, the chip 21 is etched (etched) through the via opening 63 shown in fig. 12, and the dielectric layer 61, the wafer 210 of the chip 21, and a part of the dielectric layer 211 need to be etched, so that a via 213 shown in fig. 13 is formed, wherein the via 213 is in contact with the metal wiring 212. In some embodiments, when forming the via 213, a two-step etching process is often performed, where the etching stop layer of the first step is the dielectric layer 211, and the etching stop layer of the second step is the metal wiring 212, so that the etched via 213 contacts the metal wiring 212 through the two-step etching process. For example, the etching generally takes an isotropic etching mode, and in the second etching process, the thickness of the dielectric layer 211 smaller than the thickness of the dielectric layer 61 and larger than the thickness of the dielectric layer 211 above the metal wiring 212 is especially guaranteed, so that the etching process is sequentially prevented from affecting the electronic components in the wafer 210.
Illustratively, because the via opening is circular, the formed via 213 is generally cylindrical and the diameter of the cylindrical via 213 is 1 micron or more. In other embodiments, the via opening may be configured as a polygon, and then the formed via 213 may be prismatic, and the shape of the via 213 is not limited by embodiments of the present application.
S102, forming a metal line and a first dielectric layer in the via hole.
Illustratively, a dielectric layer material is deposited by chemical vapor deposition (chemical vapor deposition, CVD) in the via 213 shown in fig. 13, wherein the dielectric layer material comprises silicon dioxide, silicon nitride, etc., and further a dielectric layer 215 (i.e., the first dielectric layer described above) is formed on the sidewalls of the via 213.
Subsequently, a material of the metal line is deposited in the via 213 where the dielectric layer 215 is formed, and the metal line 214 in the via 213 is formed, that is, the dielectric layer 215 is located between the metal line 214 and the wafer 210. As shown in fig. 14, a metal line 214 is formed by depositing a metal line material in the via hole 213 in fig. 14, in which the dielectric layer 215 is formed, and exemplary metal line materials include copper, tungsten, and the like. In some embodiments, the bottom surface of the metal line 214 in the via 213 is circular. In other embodiments, the bottom surface of the metal line 214 in the via 213 is circular. The shape of the metal line 214 is not limited by the embodiment of the present application.
Illustratively, in other embodiments, after the metal line 214 is formed, a dielectric layer material is deposited on the surface of the metal line 214 to protect the metal on the surface of the metal line 214. It is also possible to perform a metal connection process later so that the metal line 214 can be electrically connected with other metal wirings.
S103, forming a first isolation ring, wherein the first isolation ring surrounds the via hole, and the dielectric constant of the first isolation ring is smaller than that of the material of the first dielectric layer.
Illustratively, referring to fig. 15, with the passive side of the chip 21 as the working side, a photoresist 65 covering the passive side of the chip 21 is fabricated again on the passive side of the chip 21, and the photoresist 65 may be a positive photoresist or a negative photoresist. Specifically, when the dielectric layer 61 is deposited on the passive surface of the chip 21, it is necessary to fabricate the photoresist 65 covering the dielectric layer 61 on the passive surface of the chip 21.
Subsequently, the photoresist 65 is subjected to photolithography to form a spacer ring window 66, wherein the spacer ring window 66 is in particular circular.
As shown in fig. 16, the spacer trench 67 shown in fig. 16 is formed by etching (etch) the chip 21 through the spacer window 66 shown in fig. 15, which requires etching through the dielectric layer 61 and the wafer 210. When the isolation ring trench 67 is etched, an etching stop layer of the etching process is a dielectric layer 211.
Spacer material is deposited in spacer trench 67 shown in fig. 16 to form spacer 216 (i.e., the first spacer described above). Illustratively, the isolation ring trench has a ring width of 0.1 microns or more and 1 micron or less.
Illustratively, in forming the structure of spacer 216 shown in FIG. 4, spacer 216 may be prepared by depositing one or more of the following materials in spacer trench 67 shown in FIG. 16: siLK, carbon doped silica, hydrogen Silses Quioxane (HSQ), METHYL SILSES Quinone (MSQ), and Nanoglass. In forming the spacer 216 shown in fig. 5, the spacer 216 may be formed by depositing silicon dioxide or silicon nitride in the spacer groove 67 shown in fig. 16, and the spacer groove 67 may have a width of 0.1 μm or more and 1 μm or less, and when silicon dioxide or silicon nitride is deposited by chemical vapor deposition in the spacer groove 67 having such a size, the deposited silicon dioxide or silicon nitride may adhere to the bottom and the sidewall of the spacer groove 67 and may be sealed at the opening of the spacer groove 67, and thus the spacer 216 may include the air gap 217.
In some embodiments, a spacer ring 218 may be manufactured around spacer ring 216, for example, to form chip 21 as shown in fig. 6, which is not limited by the embodiment of the present application.
Illustratively, in other embodiments, the chip stack structure 20 shown in fig. 10 may be formed by selecting steps S101 to S103 to fabricate a second chip including a via hole and then bonding the second chip to the chip 21. Or a second chip not including a via is fabricated and then bonded to the chip 21 to form the chip stack structure 20 shown in fig. 8 or 9. The specific steps of bonding the two chips refer to the existing chip bonding technology, for example, a dielectric layer is arranged between the two chips as a bonding layer of a fusion bonding process, and the embodiment of the application is not limited to this.
The chip stacking structure includes a plurality of chips stacked in a stacking manner, wherein two adjacent chips in the plurality of chips stacked in a stacking manner can be face-to-back bonded, face-to-face bonded or back-to-back bonded, and the embodiment of the application is not limited thereto.
For example, the step of fabricating the via holes may be performed before the electronic components provided in the wafer of the chip 21 are fabricated, or may be performed while the electronic components provided in the wafer of the chip 21 are fabricated, or may be performed after the electronic components provided in the wafer of the chip 21 are fabricated. The embodiments of the present application are not limited in this regard.
In the above method for manufacturing the chip 21, the via hole is first manufactured and then the spacer is manufactured. In other embodiments, referring to fig. 17 to 20, in the method for manufacturing the chip 21, the dielectric layer 215 and the spacer 216 between the metal line 214 in the via 213 and the wafer 210 may be manufactured simultaneously.
For example, referring to fig. 17, a dielectric layer 211 may be formed on one side of a wafer 210, one or more metal wirings may be formed in the dielectric layer 211, and fig. 17 illustrates only one metal wiring 212, wherein the metal wirings in the dielectric layer 211 are electrically connected with electronic components disposed in the wafer of a chip to form a circuit structure. The active side of the chip 21 is the side of the dielectric layer 211 away from the wafer 210, and the passive side of the chip 21 is the side of the wafer 210 away from the dielectric layer 211.
Fig. 17 shows that a passive surface of the chip 21 is used as a working surface, and a via hole is formed in the wafer 210 of the chip 21.
For example, when forming the via hole, firstly, the substrate portion of the wafer 210 of the chip 21 exposed on the passive surface of the chip 21 needs to be thinned to a required thickness to facilitate subsequent operations, and secondly, the dielectric layer 71 needs to be deposited on the passive surface of the chip 21 to protect the substrate of the wafer 210 exposed on the passive surface of the chip 21, to avoid electrically connecting the wafer 210 with the metal line when the material of the metal line is deposited subsequently, or to avoid etching through the electronic component disposed in the wafer 210 when the isolation ring trench or the via hole trench is etched, so as to cause failure of the electronic component.
Again, on the passive side of the chip 21, a photoresist 72 is fabricated covering the passive side of the chip 21, the photoresist 72 may be a positive photoresist or a negative photoresist. Specifically, when the dielectric layer 71 is deposited on the passive surface of the chip 21, it is necessary to fabricate a photoresist 72 covering the dielectric layer 71 on the passive surface of the chip 21.
Subsequently, the photoresist 72 is subjected to photolithography to form a via opening 73 and a spacer opening 74, wherein the via opening 73 is specifically circular, the spacer opening 74 is specifically circular, and the spacer opening 74 bypasses the via opening 73.
As shown in fig. 18, the chip 21 is etched (etched) through the via opening 73 shown in fig. 17, and the dielectric layer 71 and the wafer 210 of the chip 21 need to be etched through, to form the via trench 75 shown in fig. 18, wherein the via trench 75 is not in contact with the metal wiring 212. As shown in fig. 18, the spacer trench 76 shown in fig. 18 is formed by etching (etch) the chip 21 through the spacer window 74 shown in fig. 17, requiring etching through the dielectric layer 71 and the wafer 210 of the chip 21. Illustratively, in etching to form via trench 75 and isolation ring trench 76, the etch stop layer of the etching process is dielectric layer 211.
Illustratively, referring to fig. 19, silicon dioxide or silicon nitride is deposited in the via trench 75 and the spacer trench 76 shown in fig. 18 by chemical vapor deposition, and then a dielectric layer 215 is formed on the sidewall of the via trench 75, and a spacer 216 is formed in the spacer trench 76, wherein the ring width of the spacer trench is equal to or greater than 0.1 micrometer and equal to or less than 1 micrometer, the diameter of the fabricated via trench is equal to or greater than 1 micrometer, and the same chemical vapor deposition may enable the formation of the spacer 216 to include an air gap 217 based on the dimensional difference between the via trench and the spacer trench.
Referring to fig. 20, etching is performed in the via trench 75 in which the dielectric layer 215 is formed on the sidewall shown in fig. 19, and the etching stop layer is the metal wiring 212, so as to form the metal wiring trench 77, wherein the metal wiring trench 77 is in contact with the metal wiring 212.
The chip 21 shown in fig. 5 can be formed by depositing a metal wiring material in the metal wiring trench 77 shown in fig. 20 to form a metal wiring 214. Exemplary metal wiring materials include copper, tungsten, and the like.
Illustratively, in other embodiments, after forming the metal line 214, a dielectric layer material is deposited on the surface of the metal line 214 to protect the metal on the surface of the metal line 214. It is also possible to perform a metal connection process later so that the metal line 214 can be electrically connected with other metal wirings.
In other embodiments, referring to fig. 21 to 26, in the method for manufacturing the chip 21, the spacer ring may be manufactured first and then the via hole may be manufactured.
For example, a dielectric layer 211 may be formed on one side of a wafer 210, one or more metal wirings may be formed in the dielectric layer 211, and fig. 21 shows only one metal wiring 212, wherein the metal wirings in the dielectric layer 211 are electrically connected to electronic components disposed in the wafer of the chip to form a circuit structure. The active side of the chip 21 is the side of the dielectric layer 211 away from the wafer 210, and the passive side of the chip 21 is the side of the wafer 210 away from the dielectric layer 211.
Fig. 21 shows that a passive surface of the chip 21 is used as a working surface, and a via hole and a spacer are formed in a wafer 210 of the chip 21.
For example, when forming the via hole and the isolation ring, firstly, the substrate portion of the wafer 210 of the chip 21 exposed on the passive surface of the chip 21 needs to be thinned to a required thickness to facilitate subsequent operations, and secondly, the dielectric layer 81 needs to be deposited on the passive surface of the chip 21 to protect the substrate of the wafer 210 exposed on the passive surface of the chip 21, so as to avoid electrically connecting the wafer 210 with the metal line when the material of the metal line is subsequently deposited, or avoid etching through the electronic component disposed in the wafer 210 when the isolation ring trench or the via hole trench is etched, thereby causing failure of the electronic component. Illustratively, in the above steps, dielectric layer 61, dielectric layer 71, and dielectric layer 81 are the same material layers formed in different fabrication steps.
Again, on the passive side of the chip 21, a photoresist 82 is fabricated covering the passive side of the chip 21, which photoresist 82 may be a positive photoresist or a negative photoresist. Specifically, when the dielectric layer 81 is deposited on the passive surface of the chip 21, it is necessary to fabricate the photoresist 82 covering the dielectric layer 81 on the passive surface of the chip 21.
Subsequently, the photoresist 82 is subjected to photolithography to form the spacer ring-shaped window 83, wherein the spacer ring-shaped window 83 is in particular circular ring-shaped.
As shown in fig. 22, the spacer trench 84 shown in fig. 22 is formed by etching (etching) the chip 21 through the spacer window 83 shown in fig. 21, which requires etching through the dielectric layer 81 and the wafer 210. Illustratively, in etching to form the isolation ring trench 84, the etch stop layer of the etching process is the dielectric layer 211.
Illustratively, referring to FIG. 23, spacer ring 216 is formed by depositing spacer ring material by chemical vapor deposition in spacer ring trench 84 shown in FIG. 22.
Illustratively, in forming the structure of spacer 216 shown in FIG. 4, spacer 216 may be prepared by depositing one or more of the following materials in spacer trench 84 shown in FIG. 22: siLK, carbon doped silica, hydrogen Silses Quioxane (HSQ), METHYL SILSES Quinone (MSQ), and Nanoglass. In forming the spacer 216 shown in fig. 5, silicon dioxide or silicon nitride may be deposited in the spacer trench 84 shown in fig. 22, and the spacer trench 84 has a ring width of 0.1 μm or more and 1 μm or less, and when silicon dioxide or silicon nitride is deposited in the spacer trench 84 having such a size by chemical vapor deposition, the deposited silicon dioxide or silicon nitride adheres to the bottom and the sidewall of the spacer trench 84, and seals at the opening of the spacer trench, so that the spacer 216 may include the air gap 217. Wherein an air gap 217 is included in spacer 216 shown in fig. 23.
Illustratively, referring to fig. 24, on the passive side of the chip 21, a photoresist 85 is fabricated covering the passive side of the chip 21, and the photoresist 85 may be a positive photoresist or a negative photoresist. Specifically, when the dielectric layer 81 is deposited on the passive surface of the chip 21, it is necessary to fabricate the photoresist 85 covering the dielectric layer 81 on the passive surface of the chip 21.
Subsequently, the photoresist 85 is subjected to photolithography to form a via opening 86, wherein the via opening 86 is specifically circular.
As shown in fig. 25, the chip 21 is etched (etched) through the via opening 86 shown in fig. 24, and the dielectric layer 81 and the wafer 210 need to be etched through, to form the via trench 87 shown in fig. 25, wherein the via trench 87 is not in contact with the metal wiring 212.
Illustratively, referring to fig. 26, a dielectric layer material is deposited in the via trench 87 shown in fig. 25 by chemical vapor deposition, wherein the dielectric layer material includes silicon dioxide, silicon nitride, and the like, and further a dielectric layer 215 (i.e., the first dielectric layer described above) is formed on the sidewall of the via trench 87.
Referring to fig. 26, the via trench 87 having the dielectric layer 215 formed on the sidewall is etched, and the metal wiring 212 is used as the etch stop layer, so as to form the metal wiring trench 88, wherein the metal wiring trench 88 is in contact with the metal wiring 212.
The chip 21 shown in fig. 5 can be formed by depositing a material of a metal wiring in the metal wiring trench 88 shown in fig. 26 to form a metal wiring 214. Exemplary metal wiring materials include copper, tungsten, and the like.
Illustratively, in other embodiments, after the metal line 214 is formed, a dielectric layer material is deposited on the surface of the metal line 214 to protect the metal on the surface of the metal line 214. It is also possible to perform a metal connection process later so that the metal line 214 can be electrically connected with other metal wirings.
Although the application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (16)

1. A chip, comprising:
A wafer;
the wafer is provided with a via hole, a metal circuit is arranged in the via hole, and a first dielectric layer is arranged between the metal circuit and the wafer;
The wafer also comprises a first isolation ring surrounding the via hole, and the dielectric constant of the first isolation ring is smaller than that of the material of the first dielectric layer.
2. The chip of claim 1, wherein the chip comprises a plurality of chips,
The first spacer ring includes an air gap therein.
3. The chip according to claim 1 or 2, wherein,
The wafer also comprises a second isolation ring surrounding the first isolation ring, and the dielectric constant of the second isolation ring is smaller than that of the material of the first dielectric layer.
4. The chip of claim 3, wherein the chip comprises a plurality of chips,
The second isolating ring includes an air gap therein.
5. The chip according to any one of claim 1 to 4, wherein,
The distance between the first isolation ring and the via hole is more than or equal to 0.5 micrometer.
6. The chip according to any one of claim 1 to 5, wherein,
The ring width of the first isolation ring is more than or equal to 0.1 micron and less than or equal to 1 micron.
7. The chip of any of claims 1-6, wherein the via has a diameter of 1 micron or greater.
8. The chip of any one of claims 1-7, wherein the material of the metal lines comprises copper, tungsten.
9. The chip of any one of claims 1-8, further comprising a second dielectric layer disposed on one side of the wafer, the metal lines electrically connected to metal wiring in the second dielectric layer.
10. A chip stack structure, wherein the chip stack structure includes a plurality of chips disposed in a stack, and the plurality of chips disposed in a stack include the chips as set forth in any one of claims 1 to 9.
11. The chip stacking structure as recited in claim 10, wherein,
The plurality of chips arranged in a stacked manner comprise a first chip and a second chip;
the first chip and the second chip both comprise a second dielectric layer arranged on one side of the wafer;
In the plurality of stacked chips, a wafer of the first chip is arranged between a second dielectric layer of the first chip and a second dielectric layer of the second chip, and the second dielectric layer of the first chip is arranged between the wafer of the first chip and the wafer of the second chip;
One end of the metal line of the first chip is electrically connected with the metal wiring in the second dielectric layer of the first chip, and the other end of the metal line of the first chip is electrically connected with the metal wiring in the second dielectric layer of the second chip.
12. The chip stacking structure as recited in claim 10, wherein,
The plurality of chips arranged in a stacked manner comprise a first chip and a second chip;
the first chip and the second chip both comprise a second dielectric layer arranged on one side of the wafer;
In the plurality of chips stacked, the second dielectric layer of the second chip and the second dielectric layer of the first chip are arranged between the wafer of the first chip and the wafer of the second chip;
One end of the metal line of the first chip is electrically connected with the metal wiring in the second dielectric layer of the first chip, and the metal wiring in the second dielectric layer of the first chip is electrically connected with the metal wiring in the second dielectric layer of the second chip.
13. The chip stacking structure as recited in claim 10, wherein,
The plurality of chips arranged in a stacked manner comprise a first chip and a second chip;
the first chip and the second chip both comprise a second dielectric layer arranged on one side of the wafer;
in the plurality of chips stacked, a wafer of the second chip and a wafer of the first chip are arranged between a second dielectric layer of the first chip and a second dielectric layer of the second chip;
One end of the metal line of the first chip is electrically connected with the metal wiring in the second dielectric layer of the first chip, one end of the metal line of the second chip is electrically connected with the metal wiring in the second dielectric layer of the second chip, and the other end of the metal line of the first chip is electrically connected with the other end of the metal line of the second chip.
14. A chip package structure, characterized by comprising a package substrate and the chip stack structure according to any one of claims 10-13; the chip stacking structure is electrically connected with the packaging substrate.
15. An electronic device comprising a printed circuit board and the chip package structure of claim 14; the package substrate in the chip package structure is electrically connected with the printed circuit board.
16. A method of manufacturing a chip, comprising:
forming a via in a wafer;
Forming a metal circuit and a first dielectric layer in the via hole, wherein the first dielectric layer is positioned between the metal circuit and the wafer;
A first isolation ring is formed, wherein the first isolation ring surrounds the via hole, and the dielectric constant of the first isolation ring is smaller than that of the material of the first dielectric layer.
CN202211345283.4A 2022-10-31 2022-10-31 Chip, chip stacking structure, chip packaging structure and electronic equipment Pending CN117995795A (en)

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US8647920B2 (en) * 2010-07-16 2014-02-11 Imec Vzw Method for forming 3D-interconnect structures with airgaps
US8766409B2 (en) * 2011-06-24 2014-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for through-silicon via (TSV) with diffused isolation well
KR101880155B1 (en) * 2011-12-22 2018-07-19 에스케이하이닉스 주식회사 Stacked semiconductor package having the same
CN104241249B (en) * 2013-06-21 2017-03-22 中芯国际集成电路制造(上海)有限公司 Silicon through hole interconnection structure and manufacturing method thereof
CN111968954B (en) * 2020-08-27 2022-07-01 武汉新芯集成电路制造有限公司 Semiconductor device and method for manufacturing the same

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