CN111968695A - Method, circuit, storage medium and terminal for reducing area of high-capacity non-flash memory - Google Patents
Method, circuit, storage medium and terminal for reducing area of high-capacity non-flash memory Download PDFInfo
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- CN111968695A CN111968695A CN202011132629.3A CN202011132629A CN111968695A CN 111968695 A CN111968695 A CN 111968695A CN 202011132629 A CN202011132629 A CN 202011132629A CN 111968695 A CN111968695 A CN 111968695A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
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Abstract
The invention discloses a method, a circuit, a storage medium and a terminal for reducing the area of a high-capacity non-type Flash memory.
Description
Technical Field
The present invention relates to the field of circuit technologies, and in particular, to a method, a circuit, a storage medium, and a terminal for reducing the area of a high-capacity non-flash memory.
Background
In the design process of the NOR Flash chip, the feasibility of packaging needs to be considered, the width-to-length ratio or the aspect ratio of a chip wafer generally cannot be larger than 2.5:1, and FIG. 1 is a layout diagram corresponding to main modules of serial NOR Flash chips with the storage capacity of 64Mbit, 32Mbit, 16Mbit and 8 Mbit.
As can be seen from fig. 1, when the storage capacity of the serial NOR Flash is less than or equal to 64Mbit, the serial NOR Flash with the capacity of less than 64Mbit can use the same architecture, and the aspect ratio and the width-to-length ratio of the chip die are less than 2.5:1, so that the requirement of packaging is met.
However, it is obvious that the architecture of fig. 1 cannot be used in the serial NOR Flash with a memory capacity of 128Mbit or more (if the architecture of fig. 1 is used, the aspect ratio is close to 5:1, which is not suitable for mass production packaging, and the reliability of packaging wire bonding is not guaranteed, thereby affecting the function and performance of the chip). Fig. 2 is a layout diagram corresponding to the main modules of the 128Mbit serial NOR Flash.
Because the width of each 8Mbit memory block is long (around 1350um in 65nm technology), if the left memory block (8 Mbit-0-8 Mbit-7) and the right memory block (8 Mbit-8 Mbit-15) in FIG. 2 multiplex the same sense amplifier, the metal traces connecting the memory cells to the sense amplifier are very different for the leftmost memory cell and the rightmost memory cell, and 3000um (as shown in FIG. 3), which may cause the characteristics of the leftmost memory cell and the rightmost memory cell to be greatly different during data reading, and may even cause data reading errors when the clock frequency is high.
Because the peripheral digital logic needs to take data from the data latches and process it for output to the IO pins of the chip, the data latches can be multiplexed between the left and right sense amplifiers, but the data connections between the left and right sense amplifiers and the data latches need to be added, taking 128 sense amplifiers on the left and right as an example, 128 data latches correspond to 128 sense amplifiers on the left and right, 256 data lines crossing the horizontal direction of the chip are formed between the 128 sense amplifiers on the left and right and the 128 data latches (128 x2, please refer to the schematic diagram of fig. 4), on a 65nm NOR Flash process node, the wire channels occupied by the wires are about 66um and about 2.2% of the area of a 65nm 128Mbit serial NOR Flash chip, the chip area of the 128Mbit serial NOR Flash is increased by 2.2%, and the cost of the chip at a wafer manufacturing end is directly increased.
Therefore, it is necessary to reduce the chip area of the high-capacity NOR Flash to reduce the cost of the chip on the wafer manufacturing side.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a method, a circuit, a storage medium and a terminal for reducing the area of a high-capacity non-Flash memory, which can reduce the area of a high-capacity NOR Flash chip so as to reduce the cost of the chip at a wafer manufacturing end.
The technical scheme of the invention is as follows: a method for reducing the area of a high-capacity non-flash memory specifically comprises the following steps:
reading data of a sensitive amplifier in NOR Flash;
latching the read data by a data latch corresponding to the sense amplifier;
and buffering the data latched by the data latch through a data output buffer supporting three states.
A circuit employing the method of reducing the area of a high capacity non-flash memory as described above, comprising:
a sense amplifier for storing data;
a data latch for latching data;
a data output buffer for buffering data;
reading data in a sensitive amplifier, latching the read data through a data latch corresponding to the sensitive amplifier, buffering the data latched by the data latch through a data output buffer supporting three states, and finally outputting the data to a digital logic circuit.
The circuit, wherein, the data output buffer adopts a three-state data output buffer.
The circuit of, wherein the output terminals of the data output buffers are connected together.
The circuit, wherein, the quantity that sensitive amplifier, data latch and data output buffer set up is unanimous and the one-to-one connection.
A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform the method described above.
A terminal device, comprising a processor and a memory, wherein the memory stores a computer program, and the processor is used for executing the method by calling the computer program stored in the memory.
The invention has the beneficial effects that: the invention provides a method, a circuit, a storage medium and a terminal for reducing the area of a high-capacity non-type Flash memory, which are characterized in that data of a sense amplifier are read, then are latched by respective data latches, and are cached by a data output buffer capable of supporting tristate.
Drawings
FIG. 1 is a layout diagram corresponding to the main modules of a serial NOR Flash chip with the storage capacity of 64Mbit, 32Mbit, 16Mbit and 8Mbit in the prior art.
Fig. 2 is a layout diagram corresponding to the main modules of a 128Mbit serial NOR Flash in the prior art.
FIG. 3 is a schematic diagram of a prior art left and right memory block multiplexing the same sense amplifiers and data latches.
Fig. 4 is a schematic diagram showing the connection relationship and layout of a sense amplifier, a data latch and a digital logic circuit corresponding to fig. 2 in the prior art.
FIG. 5 is a flow chart of the steps of the method of reducing the area of a high capacity non-flash memory according to the present invention.
Fig. 6 is a schematic diagram of the circuit of the present invention.
FIG. 7 is a schematic circuit diagram of the left and right sense amplifiers of the present invention.
FIG. 8 is a diagram illustrating address transition and output control timing corresponding to FIG. 7 according to the present invention.
Fig. 9 is a schematic diagram of a terminal in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 5, a method for reducing the area of a high capacity non-flash memory specifically includes the following steps:
s1: reading data of a sensitive amplifier in NOR Flash;
s2: latching the read data through a data latch corresponding to the sense amplifier;
s3: the data latched by the data latch is buffered by a data output buffer supporting three states (high level, low level, high impedance state is called three states).
As shown in fig. 6, a circuit adopting the method for reducing the area of the high capacity non-flash memory as described above includes:
a sense amplifier for storing data;
a data latch for latching data;
a data output buffer for buffering data;
reading data in the sensitive amplifier, latching the read data through a data latch corresponding to the sensitive amplifier, buffering the data latched by the data latch through a data output buffer supporting three states, and finally outputting the data to the digital logic circuit.
In some embodiments, the outputs of the data output buffers are connected together.
In some embodiments, the sense amplifiers, data latches, and data output buffer arrangements are uniform in number and connected in a one-to-one correspondence.
In the technical scheme, data of the sense amplifier is read, then the data is latched through respective data latches (because the area of a chip occupied by the data latches is small and can be almost ignored), and the data is buffered through a data output buffer capable of supporting tristate, because tristate (high level, low level and high resistance state are called tristate) can be supported, the outputs of the data output buffer can be connected together (fig. 6 is a connection relation and a layout schematic diagram of the sense amplifier, the data latches and a digital logic circuit of the framework provided by the invention), and it can be obviously seen that data connecting lines crossing the horizontal direction of the chip after the technical scheme is adopted are sharply reduced: by taking the left and right 128 sense amplifiers as an example, the left and right 128 sense amplifiers correspond to the left and right 128 data latches, and it can be seen that after the technical scheme is adopted, the data connecting lines crossing the horizontal direction of the chip are reduced from the traditional 256 to 128, the wiring channels occupied by the wiring channels are reduced from 66um to 33um in the traditional scheme, and the chip area of the 128Mbit serial NOR Flash is about 1.1% occupied, even if a group of data latches (namely 128 data latches are added), for the 128Mbit serial NOR Flash chip, the chip area is increased by about 1.2% -1.3% in total, and compared with the traditional scheme, the chip area is saved by about 0.9% -1%, the cost of the chip at the wafer manufacturing end is reduced, and the cost advantage of the chip is improved.
In order to illustrate that the output terminals of all the data output buffers proposed by the present embodiment are shorted together to reduce the chip area and operate normally, fig. 7 is used to illustrate, where a sense amplifier, a data latch, and an output data buffer are taken as an example.
When the address of the read operation is switched between left and right addresses, if no special processing is performed, the address switch is switched from left to right, the data on the data bus (DXX) is fetched from the data in the right corresponding data latch, but the data output to IOPAD should still be the data in the left corresponding data latch, and the address transition and output control timing diagram refers to fig. 8 (Flash _ addr refers to the Flash address signal, SA _ en _ L/R refers to the left/right sense amplifier enable signal, SA _ latch _ L/R refers to the left/right data storage signal, and SA _ outer _ L/R refers to the left/right output data buffer enable signal). The left output data buffer and the right output data buffer are only enabled by one at the same time, so that the output of the left output data buffer and the right output data buffer does not have the conflict condition and can work normally.
Referring to fig. 9, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.
In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: reading data of a sensitive amplifier in NOR Flash; latching the read data through a data latch corresponding to the sense amplifier; and buffering the data latched by the data latch through a data output buffer supporting three states.
Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.
An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: reading data of a sensitive amplifier in NOR Flash; latching the read data through a data latch corresponding to the sense amplifier; and buffering the data latched by the data latch through a data output buffer supporting three states. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (7)
1. A method for reducing the area of a high-capacity non-flash memory is characterized by comprising the following steps:
reading data of a sensitive amplifier in NOR Flash;
latching the read data by a data latch corresponding to the sense amplifier;
and buffering the data latched by the data latch through a data output buffer supporting three states.
2. A circuit employing the method of reducing area of a high capacity non-flash memory of claim 1, comprising:
a sense amplifier for storing data;
a data latch for latching data;
a data output buffer for buffering data;
reading data in a sensitive amplifier, latching the read data through a data latch corresponding to the sensitive amplifier, buffering the data latched by the data latch through a data output buffer supporting three states, and finally outputting the data to a digital logic circuit.
3. The circuit of claim 2, wherein the data output buffer is a tri-state data output buffer.
4. The circuit of claim 2, wherein the outputs of the data output buffers are connected together.
5. The circuit of claim 2, wherein the sense amplifiers, data latches, and data output buffer arrangements are provided in equal numbers and in a one-to-one correspondence.
6. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of claim 1.
7. A terminal device, characterized in that it comprises a processor and a memory, in which a computer program is stored, said processor being adapted to execute the method of claim 1 by calling said computer program stored in said memory.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011132629.3A CN111968695A (en) | 2020-10-21 | 2020-10-21 | Method, circuit, storage medium and terminal for reducing area of high-capacity non-flash memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011132629.3A CN111968695A (en) | 2020-10-21 | 2020-10-21 | Method, circuit, storage medium and terminal for reducing area of high-capacity non-flash memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112542195A (en) * | 2020-12-30 | 2021-03-23 | 深圳市芯天下技术有限公司 | Circuit for reducing area of nonvolatile flash memory chip and nonvolatile flash memory chip |
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Application publication date: 20201120 |