CN111966285B - Method, main control chip and system for storing data into EEPROM - Google Patents

Method, main control chip and system for storing data into EEPROM Download PDF

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CN111966285B
CN111966285B CN202010700257.3A CN202010700257A CN111966285B CN 111966285 B CN111966285 B CN 111966285B CN 202010700257 A CN202010700257 A CN 202010700257A CN 111966285 B CN111966285 B CN 111966285B
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data
stored
data storage
storage page
eeprom
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CN111966285A (en
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操四胜
刘启武
赵寰
张明勇
赵勇
周广飞
郎胡彭
王映娟
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Sichuan Hongmei Intelligent Technology Co Ltd
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Sichuan Hongmei Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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  • Read Only Memory (AREA)

Abstract

The invention provides a method, a main control chip and a system for storing data to an EEPROM, wherein the method comprises the following steps: the method comprises the steps of receiving a data storage instruction used for indicating data storage to a target EEPROM, determining a first data storage page and a starting storage position for storing the data to be stored in the target EEPROM, determining a second data amount capable of being stored in each data storage page of the target EEPROM according to a model parameter, determining a third data amount capable of being stored in the first data storage page according to the second data amount and the starting storage position, dividing the data to be stored into at least one data block according to the first data amount, the second data amount and the third data amount, and storing the at least one data block to at least one data storage page in the EEPROM from the first data storage page to finish the data storage to the EEPROM. The execution efficiency of the main control chip can be improved.

Description

Method, main control chip and system for storing data into EEPROM
Technical Field
The invention relates to the technical field of data storage, in particular to a method, a main control chip and a system for storing data into an EEPROM.
Background
With the vigorous development in the field of electronic technology, Electrically Erasable-Read-Only-Memory (EEPROM) has been widely used in household appliances. EEPROM is a semiconductor memory device that can be electronically rewritten many times, and existing information can be erased on a computer or a dedicated device, and new data can be reprogrammed, and the EEPROM generally includes several models, 24c02, 24c04, 24c08, 24c16, 24c32, and 24c 64. The operation of data storage on the external EEPROM usually has two modes of 'byte writing' and 'page writing', wherein the data format of the 'byte writing' mode is the same for any model of EEPROM, and the flow of the software control writing EEPROM operation is relatively simple; the data format of the page writing mode is different according to different models of the EEPROM, and the flow of the software control writing EEPROM is complex. Software designers basically use a "byte write" approach to write data to external EEPROMs.
At present, based on the prior art of writing in bytes, chinese patent application No. CN201911397192.3 discloses a method for simulating an EEPROM using a nonvolatile technology norflash, which simulates a small-capacity EEPROM by using a large-capacity norflash in a chip, and stores frequently modified data traffic in the simulated EEPROM.
The method of simulating an EEPROM using norflsh disclosed in the above patent is based on a "byte write" operation. However, one write operation in the "Byte write" mode can only write one Byte data, the operation needs to be stopped after each write operation, and if the write operation needs to be continued, the write operation in the "Byte write" mode needs to be restarted again to write the next Byte data. If the data written into the EEPROM is large, the writing operation of the EEPROM occupies a large amount of time resources of the main chip, thereby affecting the execution efficiency of the main chip.
Disclosure of Invention
The invention provides a method, a main control chip and a system for storing data in an EEPROM (electrically erasable programmable read-only memory), which can improve the execution efficiency of the main control chip.
In a first aspect, an embodiment of the present invention provides a method for storing data in an EEPROM, including:
receiving a data storage instruction for indicating to store data to a target EEPROM, wherein the data storage instruction comprises a model parameter and a first data volume, the model parameter is used for indicating the model of the target EEPROM, and the first data volume is used for representing the data volume of the data to be stored;
determining a first data storage page and a starting storage position for storing the data to be stored in the target EEPROM, wherein the first data storage page is a data storage page for starting to store the data to be stored, and the starting storage position is a storage position for starting to store the data to be stored in the first data storage page;
determining a second data volume which can be stored in each data storage page of the target EEPROM according to the model parameter;
determining a third data volume of the data to be stored which can be stored in the first data storage page according to the second data volume and the initial storage position;
dividing the data to be stored into at least one data block according to the first data volume, the second data volume and the third data volume;
and storing the at least one data block into at least one data storage page in the EEPROM from the first data storage page, wherein the amount of data stored in each of the at least one data storage page in which the data to be stored is equal to the second amount of data except for the first data storage page and a second data storage page, and the second data storage page is the last data storage page in the EEPROM in which the data to be stored is stored.
Optionally, the dividing the data to be stored into at least one data block according to the first data volume, the second data volume, and the third data volume includes:
s201: temporarily caching the data to be stored in a target array with continuous addresses;
s202: determining an array starting address and an array terminating address of the target array, wherein the array starting address is used for identifying a starting position of the data to be stored in the target array, and the array terminating address is used for identifying a terminating position of the data to be stored in the target array;
s203: judging whether the first data volume is smaller than or equal to the third data volume, if so, executing step S204, otherwise, executing step S205;
s204: determining data between the array starting address and the array ending address in the target array as a first data block, and ending the current flow;
s205: determining data in the target array between the array start address and a first data partition address as a second data block, wherein the data amount of the second data block is equal to the third data amount;
s206: determining data between a second data partition address and the array termination address as a third data block, wherein the data amount of the third data block is less than or equal to the second data amount;
s207: if the first data partition address is different from the second data partition address, sequentially dividing data between the first data partition address and the second data partition address in the target array into at least one fourth data block, wherein the data amount of each fourth data block is equal to the second data amount.
Optionally, starting from the first data storage page, the storing the at least one data block to at least one data storage page in the EEPROM includes:
if the first data block is obtained by dividing the data to be stored, storing the first data block into the first data storage page from the initial storage position;
if the data to be stored is divided to obtain the second data block and the third data block, storing the second data block into the first data storage page from the initial storage position, and storing the third data block into a second data storage page, wherein the second data storage page is a next data storage page of the first data storage page;
if the data to be stored are divided to obtain the second data block, the third data block and the at least one fourth data block, the second data block is stored into the first data storage page from the initial storage position, the at least one fourth data block is sequentially stored into the at least one third data storage page, and the third data block is stored into a fourth data storage page, wherein the at least one third data storage page is located between the first data storage page and the fourth data storage page, the first data storage page is adjacent to one of the third data storage pages, the fourth data storage page is adjacent to one of the third data storage pages, and the third data storage pages are sequentially adjacent.
Optionally, said storing said at least one data block into at least one data storage page in said EEPROM starting from said first data storage page comprises:
and sequentially storing each data block into at least one data storage page starting from the first data storage page through an I/O port connected with the EEPROM, wherein each data block corresponds to each data storage page, any one data storage page can only contain one data block, and any one data block can only be stored into one data storage page.
In a second aspect, an embodiment of the present invention further provides a main control chip, including: the device comprises a receiving module, a first determining module, a second determining module, a third determining module, a data dividing module and a data storage module;
the receiving module is used for receiving a data storage instruction used for indicating to store data into a target EEPROM, wherein the data storage instruction comprises a model parameter and a first data volume, the model parameter is used for indicating the model of the target EEPROM, and the first data volume is used for representing the data volume of the data to be stored;
the first determining module is configured to determine a first data storage page and a starting storage location for storing the data to be stored in the target EEPROM, where the first data storage page is a data storage page where the data to be stored starts to be stored, and the starting storage location is a storage location where the data to be stored starts to be stored in the first data storage page;
the second determining module is configured to determine, according to the model parameter received by the receiving module, a second data size that can be stored in each data storage page of the target EEPROM;
the third determining module is configured to determine, according to the second data amount determined by the second determining module and the initial storage location determined by the first determining module, a third data amount of the to-be-stored data that can be stored in the first data storage page determined by the first determining module;
the data dividing module is configured to divide the data to be stored into at least one data block according to the first data amount received by the receiving module, the second data amount determined by the determining module, and the third data amount determined by the third determining module;
the data storage module is configured to store the at least one data block divided by the data dividing module into at least one data storage page in the EEPROM starting from the first data storage page determined by the first determining module, where an amount of data stored in each of the at least one data storage page in which the data to be stored is equal to the second data amount determined by the second determining module, except for the first data storage page and the second data storage page determined by the first determining module, and the second data storage page is a last data storage page in the EEPROM in which the data to be stored is stored.
Optionally, the data dividing module includes: the device comprises a cache unit, a first determining unit, a judging unit, a second determining unit, a third determining unit, a fourth determining unit and a dividing unit;
the cache unit is used for temporarily caching the data to be stored in a target array with continuous addresses;
the first determining unit is configured to determine an array start address and an array end address of the target array, where the array start address is used to identify a start position of the data to be stored in the target array, and the array end address is used to identify an end position of the data to be stored in the target array;
the judging unit is used for judging whether the first data volume is less than or equal to the third data volume;
the second determining unit is used for determining data in the target array between the array starting address and the array ending address determined by the first determining unit as a first data block;
the third determining unit is configured to determine data in the target array between the array start address and the first data partition address determined by the first determining unit as a second data block, where a data amount of the second data block is equal to the third data amount;
the fourth determining unit is configured to determine data between the second data partition address determined by the determining unit and the array termination address determined by the first determining unit as a third data block, where a data amount of the third data block is smaller than or equal to the second data amount;
the dividing unit is configured to, if the first data division address determined by the first determining unit is different from the second data division address determined by the fourth determining unit, sequentially divide data in the target array between the first data division address determined by the first determining unit and the second data division address determined by the fourth determining unit into at least one fourth data block, where the data amount of each fourth data block is equal to the second data amount.
Optionally, the data storage module includes: a first storage unit, a second storage unit and a third storage unit;
the first storage unit is configured to store the first data block determined by the second determining unit into the first data storage page from the starting storage location if the first data block determined by the second determining unit is obtained by performing division processing on the data to be stored;
the second storage unit is configured to, if the to-be-stored data is divided to obtain the second data block determined by the third determining unit and the third data block determined by the fourth determining unit, store the second data block determined by the third determining unit into the first data storage page from the starting storage position, and store the third data block determined by the fourth determining unit into a second data storage page, where the second data storage page is a data storage page next to the first data storage page;
the third storage unit is configured to, if the second data block determined by the third determination unit, the third data block determined by the fourth determination unit, and the at least one fourth data block are obtained by dividing the data to be stored, store the second data block determined by the third determination unit into the first data storage page from the initial storage location, sequentially store the at least one fourth data block into at least one third data storage page, and store the third data block determined by the fourth determination unit into a fourth data storage page, where the at least one third data storage page is located between the first data storage page and the fourth data storage page, the first data storage page is adjacent to one of the third data storage pages, and the fourth data storage page is adjacent to one of the third data storage pages, and all the third data storage pages are adjacent in sequence.
Or,
the data storage module is further configured to sequentially store each data block into at least one data storage page starting from the first data storage page determined by the first determining module through an I/O port connected to the EEPROM, where each data block corresponds to each data storage page, any one data storage page can only accommodate one data block, and any one data block can only be stored into one data storage page.
In a third aspect, an embodiment of the present invention further provides a system for storing data in an EEPROM, including: the master control chip and the target EEPROM provided in the second aspect or any possible implementation manner of the second aspect;
and the target EEPROM is used for storing the data to be stored transmitted from the main control chip according to the instruction of the main control chip.
Alternatively,
the target EEPROM is connected with the main control chip through an I/O port on the main control chip so as to finish the operation of storing the data to be stored according to the instruction of the main control chip.
According to the technical scheme, firstly, an instruction which comprises a model parameter and a first data volume and is used for indicating data storage in the target EEPROM is received, and then a first data storage page in the target EEPROM for starting to store the data to be stored and a storage position in the first data storage page for starting to store the data to be stored are determined. According to the received model parameters of the target EEPROM, a second data volume which can be contained in each storage page of the target EEPROM is determined, a third data volume which can store the data to be stored in a first data storage page of the EEPROM is determined according to the second data volume and the initial storage position of the data to be stored in the EEPROM, then data block division is carried out on the data to be stored according to the first data volume, the second data volume and the third data volume, and then the divided data blocks are sequentially stored into the corresponding data storage pages. Therefore, the data writing operation on the EPPROM according to the page is realized by the software, and the software can simultaneously and compatibly write data into different types of EEPROMs, thereby ensuring the universality of the data storage method. In addition, when the data written into the EEPROM is more, the time resources occupied by the EEPROM for storing the data can be greatly released, so that the influence on the execution of other programs is reduced, and the execution efficiency of the main control chip is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flow chart of a method of storing data in an EEPROM according to one embodiment of the invention;
FIG. 2 is a flow chart of a database partitioning method provided by an embodiment of the present invention;
fig. 3 is a schematic diagram of a main control chip according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a data partitioning module provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram of a data partitioning module and a data storage module provided by an embodiment of the invention;
FIG. 6 is a schematic diagram of a system for storing data in an EEPROM according to one embodiment of the present invention;
fig. 7 is a flowchart of another method for storing data in an EEPROM according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention, and based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a method of storing data to an EEPROM, the method including:
step 101: receiving a data storage instruction for indicating to store data to a target EEPROM, wherein the data storage instruction comprises a model parameter and a first data volume, the model parameter is used for indicating the model of the target EEPROM, and the first data volume is used for representing the data volume of the data to be stored;
step 102: determining a first data storage page and an initial storage position for storing data to be stored in a target EEPROM, wherein the first data storage page is a data storage page for starting to store the data to be stored, and the initial storage position is a storage position for starting to store the data to be stored in the first data storage page;
step 103: determining a second data volume which can be stored in each data storage page of the target EEPROM according to the model parameter;
step 104: determining a third data volume of the data to be stored which can be stored in the first data storage page according to the second data volume and the initial storage position;
step 105: dividing the data to be stored into at least one data block according to the first data volume, the second data volume and the third data volume;
step 106: and storing at least one data block into at least one data storage page in the EEPROM from a first data storage page, wherein the amount of data stored in each of the at least one data storage page storing the data to be stored is equal to a second amount of data except the first data storage page and a second data storage page, and the second data storage page is the last data storage page storing the data to be stored in the EEPROM.
In the method for storing data in the EEPROM provided by the embodiment of the present invention, an instruction including a model parameter and a first data size for instructing to store data in the target EEPROM is first received, and then a first data storage page in the target EEPROM where the data to be stored starts to be stored and a storage location in the first data storage page where the data to be stored starts to be stored are determined. According to the received model parameters of the target EEPROM, a second data volume which can be contained in each storage page of the target EEPROM is determined, a third data volume of the data to be stored which can be stored in a first data storage page of the EEPROM is determined according to the second data volume and the initial storage position of the data to be stored in the EEPROM, then data block division is carried out on the data to be stored according to the first data volume, the second data volume and the third data volume, and then the divided data blocks are sequentially stored into corresponding data storage pages. Therefore, in the method for storing data in the EEPROM, the operation of writing data into the EPPROM according to pages is realized by software, and the software can simultaneously and compatibly write data into different types of EEPROMs, thereby ensuring the universality of the method. In addition, when the data written into the EEPROM is more, the time resources occupied by the EEPROM for storing the data can be greatly released, so that the influence on the execution of other programs is reduced, and the execution efficiency of the main control chip is improved.
Optionally, on the basis of the method for storing data in the EEPROM shown in fig. 1, the data to be stored is divided into at least one data block according to the first data amount, the second data amount, and the third data amount, as shown in fig. 2, and the method includes:
step 201: temporarily caching data to be stored in a target array with continuous addresses;
step 202: determining an array starting address and an array terminating address of a target array, wherein the array starting address is used for identifying the starting position of data to be stored in the target array, and the array terminating address is used for identifying the terminating position of the data to be stored in the target array;
step 203: judging whether the first data volume is less than or equal to the third data volume, if so, executing step 204, otherwise, executing step 205;
step 204: determining data between an array starting address and an array ending address in a target array as a first data block, and ending the current flow;
step 205: determining data in the target array between the array starting address and the first data partition address as a second data block, wherein the data volume of the second data block is equal to the third data volume;
step 206: determining data between the second data partition address and the array termination address as a third data block, wherein the data volume of the third data block is less than or equal to the second data volume;
step 207: and if the first data division address is different from the second data division address, sequentially dividing the data between the first data division address and the second data division address in the target array into at least one fourth data block, wherein the data quantity of each fourth data block is equal to the second data quantity.
In the embodiment of the present invention, data to be stored is temporarily cached in an array with consecutive addresses, and a start address and an end address of the array need to be determined, then, the size of the first data volume received in step 101 and the size of the third data volume determined in step 104 are compared, if the first data volume is not greater than the third data volume, the data located between the start address and the end address in the cache array is determined as the first data block, that is, the data division is completed; if the first data volume is larger than the third data volume, determining data, of which the data volume from the starting address is equal to the third data volume, in the cache array as a second data block, then sequentially determining data, of which the data volume is equal to or smaller than the second data volume, in the rest of data as one data block, and only data block data volume, where the data corresponding to the ending address is located, can be smaller than the second data volume, so that the operation of dividing the data to be stored according to the storage page is realized. Therefore, in the whole data block dividing process, the position where the first page of the storage pages can start to be stored can be determined according to the first data volume, and therefore the flexibility of EEPROM data storage is improved. In addition, the whole data dividing operation aims at dividing data according to storage pages in the EEPROM, so that the data can be written into the target EEPROM in a data block mode according to pages.
Optionally, on the basis shown in fig. 2, the divided data blocks are stored into corresponding data storage pages. Specifically, if a first data block is obtained in the data dividing process, the data block is stored into a first data storage page from the initial position in the target EEPROM; if the second data block and the third data block are obtained in the data dividing process, storing the second data block into a first data storage page from the initial position in the target EEPROM, and then storing the third data block into a second data storage page; and if the data division simultaneously obtains a second data block, a third data block and at least one fourth data block, storing the second data block into the first data storage page from the initial position in the target EEPROM, sequentially storing each fourth data block into each third data storage page, and storing the third data block into the fourth storage page. Therefore, the process completes the operation of storing the data to be stored into the target EEPROM according to the whole page of the storage page, reduces the time resource occupied by the storage operation, and improves the execution efficiency of the main control chip.
Optionally, on the basis of the method for storing data in the EEPROM shown in fig. 1, the target EEPROM is connected through the I/O port, and each data block is sequentially stored in each corresponding storage page, so that it is only necessary to call the general write function through the main control chip, and the data to be stored can be stored in the target EEPROM in a page manner through the I/O port, which improves the execution efficiency of the main control chip and ensures the universality of the method for storing data in the EEPROM.
As shown in fig. 3, an embodiment of the present invention provides a main control chip. The method comprises the following steps: a receiving module 301, a first determining module 302, a second determining module 303, a third determining module 304, a data dividing module 305 and a data storing module 306;
the receiving module 301 is configured to receive a data storage instruction for instructing to store data to a target EEPROM, where the data storage instruction includes a model parameter and a first data volume, the model parameter is used to instruct a model of the target EEPROM, and the first data volume is used to represent a data volume of data to be stored;
a first determining module 302, configured to determine a first data storage page and a starting storage location for storing data to be stored in a target EEPROM, where the first data storage page is a data storage page where data to be stored starts to be stored, and the starting storage location is a storage location where data to be stored starts to be stored in the first data storage page;
a second determining module 303, configured to determine, according to the model parameter received by the receiving module 301, a second data amount that can be stored in each data storage page of the target EEPROM;
a third determining module 304, configured to determine, according to the second data amount determined by the second determining module 303 and the initial storage location determined by the first determining module 302, a third data amount of the data to be stored, which can be stored in the first data storage page determined by the first determining module 302;
a data dividing module 305, configured to divide the data to be stored into at least one data block according to the first data amount received by the receiving module 301, the second data amount determined by the second determining module 303, and the third data amount determined by the third determining module 304;
and a data storage module 306, configured to store, starting from the first data storage page determined by the first determining module 302, at least one data block divided by the data dividing module 305 into at least one data storage page in the EEPROM, where, except for the first data storage page and the second data storage page determined by the first determining module 302, the amount of data stored in each of the at least one data storage page storing data to be stored is equal to the second amount determined by the second determining module, and the second data storage page is the last data storage page storing data to be stored in the EEPROM.
Optionally, on the basis of the schematic diagram of the main control chip shown in fig. 3, as shown in fig. 4, the data dividing module 305 further includes: the cache unit 3051, the first determination unit 3052, the judgment unit 3053, the second determination unit 3054, the third determination unit 3055, the fourth determination unit 3056 and the division unit 3057;
the cache unit 3051 is configured to temporarily cache data to be stored in a target array with consecutive addresses;
the first determining unit 3052, configured to determine an array start address and an array end address of the target array, where the array start address is used to identify a start position of the data to be stored in the target array, and the array end address is used to identify an end position of the data to be stored in the target array;
a determination unit 3053, configured to determine whether the first data amount is smaller than or equal to the third data amount;
a second determination unit 3054, configured to determine, as the first data block, data in the target array located between the array start address and the array end address determined by the first determination unit 3052;
a third determining unit 3055, configured to determine, as a second data block, data in the target array located between the array start address determined by the first determining unit 3052 and the first data division address, where a data amount of the second data block is equal to the third data amount;
a fourth determination unit 3056, configured to determine data between the second data division address and the array termination address determined by the first determination unit 3052 as a third data block, where a data amount of the third data block is smaller than or equal to the second data amount;
a dividing unit 3057, configured to, if the first data division address determined by the first determination unit 3052 is different from the second data division address determined by the fourth determination unit 3056, sequentially divide data in the target array between the first data division address determined by the first determination unit 3052 and the second data division address determined by the fourth determination unit 3056 into at least one fourth data block, where a data amount of each fourth data block is equal to the second data amount.
Optionally, on the basis of the schematic diagram of the main control chip shown in fig. 4, as shown in fig. 5, the data storage module 306 further includes: a first storage unit 3061, a second storage unit 3062, and a third storage unit 3063;
the first storage unit 3061, configured to, if the first data block determined by the second determination unit 3054 is obtained by performing division processing on the data to be stored, store the first data block determined by the second determination unit 3054 into the first data storage page from the starting storage location;
a second storage unit 3062, configured to, if the to-be-stored data is divided to obtain the second data block determined by the third determining unit 3055 and the third data block determined by the fourth determining unit 3056, store the second data block determined by the third determining unit 3055 into a first data storage page from the starting storage position, and store the third data block determined by the fourth determining unit 3056 into a second data storage page, where the second data storage page is a data storage page next to the first data storage page;
a third storage unit 3063, configured to, if the data to be stored is divided to obtain the second data block determined by the third determining unit 3055, the third data block determined by the fourth determining unit 3056, and the at least one fourth data block determined by the dividing unit 3057, store the second data block determined by the third determining unit 3055 into the first data storage page from the starting storage position, sequentially store the at least one fourth data block determined by the dividing unit 3057 into at least one third data storage page, and store the third data block determined by the fourth determining unit 3056 into the fourth data storage page, where the at least one third data storage page is located between the first data storage page and the fourth data storage page, the first data storage page is adjacent to one of the third data storage pages, and the fourth data storage page is adjacent to one of the third data storage pages, the third data storage pages are adjacent in sequence.
Or,
the data storage module 306 is further configured to store each data block in sequence into at least one data storage page starting from the first data storage page determined by the first determining module 302 through an I/O port connected to the EEPROM, where each data block corresponds to each data storage page, and any data storage page can only accommodate one data block, and any data block can only be stored into one data storage page.
As shown in fig. 6, an embodiment of the present invention further provides a system for storing data in an EEPROM, including: the main control chip 601 and the target EEPROM memory 602 provided in any of the above embodiments;
and the target EEPROM 602 is configured to store the data to be stored transmitted from the main control chip 601 according to an instruction of the main control chip 601.
Alternatively,
the target EEPROM 602 is connected to the main control chip 601 through an I/O port on the main control chip 601, so as to complete an operation of storing data to be stored according to an instruction of the main control chip 601.
The embodiment of the invention provides a system for storing data to an EEPROM, which comprises a main control chip and a target EEPROM memory. When data needs to be stored in the target EEPROM, the main control chip receives an instruction for indicating the data to be stored in the target EEPROM, calls a general function for writing data into the EEPROM, divides the data to be stored into at least one data block according to the received instruction and the data quantity to be stored in each page of the EEPROM, and finally sequentially stores each data block into the corresponding storage page in the EEPROM, thereby completing the operation of storing the data in the target EEPROM. In the process, the confirmation of the EEPROM model parameters is included, and then the model of the target EEPROM is identified, namely the system can be compatible with various EEPROM memories with different models. Meanwhile, the system for storing data to the EEPROM can also improve the execution efficiency of the main control chip.
In the following, the method for storing data in an EEPROM according to the embodiment of the present invention is further described in detail with reference to the system for storing data in an EEPROM shown in fig. 6, and as shown in fig. 7, the method may include the following steps:
step 701: a data storage instruction for instructing storage of data to the target EEPROM is received.
In the embodiment of the invention, the data storage instruction needs to comprise the model parameter of the EEPROM and the data volume of data needing to be stored in the EEPROM. The model parameters of the EEPROM are defined according to different types of EEPROMs, and the model of the EEPROM compatible with the data storage method comprises the following steps: 24c02, 24c04, 24c08, 24c16, 24c32, 24c 64.
For example, parameter definitions of various models 24c02, 24c04, 24c08, 24c16, 24c32 and 24c64 compatible with the EEPROM correspond to: 0. 1, 2, 3, 4 and 5. When 50 data need to be stored in an EEPROM with the model number of 24c08, the main control chip needs to receive a data storage instruction with the model number parameter of 2 and the first data size of 50.
Step 702: and determining a first data storage page for storing the data to be stored and a starting storage position in the target EEPROM.
In the embodiment of the invention, the first data storage page is a data storage page needing to start to store data to be stored in the target EEPROM, and the initial storage position is a storage position where the data to be stored is started to be stored in the first data storage page in the target EEPROM. The starting storage position is determined by an instruction for writing data into the target EEPROM, can be any position in the target EEPROM and is not limited to the next position of the original last data in the EEPROM.
For example, when data is written into the EEPROM of the model number 24c08, the received start address of data writing into the EEPROM is 18, and it is determined that 16 data can be stored in each page according to the model number 24c08 of the EEPROM, so it is determined that the data to be stored needs to be stored from the 2 nd (first address 0) storage address of the 1 st page (first page 0) in the EEPROM according to the start address of 18, that is, in this example, the first data storage page is the 1 st page, and the start storage address is the 2 nd storage address of the first page.
Step 703: and determining a second data quantity which can be stored in each data storage page of the target EEPROM according to the model parameter.
In the embodiment of the present invention, according to the description of step 701, the model parameters and the model types of the EEPROMs are in one-to-one correspondence, and the model of the EEPROM can be determined by the model parameters, and each model of EEPROM has the data size that can be accommodated by each corresponding storage page.
For example, the data storage method is compatible with the models of EEPROMs including: 24c02, 24c04, 24c08, 24c16, 24c32, 24c 64. The amount of data that can be written by a write operation in the "page write" mode is different according to different EEPROM models, wherein 8 Byte data can be written at a time in the 24c02 type, 16 Byte data can be written at a time in the 24c04, 24c08 and 24c16 types, and 32 Byte data can be written at a time in the 24c32 and 24c64 types, so that if a data storage operation is performed on the 24c08 type EEPROM, the second data amount is 16.
Step 704: and determining a third data volume of the data to be stored which can be stored in the first data storage page according to the second data volume and the initial storage position.
In the embodiment of the invention, the data amount which can be stored in the first data storage page in the data storage operation at this time needs to be calculated according to the maximum data storage amount which can be accommodated by the EEPROM in each storage page and the initial storage position at which the data needs to be stored.
For example, in the example described in step 702 above, the determined address at which the data to be stored starts to be stored is the 2 nd storage address of page 1, and the data amount that can be stored in each page of the memory with the model number of 24c08 is 16, so that the data to be stored in the first storage page is 16- (18-16) ═ 14, that is, the third data amount is 14.
Step 705: and dividing the data to be stored into at least one data block according to the first data volume, the second data volume and the third data volume.
In the embodiment of the invention, firstly, whether the third data volume which can be accommodated in the first data storage page is not less than the first data volume of the data to be stored needs to be judged, if so, the data to be stored can be divided into one data block; if the third data volume is smaller than the first data volume, dividing the data to be stored cached in the cache array into a data block with the data volume equal to the third data volume from the starting address, and then sequentially determining the rest data to be stored as a data block according to the data meeting the second data volume until all the data to be stored are divided into the data blocks, and the data volume of the last data block can be smaller than the second data volume, so that the data to be stored is divided into at least one data block in a memory page mode.
For example: in the received data storage command, the first data volume is 50, the model of the EEPROM is determined to be 24c08, the 50 data are put into a cache Array of consecutive addresses Array [1] to Array [50], and the address where the data start to be stored is the 2 nd storage address of page 1. Therefore, the amount of data that can be stored in the first storage page is 14, so that the data corresponding to the Array [1] to the Array [14] are sequentially determined as one data block, the data corresponding to the Array [15] to the Array [30] are determined as a second data block, the data corresponding to the Array [31] to the Array [46] are determined as a third data block, the data corresponding to the Array [47] to the Array [50] are determined as a fourth data block, and all the data are divided into four data blocks in the manner of the storage page.
Step 706: at least one data block is stored into at least one data storage page in the EEPROM, starting from a first data storage page.
In the embodiment of the invention, the data amount stored in each of the data storage pages except the first data storage page and the second data storage page in at least one data storage page storing the data to be stored is equal to the second data amount, and the second data storage page is the last data storage page storing the data to be stored in the EEPROM.
For example, in the example described in step 705 above, 50 data to be stored are divided into 4 data blocks by the storage pages, the first data block needs to be stored in the first storage page, that is, actually in the 1 st page in the EEPROM, and the second data block, the third data block and the fourth data block are sequentially stored in the 2 nd page, the 3 rd page and the 4 th page in the EEPROM, where the fourth page only occupies four data locations, that is, 0 to 3 four storage locations in the 4 th page.
The embodiment of the invention also provides a readable medium, which comprises an execution instruction, and when a processor of a storage controller executes the execution instruction, the storage controller executes the method for storing data in the EEPROM provided by the above embodiments.
An embodiment of the present invention further provides a storage controller, including: a processor, a memory, and a bus;
the memory is used for storing execution instructions, the processor is connected with the memory through the bus, and when the storage controller runs, the processor executes the execution instructions stored by the memory, so that the storage controller executes the method for storing data to the EEPROM, wherein the method is provided by the storage controller in the way that the above various embodiments are executed.
In summary, the method, the main control chip and the system for storing data in the EEPROM provided by the embodiments of the present invention at least have the following advantages:
1. in the embodiment of the invention, an instruction which comprises a model parameter and a first data amount and is used for indicating the data to be stored in the target EEPROM is received, and then a first data storage page in the target EEPROM for starting to store the data to be stored and a storage position in the first data storage page for starting to store the data to be stored are determined. According to the received model parameters of the target EEPROM, a second data volume which can be contained in each storage page of the target EEPROM is determined, a third data volume which can store the data to be stored in a first data storage page of the EEPROM is determined according to the second data volume and the initial storage position of the data to be stored in the EEPROM, then data block division is carried out on the data to be stored according to the first data volume, the second data volume and the third data volume, and then the divided data blocks are sequentially stored into the corresponding data storage pages. Therefore, in the method for storing data in the EEPROM, the operation of writing data into the EPPROM according to pages is realized by software, and the software can simultaneously and compatibly write data into different types of EEPROMs, thereby ensuring the universality of the method. In addition, when the data written into the EEPROM is more, the time resources occupied by the EEPROM for storing the data can be greatly released, so that the influence on the execution of other programs is reduced, and the execution efficiency of the main control chip is improved.
2. In the embodiment of the present invention, data to be stored is temporarily cached in an array with consecutive addresses, and a start address and an end address of the array need to be determined, then, the size of the first data volume received in step 101 and the size of the third data volume determined in step 104 are compared, if the first data volume is not greater than the third data volume, the data located between the start address and the end address in the cache array is determined as the first data block, that is, the data division is completed; if the first data volume is larger than the third data volume, determining data, of which the data volume from the starting address is equal to the third data volume, in the cache array as a second data block, then sequentially determining data, of which the data volume is equal to or smaller than the second data volume, in the remaining data as one data block, and only the data block data volume where the data corresponding to the termination address is located can be smaller than the second data volume, so that the operation of dividing the data to be stored by the storage page is realized. Therefore, in the whole data block dividing process, the position where the first page of the storage page can start to be stored can be determined according to the first data quantity, and therefore the flexibility of EEPROM data storage is improved. In addition, the whole data dividing operation aims at dividing data according to storage pages in the EEPROM, so that the data can be written into the target EEPROM in a data block mode according to pages.
3. In the embodiment of the invention, the I/O port is connected with the target EEPROM, and each data block is stored in each corresponding storage page in sequence, so that the data to be stored can be stored in the target EEPROM in a page mode through the I/O port only by calling the universal write function through the main control chip, and the execution efficiency of the main control chip is improved while the universality of the method for storing the data in the EEPROM is ensured.
4. The embodiment of the invention provides a system for storing data to an EEPROM, which comprises a main control chip and a target EEPROM memory. When data needs to be stored in the target EEPROM, the main control chip receives an instruction for indicating the data to be stored in the target EEPROM, calls a general function for writing data into the EEPROM, divides the data to be stored into at least one data block according to the received instruction and the data quantity to be stored in each page of the EEPROM, and finally sequentially stores each data block into the corresponding storage page in the EEPROM, thereby completing the operation of storing the data in the target EEPROM. The whole process comprises the confirmation of the EEPROM model parameters, and then the model of the target EEPROM is identified, namely the system can be compatible with various EEPROM memories with different models. Meanwhile, the system for storing data to the EEPROM can also improve the execution efficiency of the main control chip.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of other similar elements in a process, method, article, or apparatus that comprises the element.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it is to be noted that: the above description is only a preferred embodiment of the present invention, and is only used to illustrate the technical solutions of the present invention, and not to limit the protection scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.

Claims (10)

1. The method for storing data to the EEPROM is applied to a main control chip and is characterized by comprising the following steps:
receiving a data storage instruction for indicating to store data to a target EEPROM, wherein the data storage instruction comprises a model parameter and a first data volume, the model parameter is used for indicating the model of the target EEPROM, and the first data volume is used for representing the data volume of the data to be stored;
determining a first data storage page and a starting storage position for storing the data to be stored in the target EEPROM, wherein the first data storage page is a data storage page for starting to store the data to be stored, and the starting storage position is a storage position for starting to store the data to be stored in the first data storage page;
determining a second data volume which can be stored in each data storage page of the target EEPROM according to the model parameter;
determining a third data volume of the data to be stored which can be stored in the first data storage page according to the second data volume and the initial storage position;
dividing the data to be stored into at least one data block according to the first data volume, the second data volume and the third data volume;
and storing the at least one data block into at least one data storage page in the EEPROM from the first data storage page, wherein the amount of data stored in each of the at least one data storage page in which the data to be stored is equal to the second amount of data except for the first data storage page and a second data storage page, and the second data storage page is the last data storage page in the EEPROM in which the data to be stored is stored.
2. The method according to claim 1, wherein the dividing the data to be stored into at least one data block according to the first data amount, the second data amount, and the third data amount comprises:
s201: temporarily caching the data to be stored in a target array with continuous addresses;
s202: determining an array starting address and an array terminating address of the target array, wherein the array starting address is used for identifying a starting position of the data to be stored in the target array, and the array terminating address is used for identifying a terminating position of the data to be stored in the target array;
s203: judging whether the first data volume is smaller than or equal to the third data volume, if so, executing step S204, otherwise, executing step S205;
s204: determining data between the array starting address and the array ending address in the target array as a first data block, and ending the current flow;
s205: determining data in the target array between the array start address and a first data partition address as a second data block, wherein the data amount of the second data block is equal to the third data amount;
s206: determining data between a second data partition address and the array termination address as a third data block, wherein the data amount of the third data block is less than or equal to the second data amount;
s207: and if the first data partition address is different from the second data partition address, sequentially dividing data between the first data partition address and the second data partition address in the target array into at least one fourth data block, wherein the data amount of each fourth data block is equal to the second data amount.
3. The method of claim 2, wherein said storing said at least one data block into at least one data storage page in said EEPROM, starting from said first data storage page, comprises:
if the first data block is obtained by dividing the data to be stored, storing the first data block into the first data storage page from the initial storage position;
if the data to be stored is divided to obtain the second data block and the third data block, storing the second data block into the first data storage page from the initial storage position, and storing the third data block into a second data storage page, wherein the second data storage page is a next data storage page of the first data storage page;
if the data to be stored are divided to obtain the second data block, the third data block and the at least one fourth data block, the second data block is stored into the first data storage page from the initial storage position, the at least one fourth data block is sequentially stored into the at least one third data storage page, and the third data block is stored into a fourth data storage page, wherein the at least one third data storage page is located between the first data storage page and the fourth data storage page, the first data storage page is adjacent to one of the third data storage pages, the fourth data storage page is adjacent to one of the third data storage pages, and the third data storage pages are sequentially adjacent.
4. The method of any of claims 1-3, wherein said storing said at least one block of data into at least one data storage page in said EEPROM starting from said first data storage page, comprises:
and sequentially storing each data block into at least one data storage page starting from the first data storage page through an I/O port connected with the EEPROM, wherein each data block corresponds to each data storage page, any one data storage page can only contain one data block, and any one data block can only be stored into one data storage page.
5. The main control chip, its characterized in that includes: the device comprises a receiving module, a first determining module, a second determining module, a third determining module, a data dividing module and a data storage module;
the receiving module is used for receiving a data storage instruction used for indicating to store data into a target EEPROM, wherein the data storage instruction comprises a model parameter and a first data volume, the model parameter is used for indicating the model of the target EEPROM, and the first data volume is used for representing the data volume of the data to be stored;
the first determining module is configured to determine a first data storage page and a starting storage location for storing the data to be stored in the target EEPROM, where the first data storage page is a data storage page where the data to be stored starts to be stored, and the starting storage location is a storage location where the data to be stored starts to be stored in the first data storage page;
the second determining module is configured to determine, according to the model parameter received by the receiving module, a second data size that can be stored in each data storage page of the target EEPROM;
the third determining module is configured to determine, according to the second data amount determined by the second determining module and the initial storage location determined by the first determining module, a third data amount of the to-be-stored data that can be stored in the first data storage page determined by the first determining module;
the data dividing module is configured to divide the data to be stored into at least one data block according to the first data amount received by the receiving module, the second data amount determined by the determining module, and the third data amount determined by the third determining module;
the data storage module is configured to store the at least one data block divided by the data dividing module into at least one data storage page in the EEPROM starting from the first data storage page determined by the first determining module, where an amount of data stored in each of the at least one data storage page in which the data to be stored is equal to the second data amount determined by the second determining module, except for the first data storage page and the second data storage page determined by the first determining module, and the second data storage page is a last data storage page in the EEPROM in which the data to be stored is stored.
6. The main control chip according to claim 5, wherein the data dividing module comprises: the device comprises a cache unit, a first determining unit, a judging unit, a second determining unit, a third determining unit, a fourth determining unit and a dividing unit;
the cache unit is used for temporarily caching the data to be stored in a target array with continuous addresses;
the first determining unit is configured to determine an array start address and an array end address of the target array, where the array start address is used to identify a start position of the data to be stored in the target array, and the array end address is used to identify an end position of the data to be stored in the target array;
the judging unit is used for judging whether the first data volume is smaller than or equal to the third data volume;
the second determining unit is used for determining data in the target array between the array starting address and the array ending address determined by the first determining unit as a first data block;
the third determining unit is configured to determine data in the target array between the array start address and the first data partition address determined by the first determining unit as a second data block, where a data amount of the second data block is equal to the third data amount;
the fourth determining unit is configured to determine data between a second data partition address and the array termination address determined by the first determining unit as a third data block, where a data amount of the third data block is smaller than or equal to the second data amount;
the dividing unit is configured to, if the first data division address determined by the first determining unit is different from the second data division address determined by the fourth determining unit, sequentially divide data in the target array between the first data division address determined by the first determining unit and the second data division address determined by the fourth determining unit into at least one fourth data block, where the data amount of each fourth data block is equal to the second data amount.
7. The host chip of claim 6, wherein the data storage module comprises: a first storage unit, a second storage unit and a third storage unit;
the first storage unit is configured to store the first data block determined by the second determining unit into the first data storage page from the initial storage location if the first data block determined by the second determining unit is obtained by performing division processing on the data to be stored;
the second storage unit is configured to, if the to-be-stored data is divided to obtain the second data block determined by the third determining unit and the third data block determined by the fourth determining unit, store the second data block determined by the third determining unit into the first data storage page from the starting storage position, and store the third data block determined by the fourth determining unit into a second data storage page, where the second data storage page is a data storage page next to the first data storage page;
the third storage unit is configured to, if the second data block determined by the third determination unit, the third data block determined by the fourth determination unit, and at least one fourth data block determined by the division unit are obtained by dividing the data to be stored, store the second data block determined by the third determination unit into the first data storage page from the starting storage position, sequentially store the at least one fourth data block into at least one third data storage page, and store the third data block determined by the fourth determination unit into a fourth data storage page, where the at least one third data storage page is located between the first data storage page and the fourth data storage page, and the first data storage page is adjacent to one of the third data storage pages, the fourth data storage page is adjacent to one of the third data storage pages, and the third data storage pages are adjacent in sequence.
8. The main control chip according to any one of claims 5 to 7,
the data storage module is further configured to store, through an I/O port connected to the EEPROM, each data block in turn into at least one data storage page starting from the first data storage page determined by the first determining module, where each data block corresponds to each data storage page, and any one data storage page can only accommodate one data block, and any one data block can only store into one data storage page.
9. A system for storing data to an EEPROM, comprising: the master control chip and the target EEPROM of any one of claims 5 to 8;
and the target EEPROM is used for storing the data to be stored transmitted from the main control chip according to the instruction of the main control chip.
10. The system of claim 9,
the target EEPROM is connected with the main control chip through an I/O port on the main control chip so as to finish the operation of storing the data to be stored according to the instruction of the main control chip.
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