CN116893853B - Storage device and processing method of erasing instruction - Google Patents
Storage device and processing method of erasing instruction Download PDFInfo
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- CN116893853B CN116893853B CN202311159662.9A CN202311159662A CN116893853B CN 116893853 B CN116893853 B CN 116893853B CN 202311159662 A CN202311159662 A CN 202311159662A CN 116893853 B CN116893853 B CN 116893853B
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- 238000012545 processing Methods 0.000 claims abstract description 27
- 238000004891 communication Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 10
- 238000013507 mapping Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a storage device and a processing method of an erasing instruction, comprising the following steps: a flash memory block; the cache block is used for storing historical execution task data, wherein the historical execution task data comprises a historical sequence number, a historical starting logical address and a historical ending logical address; the main controller is in communication connection with the flash memory block and the cache block and is used for responding to the current erasing instruction of the host computer to generate current execution task data, wherein the current execution task data comprises a current sequence number, a current starting logic address and a current ending logic address; the master controller is further configured to update the historical execution task data according to a comparison result of the current sequence number and the historical sequence number. By the storage device and the processing method of the erasing instruction, the processing efficiency of the repeated erasing instruction which is not aligned with 4KB can be improved.
Description
Technical Field
The present invention relates to the field of data storage, and in particular, to a storage device and a method for processing an erase command.
Background
After the storage device is used, the flash memory block of the storage device can store partial invalid data. In order to release the storage space of the flash memory block (nand flash) and improve the read-write speed, invalid data of the flash memory block can be deleted through an erase command (trim) sent by a host. Since the host may frequently send repeated and non-4 KB aligned trim instructions, it takes a long time to execute the trim instructions, which easily causes a trim timeout problem. Therefore, there is a need for improvement.
Disclosure of Invention
The invention aims to provide a memory device and a processing method of an erasing instruction, so as to improve the processing efficiency of the erasing instruction which is repeated and is not aligned with 4 KB.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides a storage device comprising:
a flash memory block;
the cache block is used for storing historical execution task data, wherein the historical execution task data comprises a historical sequence number, a historical starting logical address and a historical ending logical address; and
the main controller is in communication connection with the flash memory block and the cache block and is used for responding to the current erasing instruction of the host computer to generate current execution task data, wherein the current execution task data comprises a current sequence number, a current starting logic address and a current ending logic address;
the master controller is further configured to update the historical execution task data according to a comparison result of the current sequence number and the historical sequence number.
In an embodiment of the present invention, when the current sequence number is different from the historical sequence number, the master controller is configured to determine whether the current start logical address and the current end logical address are aligned by 4kb, and update the historical execution task data based on a determination result.
In an embodiment of the present invention, when the current start logical address and the current end logical address are aligned to be 4kb, the master controller performs data erasure processing on the flash memory block according to the current execution task data, and updates the historical execution task data.
In an embodiment of the present invention, when the current start logical address is aligned with a non-4 kb and/or the current end logical address is aligned with a non-4 kb, the master obtains a non-aligned portion of the current start logical address and/or a non-aligned portion of the current end logical address, and updates the history execution task data based on a processing result of the non-aligned portion.
In an embodiment of the present invention, the master controller determines whether the unaligned portion is all 0, and updates the historical execution task data based on a determination result.
In an embodiment of the present invention, when the current sequence number is the same as the historical sequence number, the master controller updates the historical execution task data according to a comparison result of the current start logical address and the historical start logical address and a comparison result of the current end logical address and the historical end logical address.
In an embodiment of the present invention, the master updates the historical execution task data when the current start logical address and the historical start logical address completely overlap, and the current end logical address and the historical end logical address completely overlap.
In an embodiment of the present invention, when the current start logical address overlaps with the history start logical address and/or the current end logical address overlaps with the history end logical address, the master updates the history execution task data according to the non-overlapping portion, and performs a data erase operation on the flash memory block according to the history execution task data.
In an embodiment of the present invention, when the current start logical address and the history start logical address are completely non-overlapping, and the current end logical address and the history end logical address are completely non-overlapping, the master controller determines whether the current start logical address and the current end logical address are aligned with 4kb, and updates the history execution task data based on the determination result.
The invention also provides a processing method of the erasing instruction of the storage device, which comprises the following steps:
responding to a current erasing instruction of a host, generating current execution task data by a main controller, and acquiring corresponding historical execution task data, wherein the current execution task data comprises a current sequence number, a current starting logic address and a current ending logic address, and the historical execution task data comprises a historical sequence number, a historical starting logic address and a historical ending logic address;
updating the historical execution task data according to the comparison result of the current sequence number and the historical sequence number
As described above, the invention provides a memory device and a method for processing an erase command, which can reduce the frequency of reading and writing a flash memory block when processing the erase command which is repeated and is not aligned with 4KB, thereby effectively improving the operation efficiency of the memory device for processing the erase command which is repeated and is not aligned with 4KB, and avoiding the problem of overtime of the erase command.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention;
FIG. 2 is a schematic diagram of different logical addresses of a memory device according to an embodiment of the invention;
FIG. 3 is a flowchart of a method for processing an erase command of a memory device according to an embodiment of the present invention;
FIG. 4 is a flowchart of step S10 in FIG. 3;
FIG. 5 is a flowchart of step S20 in FIG. 3;
FIG. 6 is a flowchart of step S22 in FIG. 5;
FIG. 7 is a flowchart of step S224 in FIG. 6;
fig. 8 is a flowchart of step S23 in fig. 5.
In the figure: 10. a host; 20. a storage device; 21. a master controller; 22. a flash memory block; 23. caching the blocks; 30. a first logical address; 40. a second logical address; 50. and a third logical address.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to FIG. 1, the present invention provides a storage device 20 that can process repeated and non-4 KB aligned erase instructions (trim) issued by a host 10 to avoid trim timeout problems. The host 10 may be an electronic device such as a computer or a telephone. The storage device 20 may be installed in the host 10 to implement a storage function. The storage device 20 may include a master 21, a flash block (nand flash) 22, and a cache block 23. Wherein the master 21 may be communicatively connected to the host 10 to receive instructions from the host 10. The number of the flash memory blocks 22 may be at least one, and the flash memory blocks 22 are subjected to an erase operation in units of blocks. The write operation of the flash block 22 must be performed in a blank area, and if the target area already has data, it must be erased and then written, so the erase operation is the basic operation of the flash block 22. The cache block (Random Access Memory, RAM) 23 refers to a memory that can exchange data at high speed, and exchanges data with the host 10 prior to the flash block 22. The cache block 23 may store therein current execution task data (cur trim task) and history execution task data (last trim task).
Referring to fig. 1, in one embodiment of the present invention, a master 21 may be communicatively coupled to a host 10. When the host 10 transmits a current erase command (trim) to the master 21, the master 21 can respond to the current erase command and generate corresponding current execution task data. The currently executing task data may be represented as a current erase command sent by the host 10 as a task node, which may include a current sequence number (serial no), a current start logical address (trim start lba), and a current end logical address (trim end lba). The current sequence number may include a current read data sequence number and a current write data sequence number. The current read data sequence number may be expressed as a point in time when the current data is read, and is updated/accumulated each time the data in the flash block 22 is read. The current write data sequence number may be represented as a point in time when the current data is written, and is updated/accumulated each time the data in the flash block 22 is written. That is, each time data in the flash block 22 is read/written, the current sequence number is updated/accumulated accordingly. After each update/accumulation, the current sequence number will increase accordingly. The larger the current sequence number, the more recently issued by the host 10, and the smaller the current sequence number, the more previously issued by the host 10. The current start logical address may be represented as the start logical address at which the host 10 sends the current erase instruction. The current end logical address may be represented as the end logical address at which the host 10 sends the current erase instruction.
Referring to fig. 1, in one embodiment of the present invention, after the master 21 generates the current execution task data, the master 21 may read the cache block 23 to obtain the corresponding historical execution task data. The data structure of the historically performed task data may be the same as the data structure of the currently performed task data. The history execution task data may be expressed as a task node including a history sequence number, a history start logical address, and a history end logical address, which is a last erase instruction sent by the host 10. The historical sequence numbers may include historical read data sequence numbers and historical write data sequence numbers. The historical read data sequence number may be expressed as the point in time of the last data read. The history start logical address may be expressed as the start logical address at which the host 10 sent the last erase instruction. The history of ending logical addresses may be represented as the ending logical address of the last erase command sent by the host 10.
Referring to fig. 1, in an embodiment of the present invention, after the master controller 21 obtains the current execution task data and the historical execution task data, the historical execution task data may be updated according to the comparison result of the current sequence number and the historical sequence number. Specifically, the master controller 21 may determine whether the current sequence number is the same as the history sequence number. Namely, whether the current read data sequence number is the same as the historical read data sequence number or not and whether the current write data sequence number is the same as the historical write data sequence number or not is judged. When the master 21 determines that the current sequence number is different from the historical sequence number, i.e., the current read data sequence number is different from the historical read data sequence number and/or the current write data sequence number is different from the historical write data sequence number. The main controller 21 may determine whether the current start logical address and the current end logical address are aligned to 4kb, and update the history execution task data based on the determination result. When the master controller 21 determines that the current sequence number is the same as the history sequence number, that is, the current read data sequence number is the same as the history read data sequence number, the current write data sequence number is the same as the history write data sequence number. The master controller 21 may update the historical execution task data according to the comparison result of the current start logical address and the historical start logical address and the comparison result of the current end logical address and the historical end logical address.
In one embodiment of the present invention, when the current sequence number is different from the historical sequence number, the master 21 may determine whether the current start logical address and the current end logical address are aligned by 4 kb. The host logical address (host lba) is expressed in units of sectors (sectors), and the size of the sectors may be expressed as 512bytes, and 4KB corresponds to 8 sectors, so when host lba can be divided by 8, it may be expressed as that host lba is aligned as 4 KB. Specifically, when the current start logical address and the current end logical address are aligned to be 4kb, the main controller 21 is configured to perform data erasure processing on the flash memory block 22 according to the current execution task data, and update the historical execution task data. When the current start logical address and/or the current end logical address are aligned with non-4 kb, the main controller 21 is configured to obtain a non-aligned portion of the current start logical address and/or the current end logical address, and update the historical execution task data based on a processing result of the non-aligned portion.
In one embodiment of the present invention, the master 21 may perform a data erasure process on the flash memory block 22 according to the current execution task data and update the history execution task data. Specifically, the master controller 21 queries the address mapping table, and modifies the address mapping table accordingly according to the current execution task data. Wherein the address mapping table may be represented as a table of host logical addresses corresponding to device physical addresses. In the process of modifying the address mapping table, when the host 10 needs to erase the logical block address (Logical Block Address, lba) aligned with 4KB, the logical block address needs to be stored in the address mapping table, and the device physical address corresponding to the logical block address is modified to an invalid value. At this time, the master controller 21 may erase the invalid data in the flash memory block 22 according to the invalid value in the address mapping table, so as to release the storage space in the flash memory block 22. Meanwhile, the master 21 may update the history execution task data according to the current execution task data. For example, the history execution task data stored in the cache block 23 may be deleted, and the current execution task data may be stored in the cache block 23 to form new history execution task data.
In one embodiment of the present invention, the master 21 is configured to obtain a non-aligned portion of the current start logical address and/or a non-aligned portion of the current end logical address, and update the historical execution task data based on a processing result of the non-aligned portion. Specifically, the master 21 may read the unaligned portion of the current starting logical address and/or the unaligned portion of the current ending logical address from the flash memory block 22, and determine whether the unaligned portion is all 0's. When the master 21 judges that the unaligned portion is all 0, it is indicated that the unaligned portion has been processed by the erase instruction (trim) without continuing the processing. The master 21 may update the history execution task data according to the current execution task data. When the master 21 determines that the unaligned portion is not all 0 s, it may be indicated that the unaligned portion has not been processed by the erase instruction (trim). At this time, the data patch process is required for the non-aligned portion. After the current start logical address completes data filling and/or the current end logical address completes data filling, the main controller 21 may perform data erasing processing on the flash memory block 22 according to the current execution task data, and erase invalid data in the flash memory block 22 to release the storage space in the flash memory block 22. Meanwhile, the master 21 may update the history execution task data according to the current execution task data. The sector logical address (trim lba) is assumed to be 1, and the trim length is also 1, and the trim range can be expressed as lba 1-lba 2. Since the address mapping table of the memory device 20 is managed by 4KB, the process of reading lba 0-lba 7 to form a complete 4KB can be expressed as a data filling process.
In one embodiment of the present invention, when the master controller 21 determines that the current sequence number is the same as the history sequence number, the master controller 21 may determine whether the current start logical address overlaps with the history start logical address, and whether the current end logical address overlaps with the history end logical address, and update the history execution task data according to the determination result.
In one embodiment of the present invention, the historical execution task data is updated when the current start logical address fully overlaps the historical start logical address and the current end logical address fully overlaps the historical end logical address. Specifically, it may be indicated that the currently executed task data is within the range of the historically executed task data at this time, and the invalid data that needs to be deleted for the currently executed task data has been deleted by the historically executed task data. At this time, the current execution task data may be directly deleted, or the current execution task data may be stored in the history execution task data, so as to complete updating of the history execution task data.
In one embodiment of the present invention, when the current start logical address partially overlaps the history start logical address and/or the current end logical address partially overlaps the history end logical address, the history execution task data is updated according to the non-overlapping portion, and the data erase operation is performed on the flash memory block 22 according to the history execution task data. Specifically, when the current start logical address and the history start logical address are partially overlapped, a non-overlapped part on the current start logical address may be obtained. When the current ending logical address and the historical ending logical address are partially overlapped, a non-overlapping part on the current ending logical address can be obtained. After the non-overlapping portion on the current starting logical address and/or the non-overlapping portion on the current ending logical address is obtained, the non-overlapping portion may be integrated into the historical starting logical address and/or the historical ending logical address to update the historical execution task data. And erasing invalid data in the flash memory block 22 according to the updated historical execution task data so as to release the storage space in the flash memory block 22. Meanwhile, the updated history execution task data may be stored in the cache block 23.
In one embodiment of the present invention, when the current start logical address and the historical start logical address, and the current end logical address and the historical end logical address are not overlapped at all, it is determined whether the current start logical address and the current end logical address are aligned with 4kb, so as to update the historical execution task data. Specifically, when the two addresses do not overlap, the main controller 21 repeatedly determines whether the current start logical address and the current end logical address are aligned by 4kb, so as to update the history execution task data according to the determination result.
Referring to fig. 2, in an embodiment of the present invention, in the process of determining whether the logical addresses overlap by the master 21, for example, the first logical address 30 may be represented as 1st Host Trim Area, the second logical address 40 may be represented as 2cd Host Trim Area, and the third logical address 50 may be represented as 3rd Host Trim Area. It can be seen that the start logical address of the second logical address 40 is within the start logical address range of the first logical address 30 and the end logical address of the second logical address 40 is also within the end logical address range of the first logical address 30. Therefore, when the first logical address 30 is used as the history execution task data and the second logical address 40 is used as the current execution task data, it may be indicated that the current execution task data is within the range of the history execution task data. The starting logical address of the third logical address 50 is within the starting logical address range of the first logical address 30 and the ending logical address of the third logical address 50 is not within the ending logical address range of the first logical address 30. That is, the ending logical address of the third logical address 50 does not completely overlap with the ending logical address of the first logical address 30. Therefore, when the first logical address 30 is used as the history execution task data and the third logical address 50 is used as the current execution task data, this may be expressed as when the current execution task data partially overlaps with the history execution task data. A non-overlapping portion of the ending logical address of the third logical address 50 may be obtained and integrated into the historical ending logical address to update the historical execution task data.
Referring to fig. 3, the present invention further provides a method for processing an erase command of a storage device, which can be applied to the storage device 20 in the above embodiment to process a repeated erase command that is not aligned by 4KB and is issued by the host 10, so as to avoid a trim timeout problem. The processing method of the storage device erasing instruction can comprise the following steps:
step S10, responding to a current erasing instruction of a host, generating current execution task data by a main controller, and acquiring corresponding historical execution task data, wherein the current execution task data comprises a current sequence number, a current starting logic address and a current ending logic address, and the historical execution task data comprises a historical sequence number, a historical starting logic address and a historical ending logic address;
step S20, updating the historical execution task data according to the comparison result of the current sequence number and the historical sequence number;
and step S30, performing data erasure processing on the flash memory block according to the historical execution task data, and storing the historical execution task data in the cache block.
Referring to fig. 4, in one embodiment of the present invention, when step S10 is performed, specifically, step S10 may include the following steps:
step S11, responding to a current erasing instruction of a host, and analyzing the current erasing instruction by a main controller to generate a current starting logical address and a current ending logical address;
step S12, acquiring a current sequence number according to the current erasing instruction, and generating current execution task data according to a current starting logical address, a current ending logical address and the current sequence number;
step S13, acquiring historical execution task data, wherein the historical execution task data comprises a historical sequence number, a historical starting logical address and a historical ending logical address.
In one embodiment of the present invention, when performing steps S11 and S12, specifically, when the host 10 transmits a current erase command to the host 21, the host 21 can respond to the current erase command and generate corresponding current execution task data. The currently executing task data may be represented as a current erase command sent by the host 10 as a task node, which may include a current sequence number, a current start logical address, and a current end logical address.
In one embodiment of the present invention, when step S13 is performed, specifically, after the master 21 generates the current execution task data, the master 21 may read the cache block 23 to obtain the corresponding historical execution task data. The data structure of the historically performed task data may be the same as the data structure of the currently performed task data. The history execution task data may be expressed as a task node including a history sequence number, a history start logical address, and a history end logical address, which is a last erase instruction sent by the host 10.
Referring to fig. 5, in one embodiment of the present invention, when step S20 is performed, specifically, step S20 may include the following steps:
step S21, judging whether the current sequence number is the same as the historical sequence number;
step S22, when the historical execution task data are different, updating the historical execution task data;
and S23, when the current start logical address and the historical start logical address are the same, updating the historical execution task data according to the comparison result of the current end logical address and the historical end logical address.
In one embodiment of the present invention, when step S21 is performed, specifically, the current sequence number may include the current read data sequence number and the current write data sequence number. The current read data sequence number may be expressed as a point in time when the current data is read, and is updated/accumulated each time the data in the flash block 22 is read. The current write data sequence number may be represented as a point in time when the current data is written, and is updated/accumulated each time the data in the flash block 22 is written. The historical sequence numbers may include a historical read data sequence number and a historical write data sequence number. The historical read data sequence number may be expressed as the point in time of the last data read. The history start logical address may be expressed as the start logical address at which the host 10 sent the last erase instruction. The history of ending logical addresses may be represented as the ending logical address of the last erase command sent by the host 10. The master 21 can determine whether the current sequence number is the same as the history sequence number. Namely, whether the current read data sequence number is the same as the historical read data sequence number or not and whether the current write data sequence number is the same as the historical write data sequence number or not is judged.
Referring to fig. 6, in one embodiment of the present invention, when step S22 is performed, specifically, step S22 may include the following steps:
step S221, judging whether the current start logical address and the current end logical address are aligned with 4 kb;
step S222, when the current initial logical address and the current ending logical address are aligned to be 4kb, performing data erasure processing on the flash memory block according to the current execution task data, and updating the historical execution task data;
step S223, when the current initial logical address is aligned with non-4 kb and/or the current ending logical address is aligned with non-4 kb, a non-aligned part of the current initial logical address and/or a non-aligned part of the current ending logical address are obtained;
step S224, the non-aligned portion is processed to update the history execution task data.
In one embodiment of the present invention, when step S22 is performed, specifically, when the current sequence number is different from the history sequence number, the master 21 may determine whether the current start logical address and the current end logical address are aligned by 4 kb. When the current start logical address and the current end logical address are aligned to be 4kb, the main controller 21 is configured to perform data erasure processing on the flash memory block 22 according to the current execution task data, and update the historical execution task data. When the current start logical address is aligned with non-4 kb and/or the current end logical address is aligned with non-4 kb, the main controller 21 is configured to obtain a non-aligned portion of the current start logical address and/or a non-aligned portion of the current end logical address, and update the history execution task data based on a result of processing the non-aligned portion.
Referring to fig. 7, in one embodiment of the present invention, when step S224 is performed, specifically, step S224 may include the following steps:
step S2241, judging whether the non-aligned part is all 0;
step S2242, when the data is all 0, updating the history execution task data;
step S2243, when the data is not all 0, the data is subjected to data filling processing, the flash memory block is subjected to data erasing processing according to the current execution task data, and the history execution task data is updated.
In one embodiment of the present invention, when step S224 is performed, specifically, the master controller 21 is configured to obtain a non-aligned portion of the current start logical address and/or a non-aligned portion of the current end logical address, and update the historical execution task data based on a processing result of the non-aligned portion. Specifically, the master 21 may read the unaligned portion of the current starting logical address and/or the unaligned portion of the current ending logical address from the flash memory block 22, and determine whether the unaligned portion is all 0's. When the master 21 judges that the unaligned portion is all 0, it is indicated that the unaligned portion has been processed by the erase instruction (trim) without continuing the processing. The master 21 may update the history execution task data according to the current execution task data. When the master 21 determines that the unaligned portion is not all 0 s, it may be indicated that the unaligned portion has not been processed by the erase instruction (trim). At this time, the data patch process is required for the non-aligned portion. After the current start logical address completes data filling and/or the current end logical address completes data filling, the main controller 21 may perform data erasing processing on the flash memory block 22 according to the current execution task data, and erase invalid data in the flash memory block 22 to release the storage space in the flash memory block 22. Meanwhile, the master 21 may update the history execution task data according to the current execution task data.
Referring to fig. 8, in one embodiment of the present invention, when step S23 is performed, specifically, step S23 may include the following steps:
step S231, judging whether the current initial logical address and the historical initial logical address are overlapped or not, and judging whether the current ending logical address and the historical ending logical address are overlapped or not;
step S232, when the current initial logical address and the historical initial logical address are completely overlapped and the current ending logical address and the historical ending logical address are completely overlapped, updating the historical execution task data;
step S233, when the current initial logical address and the historical initial logical address are partially overlapped and/or the current ending logical address and the historical ending logical address are partially overlapped, updating the historical execution task data according to the non-overlapped part, and performing data erasing operation on the flash memory block according to the historical execution task data;
step S234, when the current start logical address and the history start logical address are completely non-overlapping and the current end logical address and the history end logical address are completely non-overlapping, determining whether the current start logical address and the current end logical address are aligned to be 4kb, so as to update the history execution task data.
In one embodiment of the present invention, when step S231 and step S232 are performed, specifically, when the master controller 21 determines that the current sequence number is the same as the historical sequence number, the master controller 21 may determine whether the current start logical address overlaps with the historical start logical address, whether the current end logical address overlaps with the historical end logical address, and update the historical execution task data according to the determination result. And updating the historical execution task data when the current start logical address and the historical start logical address are completely overlapped and the current end logical address and the historical end logical address are completely overlapped. Specifically, it may be indicated that the currently executed task data is within the range of the historically executed task data at this time, and the invalid data that needs to be deleted for the currently executed task data has been deleted by the historically executed task data. At this time, the current execution task data may be directly deleted, or the current execution task data may be stored in the history execution task data, so as to complete updating of the history execution task data.
In one embodiment of the present invention, when step S233 is performed, specifically, when the current start logical address and the history start logical address partially overlap and/or the current end logical address and the history end logical address partially overlap, the history execution task data is updated according to the non-overlapping portion, and the data erase operation is performed on the flash memory block 22 according to the history execution task data. Specifically, when the current start logical address and the history start logical address are partially overlapped, a non-overlapped part on the current start logical address may be obtained. When the current ending logical address and the historical ending logical address are partially overlapped, a non-overlapping part on the current ending logical address can be obtained. After the non-overlapping portion on the current starting logical address and/or the non-overlapping portion on the current ending logical address is obtained, the non-overlapping portion may be integrated into the historical starting logical address and/or the historical ending logical address to update the historical execution task data. And erasing invalid data in the flash memory block 22 according to the updated historical execution task data so as to release the storage space in the flash memory block 22. Meanwhile, the updated history execution task data may be stored in the cache block 23.
In one embodiment of the present invention, when step S234 is performed, specifically, when the current start logical address and the history start logical address are not overlapped at all and the current end logical address and the history end logical address are not overlapped at all, it is determined whether the current start logical address and the current end logical address are aligned by 4kb, so as to update the history execution task data. Specifically, when the two addresses do not overlap, the main controller 21 repeatedly determines whether the current start logical address and the current end logical address are aligned by 4kb, so as to update the history execution task data according to the determination result.
In one embodiment of the present invention, when step S30 is performed, specifically, after the update of the historical execution task data is completed, the invalid data in the flash memory block 22 may be deleted according to the historical execution task data, and the updated historical execution task data may be stored in the cache block 23.
Therefore, in the scheme, when the storage device processes the repeated and non-4 KB aligned erasure instructions, the frequency of reading and writing the flash memory blocks can be reduced, so that the operation efficiency of the storage device for processing the repeated and non-4 KB aligned erasure instructions is effectively improved, and the problem of overtime of the erasure instructions is not caused.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (8)
1. A memory device, comprising:
a flash memory block;
the cache block is used for storing historical execution task data, wherein the historical execution task data comprises a historical sequence number, a historical starting logical address and a historical ending logical address; and
the main controller is in communication connection with the flash memory block and the cache block and is used for responding to the current erasing instruction of the host computer to generate current execution task data, wherein the current execution task data comprises a current sequence number, a current starting logic address and a current ending logic address;
the master controller is further configured to update the historical execution task data according to a comparison result of the current sequence number and the historical sequence number;
when the current sequence number is different from the historical sequence number, the master controller is used for judging whether the current starting logical address and the current ending logical address are aligned with 4kb or not, and updating the historical execution task data based on a judging result;
when the current sequence number is the same as the historical sequence number, the master controller updates the historical execution task data according to the comparison result of the current start logic address and the historical start logic address and the comparison result of the current end logic address and the historical end logic address.
2. The memory device of claim 1, wherein the master performs a data erase process on a flash block according to currently executed task data and updates the historically executed task data when the current start logical address is aligned with the current end logical address by 4 kb.
3. The storage device according to claim 1, wherein when the current start logical address is not 4kb aligned and/or the current end logical address is not 4kb aligned, the master obtains a non-aligned portion of the current start logical address and/or a non-aligned portion of the current end logical address, and updates the history execution task data based on a result of processing of the non-aligned portion.
4. The memory device according to claim 3, wherein the main controller judges whether the unaligned portion is all 0, and updates the history execution task data based on a result of the judgment.
5. The memory device of claim 1, wherein the master updates the historical execution task data when the current start logical address completely overlaps the historical start logical address and the current end logical address completely overlaps the historical end logical address.
6. The memory device of claim 1, wherein the master updates the history execution task data according to a non-overlapping portion and performs a data erase operation on a flash block according to the history execution task data when the current start logical address partially overlaps the history start logical address and/or the current end logical address partially overlaps the history end logical address.
7. The memory device according to claim 1, wherein when the current start logical address and the history start logical address are not overlapped at all and the current end logical address and the history end logical address are not overlapped at all, the main controller judges whether the current start logical address and the current end logical address are aligned at 4kb or not, and updates the history execution task data based on the judgment result.
8. A method for processing an erase command of a storage device, comprising:
responding to a current erasing instruction of a host, generating current execution task data by a main controller, and acquiring corresponding historical execution task data, wherein the current execution task data comprises a current sequence number, a current starting logic address and a current ending logic address, and the historical execution task data comprises a historical sequence number, a historical starting logic address and a historical ending logic address;
updating the historical execution task data according to the comparison result of the current sequence number and the historical sequence number;
when the current sequence number is different from the historical sequence number, the master controller is used for judging whether the current starting logical address and the current ending logical address are aligned with 4kb or not, and updating the historical execution task data based on a judging result;
when the current sequence number is the same as the historical sequence number, the master controller updates the historical execution task data according to the comparison result of the current start logic address and the historical start logic address and the comparison result of the current end logic address and the historical end logic address.
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